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authorKyungmin Park <kyungmin.park@samsung.com>2007-12-10 21:13:18 -0500
committerKyungmin Park <kyungmin.park@samsung.com>2008-01-29 03:10:28 -0500
commitb21b72cf33bb212414c1d967850e261b795befa4 (patch)
treef7f3942a02f7742f425c7966b2759faffccdd73d /drivers/mtd
parent9d2f0b7a3de28d06ba4011b835b9a7e772553f0d (diff)
[MTD] [OneNAND] Consolidate OneNAND operation order
Consolidate OneNAND operation order as OneNAND Spec. It also doesn't break previous operation order. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/onenand/onenand_base.c19
1 files changed, 4 insertions, 15 deletions
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 799bb1bc3dbc..c79bc2ef3f50 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -182,8 +182,7 @@ static int onenand_buffer_address(int dataram1, int sectors, int count)
182static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len) 182static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len)
183{ 183{
184 struct onenand_chip *this = mtd->priv; 184 struct onenand_chip *this = mtd->priv;
185 int value, readcmd = 0, block_cmd = 0; 185 int value, block, page;
186 int block, page;
187 186
188 /* Address translation */ 187 /* Address translation */
189 switch (cmd) { 188 switch (cmd) {
@@ -198,7 +197,6 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le
198 case ONENAND_CMD_ERASE: 197 case ONENAND_CMD_ERASE:
199 case ONENAND_CMD_BUFFERRAM: 198 case ONENAND_CMD_BUFFERRAM:
200 case ONENAND_CMD_OTP_ACCESS: 199 case ONENAND_CMD_OTP_ACCESS:
201 block_cmd = 1;
202 block = (int) (addr >> this->erase_shift); 200 block = (int) (addr >> this->erase_shift);
203 page = -1; 201 page = -1;
204 break; 202 break;
@@ -240,11 +238,9 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le
240 value = onenand_block_address(this, block); 238 value = onenand_block_address(this, block);
241 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); 239 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
242 240
243 if (block_cmd) { 241 /* Select DataRAM for DDP */
244 /* Select DataRAM for DDP */ 242 value = onenand_bufferram_address(this, block);
245 value = onenand_bufferram_address(this, block); 243 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
246 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
247 }
248 } 244 }
249 245
250 if (page != -1) { 246 if (page != -1) {
@@ -256,7 +252,6 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le
256 case ONENAND_CMD_READ: 252 case ONENAND_CMD_READ:
257 case ONENAND_CMD_READOOB: 253 case ONENAND_CMD_READOOB:
258 dataram = ONENAND_SET_NEXT_BUFFERRAM(this); 254 dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
259 readcmd = 1;
260 break; 255 break;
261 256
262 default: 257 default:
@@ -273,12 +268,6 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le
273 /* Write 'BSA, BSC' of DataRAM */ 268 /* Write 'BSA, BSC' of DataRAM */
274 value = onenand_buffer_address(dataram, sectors, count); 269 value = onenand_buffer_address(dataram, sectors, count);
275 this->write_word(value, this->base + ONENAND_REG_START_BUFFER); 270 this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
276
277 if (readcmd) {
278 /* Select DataRAM for DDP */
279 value = onenand_bufferram_address(this, block);
280 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
281 }
282 } 271 }
283 272
284 /* Interrupt clear */ 273 /* Interrupt clear */