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authorRafał Miłecki <zajec5@gmail.com>2012-11-23 01:51:31 -0500
committerArtem Bityutskiy <artem.bityutskiy@linux.intel.com>2012-12-03 09:36:51 -0500
commite7e46168bcc768fa31628d3d080ac9ee7b553b56 (patch)
treeeb6502bb677497a0ad35ad6f02807fdac266b1fd /drivers/mtd
parent6a8214aa3d323d2e185523ea112116759bc3c5ce (diff)
mtd: bcm47xxnflash: define some magic numbers
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c31
1 files changed, 20 insertions, 11 deletions
diff --git a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
index e42e18208abc..672dc90aa5b1 100644
--- a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
+++ b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
@@ -22,6 +22,15 @@
22 22
23#define NFLASH_SECTOR_SIZE 512 23#define NFLASH_SECTOR_SIZE 512
24 24
25#define NCTL_CMD0 0x00010000
26#define NCTL_CMD1W 0x00080000
27#define NCTL_READ 0x00100000
28#define NCTL_SPECADDR 0x01000000
29#define NCTL_READY 0x04000000
30#define NCTL_ERR 0x08000000
31#define NCTL_CSA 0x40000000
32#define NCTL_START 0x80000000
33
25/************************************************** 34/**************************************************
26 * Various helpers 35 * Various helpers
27 **************************************************/ 36 **************************************************/
@@ -35,9 +44,9 @@ static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
35{ 44{
36 int i = 0; 45 int i = 0;
37 46
38 bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, 0x80000000 | code); 47 bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, NCTL_START | code);
39 for (i = 0; i < NFLASH_READY_RETRIES; i++) { 48 for (i = 0; i < NFLASH_READY_RETRIES; i++) {
40 if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & 0x80000000)) { 49 if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_START)) {
41 i = 0; 50 i = 0;
42 break; 51 break;
43 } 52 }
@@ -54,7 +63,7 @@ static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc)
54 int i; 63 int i;
55 64
56 for (i = 0; i < NFLASH_READY_RETRIES; i++) { 65 for (i = 0; i < NFLASH_READY_RETRIES; i++) {
57 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & 0x04000000) { 66 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_READY) {
58 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & 67 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) &
59 BCMA_CC_NFLASH_CTL_ERR) { 68 BCMA_CC_NFLASH_CTL_ERR) {
60 pr_err("Error on polling\n"); 69 pr_err("Error on polling\n");
@@ -99,8 +108,8 @@ static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
99 b47n->curr_page_addr); 108 b47n->curr_page_addr);
100 109
101 /* Prepare to read */ 110 /* Prepare to read */
102 ctlcode = 0x40000000 | 0x00080000 | 0x00040000 | 0x00020000 | 111 ctlcode = NCTL_CSA | NCTL_CMD1W | 0x00040000 | 0x00020000 |
103 0x00010000; 112 NCTL_CMD0;
104 ctlcode |= NAND_CMD_READSTART << 8; 113 ctlcode |= NAND_CMD_READSTART << 8;
105 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) 114 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode))
106 return; 115 return;
@@ -109,9 +118,9 @@ static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
109 118
110 /* Eventually read some data :) */ 119 /* Eventually read some data :) */
111 for (i = 0; i < toread; i += 4, dest++) { 120 for (i = 0; i < toread; i += 4, dest++) {
112 ctlcode = 0x40000000 | 0x30000000 | 0x00100000; 121 ctlcode = NCTL_CSA | 0x30000000 | NCTL_READ;
113 if (i == toread - 4) /* Last read goes without that */ 122 if (i == toread - 4) /* Last read goes without that */
114 ctlcode &= ~0x40000000; 123 ctlcode &= ~NCTL_CSA;
115 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, 124 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
116 ctlcode)) 125 ctlcode))
117 return; 126 return;
@@ -160,7 +169,7 @@ static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
160 pr_warn("Chip reset not implemented yet\n"); 169 pr_warn("Chip reset not implemented yet\n");
161 break; 170 break;
162 case NAND_CMD_READID: 171 case NAND_CMD_READID:
163 ctlcode = 0x40000000 | 0x01000000 | 0x00080000 | 0x00010000; 172 ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0;
164 ctlcode |= NAND_CMD_READID; 173 ctlcode |= NAND_CMD_READID;
165 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) { 174 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) {
166 pr_err("READID error\n"); 175 pr_err("READID error\n");
@@ -168,14 +177,14 @@ static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
168 } 177 }
169 178
170 /* 179 /*
171 * Reading is specific, last one has to go without 0x40000000 180 * Reading is specific, last one has to go without NCTL_CSA
172 * bit. We don't know how many reads NAND subsystem is going 181 * bit. We don't know how many reads NAND subsystem is going
173 * to perform, so cache everything. 182 * to perform, so cache everything.
174 */ 183 */
175 for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) { 184 for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) {
176 ctlcode = 0x40000000 | 0x00100000; 185 ctlcode = NCTL_CSA | NCTL_READ;
177 if (i == ARRAY_SIZE(b47n->id_data) - 1) 186 if (i == ARRAY_SIZE(b47n->id_data) - 1)
178 ctlcode &= ~0x40000000; 187 ctlcode &= ~NCTL_CSA;
179 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, 188 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
180 ctlcode)) { 189 ctlcode)) {
181 pr_err("READID error\n"); 190 pr_err("READID error\n");