aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/mtd
diff options
context:
space:
mode:
authorKyungmin Park <kyungmin.park@samsung.com>2010-09-27 03:25:17 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2010-10-24 19:50:09 -0400
commitebe8a642f50a0020bed317afcde1f9d2a9da429b (patch)
tree0bfc44174459b60ae434f35157b597fe3eced428 /drivers/mtd
parent12a40a57f762f569f58a393437d8c13864db390a (diff)
mtd: OneNAND: S5PC110: Add timeout to prevent the endless loop
There's no case timeout but add it for some H/W problem or wrong codes implementation Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/onenand/samsung.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c
index 7913a921b08b..b80128036a28 100644
--- a/drivers/mtd/onenand/samsung.c
+++ b/drivers/mtd/onenand/samsung.c
@@ -535,6 +535,7 @@ static int s5pc110_dma_ops(void *dst, void *src, size_t count, int direction)
535{ 535{
536 void __iomem *base = onenand->dma_addr; 536 void __iomem *base = onenand->dma_addr;
537 int status; 537 int status;
538 unsigned long timeout;
538 539
539 writel(src, base + S5PC110_DMA_SRC_ADDR); 540 writel(src, base + S5PC110_DMA_SRC_ADDR);
540 writel(dst, base + S5PC110_DMA_DST_ADDR); 541 writel(dst, base + S5PC110_DMA_DST_ADDR);
@@ -552,6 +553,13 @@ static int s5pc110_dma_ops(void *dst, void *src, size_t count, int direction)
552 553
553 writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD); 554 writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
554 555
556 /*
557 * There's no exact timeout values at Spec.
558 * In real case it takes under 1 msec.
559 * So 20 msecs are enough.
560 */
561 timeout = jiffies + msecs_to_jiffies(20);
562
555 do { 563 do {
556 status = readl(base + S5PC110_DMA_TRANS_STATUS); 564 status = readl(base + S5PC110_DMA_TRANS_STATUS);
557 if (status & S5PC110_DMA_TRANS_STATUS_TE) { 565 if (status & S5PC110_DMA_TRANS_STATUS_TE) {
@@ -559,7 +567,8 @@ static int s5pc110_dma_ops(void *dst, void *src, size_t count, int direction)
559 base + S5PC110_DMA_TRANS_CMD); 567 base + S5PC110_DMA_TRANS_CMD);
560 return -EIO; 568 return -EIO;
561 } 569 }
562 } while (!(status & S5PC110_DMA_TRANS_STATUS_TD)); 570 } while (!(status & S5PC110_DMA_TRANS_STATUS_TD) &&
571 time_before(jiffies, timeout));
563 572
564 writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD); 573 writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD);
565 574