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authorLinus Torvalds <torvalds@linux-foundation.org>2013-03-18 11:27:41 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-03-18 11:27:41 -0400
commit35f8c769aa5f3d9a81d50e9bdcbfd4151e72a0c9 (patch)
tree5541f88e5da4df063e53bcf841217d7c79d9aec4 /drivers/mtd
parent4b767155ffad4be0aaafeead585ad21375dc7475 (diff)
parent5bc7c33ca93a285dcfe7b7fd64970f6314440ad1 (diff)
Merge tag 'for-linus-20130318' of git://git.infradead.org/linux-mtd
Pull MTD fixes from David Woodhouse: "This fixes a couple of problems. Firstly, some people are actually still using old small-page flash and we broke it by removing the ready check. Secondly. fix the handling of partitions on Broadcom 47xx devices. Recent changes had made it misdetect the location of the NVRAM and scribble over the bootloader when it tried to update the variables there. With predictably sad results." * tag 'for-linus-20130318' of git://git.infradead.org/linux-mtd: mtd: nand: reintroduce NAND_NO_READRDY as NAND_NEED_READRDY mtd: bcm47xxpart: look for NVRAM at the end of device Revert "mtd: bcm47xxpart: improve probing of nvram partition"
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/bcm47xxpart.c52
-rw-r--r--drivers/mtd/nand/nand_base.c16
-rw-r--r--drivers/mtd/nand/nand_ids.c80
3 files changed, 90 insertions, 58 deletions
diff --git a/drivers/mtd/bcm47xxpart.c b/drivers/mtd/bcm47xxpart.c
index 63feb75cc8e0..9279a9174f84 100644
--- a/drivers/mtd/bcm47xxpart.c
+++ b/drivers/mtd/bcm47xxpart.c
@@ -19,6 +19,12 @@
19/* 10 parts were found on sflash on Netgear WNDR4500 */ 19/* 10 parts were found on sflash on Netgear WNDR4500 */
20#define BCM47XXPART_MAX_PARTS 12 20#define BCM47XXPART_MAX_PARTS 12
21 21
22/*
23 * Amount of bytes we read when analyzing each block of flash memory.
24 * Set it big enough to allow detecting partition and reading important data.
25 */
26#define BCM47XXPART_BYTES_TO_READ 0x404
27
22/* Magics */ 28/* Magics */
23#define BOARD_DATA_MAGIC 0x5246504D /* MPFR */ 29#define BOARD_DATA_MAGIC 0x5246504D /* MPFR */
24#define POT_MAGIC1 0x54544f50 /* POTT */ 30#define POT_MAGIC1 0x54544f50 /* POTT */
@@ -57,17 +63,15 @@ static int bcm47xxpart_parse(struct mtd_info *master,
57 struct trx_header *trx; 63 struct trx_header *trx;
58 int trx_part = -1; 64 int trx_part = -1;
59 int last_trx_part = -1; 65 int last_trx_part = -1;
60 int max_bytes_to_read = 0x8004; 66 int possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, };
61 67
62 if (blocksize <= 0x10000) 68 if (blocksize <= 0x10000)
63 blocksize = 0x10000; 69 blocksize = 0x10000;
64 if (blocksize == 0x20000)
65 max_bytes_to_read = 0x18004;
66 70
67 /* Alloc */ 71 /* Alloc */
68 parts = kzalloc(sizeof(struct mtd_partition) * BCM47XXPART_MAX_PARTS, 72 parts = kzalloc(sizeof(struct mtd_partition) * BCM47XXPART_MAX_PARTS,
69 GFP_KERNEL); 73 GFP_KERNEL);
70 buf = kzalloc(max_bytes_to_read, GFP_KERNEL); 74 buf = kzalloc(BCM47XXPART_BYTES_TO_READ, GFP_KERNEL);
71 75
72 /* Parse block by block looking for magics */ 76 /* Parse block by block looking for magics */
73 for (offset = 0; offset <= master->size - blocksize; 77 for (offset = 0; offset <= master->size - blocksize;
@@ -82,7 +86,7 @@ static int bcm47xxpart_parse(struct mtd_info *master,
82 } 86 }
83 87
84 /* Read beginning of the block */ 88 /* Read beginning of the block */
85 if (mtd_read(master, offset, max_bytes_to_read, 89 if (mtd_read(master, offset, BCM47XXPART_BYTES_TO_READ,
86 &bytes_read, (uint8_t *)buf) < 0) { 90 &bytes_read, (uint8_t *)buf) < 0) {
87 pr_err("mtd_read error while parsing (offset: 0x%X)!\n", 91 pr_err("mtd_read error while parsing (offset: 0x%X)!\n",
88 offset); 92 offset);
@@ -96,20 +100,6 @@ static int bcm47xxpart_parse(struct mtd_info *master,
96 continue; 100 continue;
97 } 101 }
98 102
99 /* Standard NVRAM */
100 if (buf[0x000 / 4] == NVRAM_HEADER ||
101 buf[0x1000 / 4] == NVRAM_HEADER ||
102 buf[0x8000 / 4] == NVRAM_HEADER ||
103 (blocksize == 0x20000 && (
104 buf[0x10000 / 4] == NVRAM_HEADER ||
105 buf[0x11000 / 4] == NVRAM_HEADER ||
106 buf[0x18000 / 4] == NVRAM_HEADER))) {
107 bcm47xxpart_add_part(&parts[curr_part++], "nvram",
108 offset, 0);
109 offset = rounddown(offset, blocksize);
110 continue;
111 }
112
113 /* 103 /*
114 * board_data starts with board_id which differs across boards, 104 * board_data starts with board_id which differs across boards,
115 * but we can use 'MPFR' (hopefully) magic at 0x100 105 * but we can use 'MPFR' (hopefully) magic at 0x100
@@ -178,6 +168,30 @@ static int bcm47xxpart_parse(struct mtd_info *master,
178 continue; 168 continue;
179 } 169 }
180 } 170 }
171
172 /* Look for NVRAM at the end of the last block. */
173 for (i = 0; i < ARRAY_SIZE(possible_nvram_sizes); i++) {
174 if (curr_part > BCM47XXPART_MAX_PARTS) {
175 pr_warn("Reached maximum number of partitions, scanning stopped!\n");
176 break;
177 }
178
179 offset = master->size - possible_nvram_sizes[i];
180 if (mtd_read(master, offset, 0x4, &bytes_read,
181 (uint8_t *)buf) < 0) {
182 pr_err("mtd_read error while reading at offset 0x%X!\n",
183 offset);
184 continue;
185 }
186
187 /* Standard NVRAM */
188 if (buf[0] == NVRAM_HEADER) {
189 bcm47xxpart_add_part(&parts[curr_part++], "nvram",
190 master->size - blocksize, 0);
191 break;
192 }
193 }
194
181 kfree(buf); 195 kfree(buf);
182 196
183 /* 197 /*
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 43214151b882..42c63927609d 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1523,6 +1523,14 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1523 oobreadlen -= toread; 1523 oobreadlen -= toread;
1524 } 1524 }
1525 } 1525 }
1526
1527 if (chip->options & NAND_NEED_READRDY) {
1528 /* Apply delay or wait for ready/busy pin */
1529 if (!chip->dev_ready)
1530 udelay(chip->chip_delay);
1531 else
1532 nand_wait_ready(mtd);
1533 }
1526 } else { 1534 } else {
1527 memcpy(buf, chip->buffers->databuf + col, bytes); 1535 memcpy(buf, chip->buffers->databuf + col, bytes);
1528 buf += bytes; 1536 buf += bytes;
@@ -1787,6 +1795,14 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1787 len = min(len, readlen); 1795 len = min(len, readlen);
1788 buf = nand_transfer_oob(chip, buf, ops, len); 1796 buf = nand_transfer_oob(chip, buf, ops, len);
1789 1797
1798 if (chip->options & NAND_NEED_READRDY) {
1799 /* Apply delay or wait for ready/busy pin */
1800 if (!chip->dev_ready)
1801 udelay(chip->chip_delay);
1802 else
1803 nand_wait_ready(mtd);
1804 }
1805
1790 readlen -= len; 1806 readlen -= len;
1791 if (!readlen) 1807 if (!readlen)
1792 break; 1808 break;
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index e3aa2748a6e7..9c612388e5de 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -22,49 +22,51 @@
22* 512 512 Byte page size 22* 512 512 Byte page size
23*/ 23*/
24struct nand_flash_dev nand_flash_ids[] = { 24struct nand_flash_dev nand_flash_ids[] = {
25#define SP_OPTIONS NAND_NEED_READRDY
26#define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16)
25 27
26#ifdef CONFIG_MTD_NAND_MUSEUM_IDS 28#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
27 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0}, 29 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, SP_OPTIONS},
28 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0}, 30 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, SP_OPTIONS},
29 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0}, 31 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, SP_OPTIONS},
30 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0}, 32 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, SP_OPTIONS},
31 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, 33 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, SP_OPTIONS},
32 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0}, 34 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, SP_OPTIONS},
33 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0}, 35 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, SP_OPTIONS},
34 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0}, 36 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, SP_OPTIONS},
35 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0}, 37 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, SP_OPTIONS},
36 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0}, 38 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, SP_OPTIONS},
37 39
38 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0}, 40 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, SP_OPTIONS},
39 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0}, 41 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, SP_OPTIONS},
40 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16}, 42 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, SP_OPTIONS16},
41 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16}, 43 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, SP_OPTIONS16},
42#endif 44#endif
43 45
44 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0}, 46 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, SP_OPTIONS},
45 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0}, 47 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, SP_OPTIONS},
46 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16}, 48 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, SP_OPTIONS16},
47 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16}, 49 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, SP_OPTIONS16},
48 50
49 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0}, 51 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, SP_OPTIONS},
50 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0}, 52 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, SP_OPTIONS},
51 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16}, 53 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, SP_OPTIONS16},
52 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16}, 54 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, SP_OPTIONS16},
53 55
54 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0}, 56 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, SP_OPTIONS},
55 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0}, 57 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, SP_OPTIONS},
56 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16}, 58 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, SP_OPTIONS16},
57 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16}, 59 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, SP_OPTIONS16},
58 60
59 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0}, 61 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, SP_OPTIONS},
60 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0}, 62 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, SP_OPTIONS},
61 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0}, 63 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, SP_OPTIONS},
62 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16}, 64 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, SP_OPTIONS16},
63 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16}, 65 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, SP_OPTIONS16},
64 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16}, 66 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, SP_OPTIONS16},
65 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16}, 67 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, SP_OPTIONS16},
66 68
67 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0}, 69 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, SP_OPTIONS},
68 70
69 /* 71 /*
70 * These are the new chips with large page size. The pagesize and the 72 * These are the new chips with large page size. The pagesize and the
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