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authorBen Dooks <ben@simtec.co.uk>2005-02-18 09:46:15 -0500
committerThomas Gleixner <tglx@mtd.linutronix.de>2005-05-23 06:41:32 -0400
commitfdf2fd52746bbffeffa19e24cb0608abc5429bc2 (patch)
treee9899108b87aa0fc600809697dec816087687517 /drivers/mtd
parent49450795844daba7867cc215f17532cac2c2b284 (diff)
[MTD] Sparse fixes
Fix sparse errors due to lack of address-space markers Updated header comments Small re-format of initialiser Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/s3c2410.c20
1 files changed, 11 insertions, 9 deletions
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
index d05e9b97947d..cb04b3c771e4 100644
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -1,7 +1,8 @@
1/* linux/drivers/mtd/nand/s3c2410.c 1/* linux/drivers/mtd/nand/s3c2410.c
2 * 2 *
3 * Copyright (c) 2004 Simtec Electronics 3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
5 * 6 *
6 * Samsung S3C2410 NAND driver 7 * Samsung S3C2410 NAND driver
7 * 8 *
@@ -10,8 +11,9 @@
10 * 23-Sep-2004 BJD Mulitple device support 11 * 23-Sep-2004 BJD Mulitple device support
11 * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode 12 * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode
12 * 12-Oct-2004 BJD Fixed errors in use of platform data 13 * 12-Oct-2004 BJD Fixed errors in use of platform data
14 * 18-Feb-2004 BJD Fix sparse errors
13 * 15 *
14 * $Id: s3c2410.c,v 1.7 2005/01/05 18:05:14 dwmw2 Exp $ 16 * $Id: s3c2410.c,v 1.8 2005/02/18 14:46:12 bjd Exp $
15 * 17 *
16 * This program is free software; you can redistribute it and/or modify 18 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by 19 * it under the terms of the GNU General Public License as published by
@@ -69,10 +71,10 @@ static int hardware_ecc = 0;
69 */ 71 */
70 72
71static struct nand_oobinfo nand_hw_eccoob = { 73static struct nand_oobinfo nand_hw_eccoob = {
72 .useecc = MTD_NANDECC_AUTOPLACE, 74 .useecc = MTD_NANDECC_AUTOPLACE,
73 .eccbytes = 3, 75 .eccbytes = 3,
74 .eccpos = {0, 1, 2 }, 76 .eccpos = {0, 1, 2 },
75 .oobfree = { {8, 8} } 77 .oobfree = { {8, 8} }
76}; 78};
77 79
78/* controller and mtd information */ 80/* controller and mtd information */
@@ -99,7 +101,7 @@ struct s3c2410_nand_info {
99 struct device *device; 101 struct device *device;
100 struct resource *area; 102 struct resource *area;
101 struct clk *clk; 103 struct clk *clk;
102 void *regs; 104 void __iomem *regs;
103 int mtd_count; 105 int mtd_count;
104}; 106};
105 107
@@ -523,8 +525,8 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
523{ 525{
524 struct nand_chip *chip = &nmtd->chip; 526 struct nand_chip *chip = &nmtd->chip;
525 527
526 chip->IO_ADDR_R = (char *)info->regs + S3C2410_NFDATA; 528 chip->IO_ADDR_R = info->regs + S3C2410_NFDATA;
527 chip->IO_ADDR_W = (char *)info->regs + S3C2410_NFDATA; 529 chip->IO_ADDR_W = info->regs + S3C2410_NFDATA;
528 chip->hwcontrol = s3c2410_nand_hwcontrol; 530 chip->hwcontrol = s3c2410_nand_hwcontrol;
529 chip->dev_ready = s3c2410_nand_devready; 531 chip->dev_ready = s3c2410_nand_devready;
530 chip->cmdfunc = s3c2410_nand_command; 532 chip->cmdfunc = s3c2410_nand_command;