Merge branch 'origin' into devel-stable

Conflicts:
	arch/arm/mach-mx2/devices.c
	arch/arm/mach-mx2/devices.h
	sound/soc/pxa/pxa-ssp.c

4 files changed, 58 insertions, 54 deletions

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 4f99274b24c2..1157d5679e66 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -457,10 +457,10 @@ config MTD_NAND_NOMADIK
 
 config MTD_NAND_SH_FLCTL
         tristate "Support for NAND on Renesas SuperH FLCTL"
-        depends on MTD_NAND && SUPERH && CPU_SUBTYPE_SH7723
+        depends on MTD_NAND && SUPERH
         help
           Several Renesas SuperH CPU has FLCTL. This option enables support
-          for NAND Flash using FLCTL. This driver support SH7723.
+          for NAND Flash using FLCTL.
 
 config MTD_NAND_DAVINCI
         tristate "Support NAND on DaVinci SoC"
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index 92c334ff4508..43d46e424040 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -19,6 +19,7 @@
 #include <asm/io.h>
 
 #include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-db1x00/bcsr.h>
 
 /*
  * MTD structure for NAND controller
@@ -475,7 +476,8 @@ static int __init au1xxx_nand_init(void)
         /* set gpio206 high */
         au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
 
-        boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1);
+        boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
+
         switch (boot_swapboot) {
         case 0:
         case 2:
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 1bb799f0125c..26aec0080184 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -30,12 +30,8 @@
 
 #define DRIVER_NAME     "omap2-nand"
 
-/* size (4 KiB) for IO mapping */
-#define NAND_IO_SIZE    SZ_4K
-
 #define NAND_WP_OFF     0
 #define NAND_WP_BIT     0x00000010
-#define WR_RD_PIN_MONITORING    0x00600000
 
 #define GPMC_BUF_FULL   0x00000001
 #define GPMC_BUF_EMPTY  0x00000000
@@ -882,8 +878,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
         struct omap_nand_info           *info;
         struct omap_nand_platform_data  *pdata;
         int                             err;
-        unsigned long                   val;
-
 
         pdata = pdev->dev.platform_data;
         if (pdata == NULL) {
@@ -905,28 +899,14 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
         info->gpmc_cs           = pdata->cs;
         info->gpmc_baseaddr     = pdata->gpmc_baseaddr;
         info->gpmc_cs_baseaddr  = pdata->gpmc_cs_baseaddr;
+        info->phys_base         = pdata->phys_base;
 
         info->mtd.priv          = &info->nand;
         info->mtd.name          = dev_name(&pdev->dev);
         info->mtd.owner         = THIS_MODULE;
 
-        err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base);
-        if (err < 0) {
-                dev_err(&pdev->dev, "Cannot request GPMC CS\n");
-                goto out_free_info;
-        }
-
-        /* Enable RD PIN Monitoring Reg */
-        if (pdata->dev_ready) {
-                val  = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
-                val |= WR_RD_PIN_MONITORING;
-                gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
-        }
-
-        val  = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7);
-        val &= ~(0xf << 8);
-        val |=  (0xc & 0xf) << 8;
-        gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val);
+        info->nand.options      |= pdata->devsize ? NAND_BUSWIDTH_16 : 0;
+        info->nand.options      |= NAND_SKIP_BBTSCAN;
 
         /* NAND write protect off */
         omap_nand_wp(&info->mtd, NAND_WP_OFF);
@@ -934,7 +914,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
         if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
                                 pdev->dev.driver->name)) {
                 err = -EBUSY;
-                goto out_free_cs;
+                goto out_free_info;
         }
 
         info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
@@ -963,11 +943,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
                 info->nand.chip_delay = 50;
         }
 
-        info->nand.options  |= NAND_SKIP_BBTSCAN;
-        if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000)
-                                                                == 0x1000)
-                info->nand.options  |= NAND_BUSWIDTH_16;
-
         if (use_prefetch) {
                 /* copy the virtual address of nand base for fifo access */
                 info->nand_pref_fifo_add = info->nand.IO_ADDR_R;
@@ -1043,8 +1018,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 
 out_release_mem_region:
         release_mem_region(info->phys_base, NAND_IO_SIZE);
-out_free_cs:
-        gpmc_cs_free(info->gpmc_cs);
 out_free_info:
         kfree(info);
 
diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 02bef21f2e4b..1842df8bdd93 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -1,10 +1,10 @@
 /*
  * SuperH FLCTL nand controller
  *
- * Copyright © 2008 Renesas Solutions Corp.
- * Copyright © 2008 Atom Create Engineering Co., Ltd.
+ * Copyright (c) 2008 Renesas Solutions Corp.
+ * Copyright (c) 2008 Atom Create Engineering Co., Ltd.
  *
- * Based on fsl_elbc_nand.c, Copyright © 2006-2007 Freescale Semiconductor
+ * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -75,6 +75,11 @@ static void start_translation(struct sh_flctl *flctl)
         writeb(TRSTRT, FLTRCR(flctl));
 }
 
+static void timeout_error(struct sh_flctl *flctl, const char *str)
+{
+        dev_err(&flctl->pdev->dev, "Timeout occured in %s\n", str);
+}
+
 static void wait_completion(struct sh_flctl *flctl)
 {
         uint32_t timeout = LOOP_TIMEOUT_MAX;
@@ -87,7 +92,7 @@ static void wait_completion(struct sh_flctl *flctl)
                 udelay(1);
         }
 
-        printk(KERN_ERR "wait_completion(): Timeout occured \n");
+        timeout_error(flctl, __func__);
         writeb(0x0, FLTRCR(flctl));
 }
 
@@ -100,6 +105,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr)
                 addr = page_addr;       /* ERASE1 */
         } else if (page_addr != -1) {
                 /* SEQIN, READ0, etc.. */
+                if (flctl->chip.options & NAND_BUSWIDTH_16)
+                        column >>= 1;
                 if (flctl->page_size) {
                         addr = column & 0x0FFF;
                         addr |= (page_addr & 0xff) << 16;
@@ -132,7 +139,7 @@ static void wait_rfifo_ready(struct sh_flctl *flctl)
                         return;
                 udelay(1);
         }
-        printk(KERN_ERR "wait_rfifo_ready(): Timeout occured \n");
+        timeout_error(flctl, __func__);
 }
 
 static void wait_wfifo_ready(struct sh_flctl *flctl)
@@ -146,7 +153,7 @@ static void wait_wfifo_ready(struct sh_flctl *flctl)
                         return;
                 udelay(1);
         }
-        printk(KERN_ERR "wait_wfifo_ready(): Timeout occured \n");
+        timeout_error(flctl, __func__);
 }
 
 static int wait_recfifo_ready(struct sh_flctl *flctl, int sector_number)
@@ -198,7 +205,7 @@ static int wait_recfifo_ready(struct sh_flctl *flctl, int sector_number)
                 writel(0, FL4ECCCR(flctl));
         }
 
-        printk(KERN_ERR "wait_recfifo_ready(): Timeout occured \n");
+        timeout_error(flctl, __func__);
         return 1;       /* timeout */
 }
 
@@ -214,7 +221,7 @@ static void wait_wecfifo_ready(struct sh_flctl *flctl)
                         return;
                 udelay(1);
         }
-        printk(KERN_ERR "wait_wecfifo_ready(): Timeout occured \n");
+        timeout_error(flctl, __func__);
 }
 
 static void read_datareg(struct sh_flctl *flctl, int offset)
@@ -275,7 +282,7 @@ static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
 static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val)
 {
         struct sh_flctl *flctl = mtd_to_flctl(mtd);
-        uint32_t flcmncr_val = readl(FLCMNCR(flctl));
+        uint32_t flcmncr_val = readl(FLCMNCR(flctl)) & ~SEL_16BIT;
         uint32_t flcmdcr_val, addr_len_bytes = 0;
 
         /* Set SNAND bit if page size is 2048byte */
@@ -297,6 +304,8 @@ static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_va
         case NAND_CMD_READOOB:
                 addr_len_bytes = flctl->rw_ADRCNT;
                 flcmdcr_val |= CDSRC_E;
+                if (flctl->chip.options & NAND_BUSWIDTH_16)
+                        flcmncr_val |= SEL_16BIT;
                 break;
         case NAND_CMD_SEQIN:
                 /* This case is that cmd is READ0 or READ1 or READ00 */
@@ -305,6 +314,8 @@ static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_va
         case NAND_CMD_PAGEPROG:
                 addr_len_bytes = flctl->rw_ADRCNT;
                 flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW;
+                if (flctl->chip.options & NAND_BUSWIDTH_16)
+                        flcmncr_val |= SEL_16BIT;
                 break;
         case NAND_CMD_READID:
                 flcmncr_val &= ~SNAND_E;
@@ -523,6 +534,8 @@ static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
                 set_addr(mtd, 0, page_addr);
 
                 flctl->read_bytes = mtd->writesize + mtd->oobsize;
+                if (flctl->chip.options & NAND_BUSWIDTH_16)
+                        column >>= 1;
                 flctl->index += column;
                 goto read_normal_exit;
 
@@ -686,6 +699,18 @@ static uint8_t flctl_read_byte(struct mtd_info *mtd)
         return data;
 }
 
+static uint16_t flctl_read_word(struct mtd_info *mtd)
+{
+       struct sh_flctl *flctl = mtd_to_flctl(mtd);
+       int index = flctl->index;
+       uint16_t data;
+       uint16_t *buf = (uint16_t *)&flctl->done_buff[index];
+
+       data = *buf;
+       flctl->index += 2;
+       return data;
+}
+
 static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
         int i;
@@ -769,38 +794,36 @@ static int flctl_chip_init_tail(struct mtd_info *mtd)
         return 0;
 }
 
-static int __init flctl_probe(struct platform_device *pdev)
+static int __devinit flctl_probe(struct platform_device *pdev)
 {
         struct resource *res;
         struct sh_flctl *flctl;
         struct mtd_info *flctl_mtd;
         struct nand_chip *nand;
         struct sh_flctl_platform_data *pdata;
-        int ret;
+        int ret = -ENXIO;
 
         pdata = pdev->dev.platform_data;
         if (pdata == NULL) {
-                printk(KERN_ERR "sh_flctl platform_data not found.\n");
-                return -ENODEV;
+                dev_err(&pdev->dev, "no platform data defined\n");
+                return -EINVAL;
         }
 
         flctl = kzalloc(sizeof(struct sh_flctl), GFP_KERNEL);
         if (!flctl) {
-                printk(KERN_ERR "Unable to allocate NAND MTD dev structure.\n");
+                dev_err(&pdev->dev, "failed to allocate driver data\n");
                 return -ENOMEM;
         }
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!res) {
-                printk(KERN_ERR "%s: resource not found.\n", __func__);
-                ret = -ENODEV;
+                dev_err(&pdev->dev, "failed to get I/O memory\n");
                 goto err;
         }
 
-        flctl->reg = ioremap(res->start, res->end - res->start + 1);
+        flctl->reg = ioremap(res->start, resource_size(res));
         if (flctl->reg == NULL) {
-                printk(KERN_ERR "%s: ioremap error.\n", __func__);
-                ret = -ENOMEM;
+                dev_err(&pdev->dev, "failed to remap I/O memory\n");
                 goto err;
         }
 
@@ -808,6 +831,7 @@ static int __init flctl_probe(struct platform_device *pdev)
         flctl_mtd = &flctl->mtd;
         nand = &flctl->chip;
         flctl_mtd->priv = nand;
+        flctl->pdev = pdev;
         flctl->hwecc = pdata->has_hwecc;
 
         flctl_register_init(flctl, pdata->flcmncr_val);
@@ -825,6 +849,11 @@ static int __init flctl_probe(struct platform_device *pdev)
         nand->select_chip = flctl_select_chip;
         nand->cmdfunc = flctl_cmdfunc;
 
+        if (pdata->flcmncr_val & SEL_16BIT) {
+                nand->options |= NAND_BUSWIDTH_16;
+                nand->read_word = flctl_read_word;
+        }
+
         ret = nand_scan_ident(flctl_mtd, 1);
         if (ret)
                 goto err;
@@ -846,7 +875,7 @@ err:
         return ret;
 }
 
-static int __exit flctl_remove(struct platform_device *pdev)
+static int __devexit flctl_remove(struct platform_device *pdev)
 {
         struct sh_flctl *flctl = platform_get_drvdata(pdev);