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authorArtem Bityutskiy <artem.bityutskiy@linux.intel.com>2013-03-04 07:21:34 -0500
committerDavid Woodhouse <David.Woodhouse@intel.com>2013-04-05 07:00:50 -0400
commit14c6578683367b1e7af0c3c09e872b45a45183a7 (patch)
tree8035d78cea0c4d1849134eaf113d29bef6286f28 /drivers/mtd/nand
parent02f57fe448618722ed713fe1002894ead9981310 (diff)
mtd: nand: remove AG-AND support
We have only one AG-AND driver and it was not touched since 2005. It looks like AG-AND was not really make it to mass-production and can be considered a dead technology. Along with the AG-AND support, this patch removes the BBT_AUTO_REFRESH feature, because the only user of this feature is AG-AND. And even though it is implemented as a generic feature, I prefer to remove it because NAND flashes do not really need it in this form. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/nand')
-rw-r--r--drivers/mtd/nand/nand_base.c80
-rw-r--r--drivers/mtd/nand/nand_bbt.c25
-rw-r--r--drivers/mtd/nand/nand_ids.c13
3 files changed, 2 insertions, 116 deletions
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 42c63927609d..7b7ebd5ed430 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4,7 +4,6 @@
4 * Overview: 4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be 5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available. 6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 * 7 *
9 * Additional technical information is available on 8 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html 9 * http://www.linux-mtd.infradead.org/doc/nand.html
@@ -22,8 +21,6 @@
22 * Enable cached programming for 2k page size chips 21 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW 22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ECC support. 23 * if we have HW ECC support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed 24 * BBT table is not serialized, has to be fixed
28 * 25 *
29 * This program is free software; you can redistribute it and/or modify 26 * This program is free software; you can redistribute it and/or modify
@@ -836,10 +833,7 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
836 */ 833 */
837 ndelay(100); 834 ndelay(100);
838 835
839 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) 836 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
840 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
841 else
842 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
843 837
844 if (in_interrupt() || oops_in_progress) 838 if (in_interrupt() || oops_in_progress)
845 panic_nand_wait(mtd, chip, timeo); 839 panic_nand_wait(mtd, chip, timeo);
@@ -2481,24 +2475,6 @@ static void single_erase_cmd(struct mtd_info *mtd, int page)
2481} 2475}
2482 2476
2483/** 2477/**
2484 * multi_erase_cmd - [GENERIC] AND specific block erase command function
2485 * @mtd: MTD device structure
2486 * @page: the page address of the block which will be erased
2487 *
2488 * AND multi block erase command function. Erase 4 consecutive blocks.
2489 */
2490static void multi_erase_cmd(struct mtd_info *mtd, int page)
2491{
2492 struct nand_chip *chip = mtd->priv;
2493 /* Send commands to erase a block */
2494 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2495 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2496 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2497 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2498 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2499}
2500
2501/**
2502 * nand_erase - [MTD Interface] erase block(s) 2478 * nand_erase - [MTD Interface] erase block(s)
2503 * @mtd: MTD device structure 2479 * @mtd: MTD device structure
2504 * @instr: erase instruction 2480 * @instr: erase instruction
@@ -2510,7 +2486,6 @@ static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2510 return nand_erase_nand(mtd, instr, 0); 2486 return nand_erase_nand(mtd, instr, 0);
2511} 2487}
2512 2488
2513#define BBT_PAGE_MASK 0xffffff3f
2514/** 2489/**
2515 * nand_erase_nand - [INTERN] erase block(s) 2490 * nand_erase_nand - [INTERN] erase block(s)
2516 * @mtd: MTD device structure 2491 * @mtd: MTD device structure
@@ -2524,8 +2499,6 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2524{ 2499{
2525 int page, status, pages_per_block, ret, chipnr; 2500 int page, status, pages_per_block, ret, chipnr;
2526 struct nand_chip *chip = mtd->priv; 2501 struct nand_chip *chip = mtd->priv;
2527 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2528 unsigned int bbt_masked_page = 0xffffffff;
2529 loff_t len; 2502 loff_t len;
2530 2503
2531 pr_debug("%s: start = 0x%012llx, len = %llu\n", 2504 pr_debug("%s: start = 0x%012llx, len = %llu\n",
@@ -2556,15 +2529,6 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2556 goto erase_exit; 2529 goto erase_exit;
2557 } 2530 }
2558 2531
2559 /*
2560 * If BBT requires refresh, set the BBT page mask to see if the BBT
2561 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2562 * can not be matched. This is also done when the bbt is actually
2563 * erased to avoid recursive updates.
2564 */
2565 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2566 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2567
2568 /* Loop through the pages */ 2532 /* Loop through the pages */
2569 len = instr->len; 2533 len = instr->len;
2570 2534
@@ -2610,15 +2574,6 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2610 goto erase_exit; 2574 goto erase_exit;
2611 } 2575 }
2612 2576
2613 /*
2614 * If BBT requires refresh, set the BBT rewrite flag to the
2615 * page being erased.
2616 */
2617 if (bbt_masked_page != 0xffffffff &&
2618 (page & BBT_PAGE_MASK) == bbt_masked_page)
2619 rewrite_bbt[chipnr] =
2620 ((loff_t)page << chip->page_shift);
2621
2622 /* Increment page address and decrement length */ 2577 /* Increment page address and decrement length */
2623 len -= (1 << chip->phys_erase_shift); 2578 len -= (1 << chip->phys_erase_shift);
2624 page += pages_per_block; 2579 page += pages_per_block;
@@ -2628,15 +2583,6 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2628 chipnr++; 2583 chipnr++;
2629 chip->select_chip(mtd, -1); 2584 chip->select_chip(mtd, -1);
2630 chip->select_chip(mtd, chipnr); 2585 chip->select_chip(mtd, chipnr);
2631
2632 /*
2633 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2634 * page mask to see if this BBT should be rewritten.
2635 */
2636 if (bbt_masked_page != 0xffffffff &&
2637 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2638 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2639 BBT_PAGE_MASK;
2640 } 2586 }
2641 } 2587 }
2642 instr->state = MTD_ERASE_DONE; 2588 instr->state = MTD_ERASE_DONE;
@@ -2653,23 +2599,6 @@ erase_exit:
2653 if (!ret) 2599 if (!ret)
2654 mtd_erase_callback(instr); 2600 mtd_erase_callback(instr);
2655 2601
2656 /*
2657 * If BBT requires refresh and erase was successful, rewrite any
2658 * selected bad block tables.
2659 */
2660 if (bbt_masked_page == 0xffffffff || ret)
2661 return ret;
2662
2663 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2664 if (!rewrite_bbt[chipnr])
2665 continue;
2666 /* Update the BBT for chip */
2667 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2668 __func__, chipnr, rewrite_bbt[chipnr],
2669 chip->bbt_td->pages[chipnr]);
2670 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2671 }
2672
2673 /* Return more or less happy */ 2602 /* Return more or less happy */
2674 return ret; 2603 return ret;
2675} 2604}
@@ -3302,12 +3231,7 @@ ident_done:
3302 } 3231 }
3303 3232
3304 chip->badblockbits = 8; 3233 chip->badblockbits = 8;
3305 3234 chip->erase_cmd = single_erase_cmd;
3306 /* Check for AND chips with 4 page planes */
3307 if (chip->options & NAND_4PAGE_ARRAY)
3308 chip->erase_cmd = multi_erase_cmd;
3309 else
3310 chip->erase_cmd = single_erase_cmd;
3311 3235
3312 /* Do not replace user supplied command function! */ 3236 /* Do not replace user supplied command function! */
3313 if (mtd->writesize > 512 && chip->cmdfunc == nand_command) 3237 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 916d6e9c0ab1..267264320e06 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -1240,15 +1240,6 @@ int nand_update_bbt(struct mtd_info *mtd, loff_t offs)
1240 */ 1240 */
1241static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; 1241static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
1242 1242
1243static uint8_t scan_agand_pattern[] = { 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7 };
1244
1245static struct nand_bbt_descr agand_flashbased = {
1246 .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
1247 .offs = 0x20,
1248 .len = 6,
1249 .pattern = scan_agand_pattern
1250};
1251
1252/* Generic flash bbt descriptors */ 1243/* Generic flash bbt descriptors */
1253static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; 1244static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1254static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; 1245static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
@@ -1333,22 +1324,6 @@ int nand_default_bbt(struct mtd_info *mtd)
1333{ 1324{
1334 struct nand_chip *this = mtd->priv; 1325 struct nand_chip *this = mtd->priv;
1335 1326
1336 /*
1337 * Default for AG-AND. We must use a flash based bad block table as the
1338 * devices have factory marked _good_ blocks. Erasing those blocks
1339 * leads to loss of the good / bad information, so we _must_ store this
1340 * information in a good / bad table during startup.
1341 */
1342 if (this->options & NAND_IS_AND) {
1343 /* Use the default pattern descriptors */
1344 if (!this->bbt_td) {
1345 this->bbt_td = &bbt_main_descr;
1346 this->bbt_md = &bbt_mirror_descr;
1347 }
1348 this->bbt_options |= NAND_BBT_USE_FLASH;
1349 return nand_scan_bbt(mtd, &agand_flashbased);
1350 }
1351
1352 /* Is a flash based bad block table requested? */ 1327 /* Is a flash based bad block table requested? */
1353 if (this->bbt_options & NAND_BBT_USE_FLASH) { 1328 if (this->bbt_options & NAND_BBT_USE_FLASH) {
1354 /* Use the default pattern descriptors */ 1329 /* Use the default pattern descriptors */
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 818bb9e29819..a907e47ce668 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -134,19 +134,6 @@ struct nand_flash_dev nand_flash_ids[] = {
134 {"NAND 64GiB 1,8V 16-bit", 0x2E, 0, 65536, 0, LP_OPTIONS16}, 134 {"NAND 64GiB 1,8V 16-bit", 0x2E, 0, 65536, 0, LP_OPTIONS16},
135 {"NAND 64GiB 3,3V 16-bit", 0x4E, 0, 65536, 0, LP_OPTIONS16}, 135 {"NAND 64GiB 3,3V 16-bit", 0x4E, 0, 65536, 0, LP_OPTIONS16},
136 136
137 /*
138 * Renesas AND 1 Gigabit. Those chips do not support extended id and
139 * have a strange page/block layout ! The chosen minimum erasesize is
140 * 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page
141 * planes 1 block = 2 pages, but due to plane arrangement the blocks
142 * 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would
143 * increase the eraseblock size so we chose a combined one which can be
144 * erased in one go There are more speed improvements for reads and
145 * writes possible, but not implemented now
146 */
147 {"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000,
148 NAND_IS_AND | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH},
149
150 {NULL,} 137 {NULL,}
151}; 138};
152 139