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authorLinus Torvalds <torvalds@linux-foundation.org>2009-12-16 13:23:43 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-12-16 13:23:43 -0500
commit60d9aa758c00f20ade0cb1951f6a934f628dd2d7 (patch)
treee3bdfa4ec0d3f9a29a822810b8b9188c7d613cbd /drivers/mtd/nand
parentb2adf0cbec4cf0934c63f48f893e0cebde380d0c (diff)
parent2e16cfca6e17ae37ae21feca080a6f2eca9087dc (diff)
Merge git://git.infradead.org/mtd-2.6
* git://git.infradead.org/mtd-2.6: (90 commits) jffs2: Fix long-standing bug with symlink garbage collection. mtd: OneNAND: Fix test of unsigned in onenand_otp_walk() mtd: cfi_cmdset_0002, fix lock imbalance Revert "mtd: move mxcnd_remove to .exit.text" mtd: m25p80: add support for Macronix MX25L4005A kmsg_dump: fix build for CONFIG_PRINTK=n mtd: nandsim: add support for 4KiB pages mtd: mtdoops: refactor as a kmsg_dumper mtd: mtdoops: make record size configurable mtd: mtdoops: limit the maximum mtd partition size mtd: mtdoops: keep track of used/unused pages in an array mtd: mtdoops: several minor cleanups core: Add kernel message dumper to call on oopses and panics mtd: add ARM pismo support mtd: pxa3xx_nand: Fix PIO data transfer mtd: nand: fix multi-chip suspend problem mtd: add support for switching old SST chips into QRY mode mtd: fix M29W800D dev_id and uaddr mtd: don't use PF_MEMALLOC mtd: Add bad block table overrides to Davinci NAND driver ... Fixed up conflicts (mostly trivial) in drivers/mtd/devices/m25p80.c drivers/mtd/maps/pcmciamtd.c drivers/mtd/nand/pxa3xx_nand.c kernel/printk.c
Diffstat (limited to 'drivers/mtd/nand')
-rw-r--r--drivers/mtd/nand/Kconfig16
-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/alauda.c11
-rw-r--r--drivers/mtd/nand/atmel_nand.c5
-rw-r--r--drivers/mtd/nand/bcm_umi_bch.c213
-rw-r--r--drivers/mtd/nand/bcm_umi_nand.c581
-rw-r--r--drivers/mtd/nand/davinci_nand.c4
-rw-r--r--drivers/mtd/nand/excite_nandflash.c2
-rw-r--r--drivers/mtd/nand/fsl_elbc_nand.c86
-rw-r--r--drivers/mtd/nand/fsl_upm.c2
-rw-r--r--drivers/mtd/nand/mxc_nand.c783
-rw-r--r--drivers/mtd/nand/nand_base.c141
-rw-r--r--drivers/mtd/nand/nand_bcm_umi.c149
-rw-r--r--drivers/mtd/nand/nand_bcm_umi.h358
-rw-r--r--drivers/mtd/nand/nand_ecc.c25
-rw-r--r--drivers/mtd/nand/nandsim.c7
-rw-r--r--drivers/mtd/nand/plat_nand.c50
-rw-r--r--drivers/mtd/nand/s3c2410.c2
-rw-r--r--drivers/mtd/nand/txx9ndfmc.c3
19 files changed, 1855 insertions, 584 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 0e35e1aefd22..7678538344f4 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -201,6 +201,22 @@ config MTD_NAND_S3C2410_CLKSTOP
201 when the is NAND chip selected or released, but will save 201 when the is NAND chip selected or released, but will save
202 approximately 5mA of power when there is nothing happening. 202 approximately 5mA of power when there is nothing happening.
203 203
204config MTD_NAND_BCM_UMI
205 tristate "NAND Flash support for BCM Reference Boards"
206 depends on ARCH_BCMRING && MTD_NAND
207 help
208 This enables the NAND flash controller on the BCM UMI block.
209
210 No board specfic support is done by this driver, each board
211 must advertise a platform_device for the driver to attach.
212
213config MTD_NAND_BCM_UMI_HWCS
214 bool "BCM UMI NAND Hardware CS"
215 depends on MTD_NAND_BCM_UMI
216 help
217 Enable the use of the BCM UMI block's internal CS using NAND.
218 This should only be used if you know the external NAND CS can toggle.
219
204config MTD_NAND_DISKONCHIP 220config MTD_NAND_DISKONCHIP
205 tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)" 221 tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)"
206 depends on EXPERIMENTAL 222 depends on EXPERIMENTAL
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 6950d3dabf10..460a1f39a8d1 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -42,5 +42,6 @@ obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o
42obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o 42obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o
43obj-$(CONFIG_MTD_NAND_W90P910) += w90p910_nand.o 43obj-$(CONFIG_MTD_NAND_W90P910) += w90p910_nand.o
44obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o 44obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o
45obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o
45 46
46nand-objs := nand_base.o nand_bbt.o 47nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/alauda.c b/drivers/mtd/nand/alauda.c
index 6d9649159a18..2d6773281fd9 100644
--- a/drivers/mtd/nand/alauda.c
+++ b/drivers/mtd/nand/alauda.c
@@ -372,15 +372,6 @@ static int alauda_read_oob(struct mtd_info *mtd, loff_t from, void *oob)
372 return __alauda_read_page(mtd, from, ignore_buf, oob); 372 return __alauda_read_page(mtd, from, ignore_buf, oob);
373} 373}
374 374
375static int popcount8(u8 c)
376{
377 int ret = 0;
378
379 for ( ; c; c>>=1)
380 ret += c & 1;
381 return ret;
382}
383
384static int alauda_isbad(struct mtd_info *mtd, loff_t ofs) 375static int alauda_isbad(struct mtd_info *mtd, loff_t ofs)
385{ 376{
386 u8 oob[16]; 377 u8 oob[16];
@@ -391,7 +382,7 @@ static int alauda_isbad(struct mtd_info *mtd, loff_t ofs)
391 return err; 382 return err;
392 383
393 /* A block is marked bad if two or more bits are zero */ 384 /* A block is marked bad if two or more bits are zero */
394 return popcount8(oob[5]) >= 7 ? 0 : 1; 385 return hweight8(oob[5]) >= 7 ? 0 : 1;
395} 386}
396 387
397static int alauda_bounce_read(struct mtd_info *mtd, loff_t from, size_t len, 388static int alauda_bounce_read(struct mtd_info *mtd, loff_t from, size_t len,
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index f8e9975c86e5..524e6c9e0672 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -192,7 +192,6 @@ static int atmel_nand_calculate(struct mtd_info *mtd,
192{ 192{
193 struct nand_chip *nand_chip = mtd->priv; 193 struct nand_chip *nand_chip = mtd->priv;
194 struct atmel_nand_host *host = nand_chip->priv; 194 struct atmel_nand_host *host = nand_chip->priv;
195 uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
196 unsigned int ecc_value; 195 unsigned int ecc_value;
197 196
198 /* get the first 2 ECC bytes */ 197 /* get the first 2 ECC bytes */
@@ -464,7 +463,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
464 if (host->board->det_pin) { 463 if (host->board->det_pin) {
465 if (gpio_get_value(host->board->det_pin)) { 464 if (gpio_get_value(host->board->det_pin)) {
466 printk(KERN_INFO "No SmartMedia card inserted.\n"); 465 printk(KERN_INFO "No SmartMedia card inserted.\n");
467 res = ENXIO; 466 res = -ENXIO;
468 goto err_no_card; 467 goto err_no_card;
469 } 468 }
470 } 469 }
@@ -535,7 +534,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
535 534
536 if ((!partitions) || (num_partitions == 0)) { 535 if ((!partitions) || (num_partitions == 0)) {
537 printk(KERN_ERR "atmel_nand: No partitions defined, or unsupported device.\n"); 536 printk(KERN_ERR "atmel_nand: No partitions defined, or unsupported device.\n");
538 res = ENXIO; 537 res = -ENXIO;
539 goto err_no_partitions; 538 goto err_no_partitions;
540 } 539 }
541 540
diff --git a/drivers/mtd/nand/bcm_umi_bch.c b/drivers/mtd/nand/bcm_umi_bch.c
new file mode 100644
index 000000000000..a930666d0687
--- /dev/null
+++ b/drivers/mtd/nand/bcm_umi_bch.c
@@ -0,0 +1,213 @@
1/*****************************************************************************
2* Copyright 2004 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/* ---- Include Files ---------------------------------------------------- */
16#include "nand_bcm_umi.h"
17
18/* ---- External Variable Declarations ----------------------------------- */
19/* ---- External Function Prototypes ------------------------------------- */
20/* ---- Public Variables ------------------------------------------------- */
21/* ---- Private Constants and Types -------------------------------------- */
22
23/* ---- Private Function Prototypes -------------------------------------- */
24static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
25 struct nand_chip *chip, uint8_t *buf, int page);
26static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
27 struct nand_chip *chip, const uint8_t *buf);
28
29/* ---- Private Variables ------------------------------------------------ */
30
31/*
32** nand_hw_eccoob
33** New oob placement block for use with hardware ecc generation.
34*/
35static struct nand_ecclayout nand_hw_eccoob_512 = {
36 /* Reserve 5 for BI indicator */
37 .oobfree = {
38#if (NAND_ECC_NUM_BYTES > 3)
39 {.offset = 0, .length = 2}
40#else
41 {.offset = 0, .length = 5},
42 {.offset = 6, .length = 7}
43#endif
44 }
45};
46
47/*
48** We treat the OOB for a 2K page as if it were 4 512 byte oobs,
49** except the BI is at byte 0.
50*/
51static struct nand_ecclayout nand_hw_eccoob_2048 = {
52 /* Reserve 0 as BI indicator */
53 .oobfree = {
54#if (NAND_ECC_NUM_BYTES > 10)
55 {.offset = 1, .length = 2},
56#elif (NAND_ECC_NUM_BYTES > 7)
57 {.offset = 1, .length = 5},
58 {.offset = 16, .length = 6},
59 {.offset = 32, .length = 6},
60 {.offset = 48, .length = 6}
61#else
62 {.offset = 1, .length = 8},
63 {.offset = 16, .length = 9},
64 {.offset = 32, .length = 9},
65 {.offset = 48, .length = 9}
66#endif
67 }
68};
69
70/* We treat the OOB for a 4K page as if it were 8 512 byte oobs,
71 * except the BI is at byte 0. */
72static struct nand_ecclayout nand_hw_eccoob_4096 = {
73 /* Reserve 0 as BI indicator */
74 .oobfree = {
75#if (NAND_ECC_NUM_BYTES > 10)
76 {.offset = 1, .length = 2},
77 {.offset = 16, .length = 3},
78 {.offset = 32, .length = 3},
79 {.offset = 48, .length = 3},
80 {.offset = 64, .length = 3},
81 {.offset = 80, .length = 3},
82 {.offset = 96, .length = 3},
83 {.offset = 112, .length = 3}
84#else
85 {.offset = 1, .length = 5},
86 {.offset = 16, .length = 6},
87 {.offset = 32, .length = 6},
88 {.offset = 48, .length = 6},
89 {.offset = 64, .length = 6},
90 {.offset = 80, .length = 6},
91 {.offset = 96, .length = 6},
92 {.offset = 112, .length = 6}
93#endif
94 }
95};
96
97/* ---- Private Functions ------------------------------------------------ */
98/* ==== Public Functions ================================================= */
99
100/****************************************************************************
101*
102* bcm_umi_bch_read_page_hwecc - hardware ecc based page read function
103* @mtd: mtd info structure
104* @chip: nand chip info structure
105* @buf: buffer to store read data
106*
107***************************************************************************/
108static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
109 struct nand_chip *chip, uint8_t * buf,
110 int page)
111{
112 int sectorIdx = 0;
113 int eccsize = chip->ecc.size;
114 int eccsteps = chip->ecc.steps;
115 uint8_t *datap = buf;
116 uint8_t eccCalc[NAND_ECC_NUM_BYTES];
117 int sectorOobSize = mtd->oobsize / eccsteps;
118 int stat;
119
120 for (sectorIdx = 0; sectorIdx < eccsteps;
121 sectorIdx++, datap += eccsize) {
122 if (sectorIdx > 0) {
123 /* Seek to page location within sector */
124 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, sectorIdx * eccsize,
125 -1);
126 }
127
128 /* Enable hardware ECC before reading the buf */
129 nand_bcm_umi_bch_enable_read_hwecc();
130
131 /* Read in data */
132 bcm_umi_nand_read_buf(mtd, datap, eccsize);
133
134 /* Pause hardware ECC after reading the buf */
135 nand_bcm_umi_bch_pause_read_ecc_calc();
136
137 /* Read the OOB ECC */
138 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
139 mtd->writesize + sectorIdx * sectorOobSize, -1);
140 nand_bcm_umi_bch_read_oobEcc(mtd->writesize, eccCalc,
141 NAND_ECC_NUM_BYTES,
142 chip->oob_poi +
143 sectorIdx * sectorOobSize);
144
145 /* Correct any ECC detected errors */
146 stat =
147 nand_bcm_umi_bch_correct_page(datap, eccCalc,
148 NAND_ECC_NUM_BYTES);
149
150 /* Update Stats */
151 if (stat < 0) {
152#if defined(NAND_BCM_UMI_DEBUG)
153 printk(KERN_WARNING "%s uncorr_err sectorIdx=%d\n",
154 __func__, sectorIdx);
155 printk(KERN_WARNING
156 "%s data %02x %02x %02x %02x "
157 "%02x %02x %02x %02x\n",
158 __func__, datap[0], datap[1], datap[2], datap[3],
159 datap[4], datap[5], datap[6], datap[7]);
160 printk(KERN_WARNING
161 "%s ecc %02x %02x %02x %02x "
162 "%02x %02x %02x %02x %02x %02x "
163 "%02x %02x %02x\n",
164 __func__, eccCalc[0], eccCalc[1], eccCalc[2],
165 eccCalc[3], eccCalc[4], eccCalc[5], eccCalc[6],
166 eccCalc[7], eccCalc[8], eccCalc[9], eccCalc[10],
167 eccCalc[11], eccCalc[12]);
168 BUG();
169#endif
170 mtd->ecc_stats.failed++;
171 } else {
172#if defined(NAND_BCM_UMI_DEBUG)
173 if (stat > 0) {
174 printk(KERN_INFO
175 "%s %d correctable_errors detected\n",
176 __func__, stat);
177 }
178#endif
179 mtd->ecc_stats.corrected += stat;
180 }
181 }
182 return 0;
183}
184
185/****************************************************************************
186*
187* bcm_umi_bch_write_page_hwecc - hardware ecc based page write function
188* @mtd: mtd info structure
189* @chip: nand chip info structure
190* @buf: data buffer
191*
192***************************************************************************/
193static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
194 struct nand_chip *chip, const uint8_t *buf)
195{
196 int sectorIdx = 0;
197 int eccsize = chip->ecc.size;
198 int eccsteps = chip->ecc.steps;
199 const uint8_t *datap = buf;
200 uint8_t *oobp = chip->oob_poi;
201 int sectorOobSize = mtd->oobsize / eccsteps;
202
203 for (sectorIdx = 0; sectorIdx < eccsteps;
204 sectorIdx++, datap += eccsize, oobp += sectorOobSize) {
205 /* Enable hardware ECC before writing the buf */
206 nand_bcm_umi_bch_enable_write_hwecc();
207 bcm_umi_nand_write_buf(mtd, datap, eccsize);
208 nand_bcm_umi_bch_write_oobEcc(mtd->writesize, oobp,
209 NAND_ECC_NUM_BYTES);
210 }
211
212 bcm_umi_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
213}
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
new file mode 100644
index 000000000000..087bcd745bb7
--- /dev/null
+++ b/drivers/mtd/nand/bcm_umi_nand.c
@@ -0,0 +1,581 @@
1/*****************************************************************************
2* Copyright 2004 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/* ---- Include Files ---------------------------------------------------- */
16#include <linux/version.h>
17#include <linux/module.h>
18#include <linux/types.h>
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/string.h>
22#include <linux/ioport.h>
23#include <linux/device.h>
24#include <linux/delay.h>
25#include <linux/err.h>
26#include <linux/io.h>
27#include <linux/platform_device.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/nand.h>
30#include <linux/mtd/nand_ecc.h>
31#include <linux/mtd/partitions.h>
32
33#include <asm/mach-types.h>
34#include <asm/system.h>
35
36#include <mach/reg_nand.h>
37#include <mach/reg_umi.h>
38
39#include "nand_bcm_umi.h"
40
41#include <mach/memory_settings.h>
42
43#define USE_DMA 1
44#include <mach/dma.h>
45#include <linux/dma-mapping.h>
46#include <linux/completion.h>
47
48/* ---- External Variable Declarations ----------------------------------- */
49/* ---- External Function Prototypes ------------------------------------- */
50/* ---- Public Variables ------------------------------------------------- */
51/* ---- Private Constants and Types -------------------------------------- */
52static const __devinitconst char gBanner[] = KERN_INFO \
53 "BCM UMI MTD NAND Driver: 1.00\n";
54
55#ifdef CONFIG_MTD_PARTITIONS
56const char *part_probes[] = { "cmdlinepart", NULL };
57#endif
58
59#if NAND_ECC_BCH
60static uint8_t scan_ff_pattern[] = { 0xff };
61
62static struct nand_bbt_descr largepage_bbt = {
63 .options = 0,
64 .offs = 0,
65 .len = 1,
66 .pattern = scan_ff_pattern
67};
68#endif
69
70/*
71** Preallocate a buffer to avoid having to do this every dma operation.
72** This is the size of the preallocated coherent DMA buffer.
73*/
74#if USE_DMA
75#define DMA_MIN_BUFLEN 512
76#define DMA_MAX_BUFLEN PAGE_SIZE
77#define USE_DIRECT_IO(len) (((len) < DMA_MIN_BUFLEN) || \
78 ((len) > DMA_MAX_BUFLEN))
79
80/*
81 * The current NAND data space goes from 0x80001900 to 0x80001FFF,
82 * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
83 * size NAND flash. Need to break the DMA down to multiple 1Ks.
84 *
85 * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
86 */
87#define DMA_MAX_LEN 1024
88
89#else /* !USE_DMA */
90#define DMA_MIN_BUFLEN 0
91#define DMA_MAX_BUFLEN 0
92#define USE_DIRECT_IO(len) 1
93#endif
94/* ---- Private Function Prototypes -------------------------------------- */
95static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len);
96static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
97 int len);
98
99/* ---- Private Variables ------------------------------------------------ */
100static struct mtd_info *board_mtd;
101static void __iomem *bcm_umi_io_base;
102static void *virtPtr;
103static dma_addr_t physPtr;
104static struct completion nand_comp;
105
106/* ---- Private Functions ------------------------------------------------ */
107#if NAND_ECC_BCH
108#include "bcm_umi_bch.c"
109#else
110#include "bcm_umi_hamming.c"
111#endif
112
113#if USE_DMA
114
115/* Handler called when the DMA finishes. */
116static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData)
117{
118 complete(&nand_comp);
119}
120
121static int nand_dma_init(void)
122{
123 int rc;
124
125 rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM,
126 nand_dma_handler, NULL);
127 if (rc != 0) {
128 printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc);
129 return rc;
130 }
131
132 virtPtr =
133 dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL);
134 if (virtPtr == NULL) {
135 printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n");
136 return -ENOMEM;
137 }
138
139 return 0;
140}
141
142static void nand_dma_term(void)
143{
144 if (virtPtr != NULL)
145 dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr);
146}
147
148static void nand_dma_read(void *buf, int len)
149{
150 int offset = 0;
151 int tmp_len = 0;
152 int len_left = len;
153 DMA_Handle_t hndl;
154
155 if (virtPtr == NULL)
156 panic("nand_dma_read: virtPtr == NULL\n");
157
158 if ((void *)physPtr == NULL)
159 panic("nand_dma_read: physPtr == NULL\n");
160
161 hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
162 if (hndl < 0) {
163 printk(KERN_ERR
164 "nand_dma_read: unable to allocate dma channel: %d\n",
165 (int)hndl);
166 panic("\n");
167 }
168
169 while (len_left > 0) {
170 if (len_left > DMA_MAX_LEN) {
171 tmp_len = DMA_MAX_LEN;
172 len_left -= DMA_MAX_LEN;
173 } else {
174 tmp_len = len_left;
175 len_left = 0;
176 }
177
178 init_completion(&nand_comp);
179 dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR,
180 physPtr + offset, tmp_len);
181 wait_for_completion(&nand_comp);
182
183 offset += tmp_len;
184 }
185
186 dma_free_channel(hndl);
187
188 if (buf != NULL)
189 memcpy(buf, virtPtr, len);
190}
191
192static void nand_dma_write(const void *buf, int len)
193{
194 int offset = 0;
195 int tmp_len = 0;
196 int len_left = len;
197 DMA_Handle_t hndl;
198
199 if (buf == NULL)
200 panic("nand_dma_write: buf == NULL\n");
201
202 if (virtPtr == NULL)
203 panic("nand_dma_write: virtPtr == NULL\n");
204
205 if ((void *)physPtr == NULL)
206 panic("nand_dma_write: physPtr == NULL\n");
207
208 memcpy(virtPtr, buf, len);
209
210
211 hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
212 if (hndl < 0) {
213 printk(KERN_ERR
214 "nand_dma_write: unable to allocate dma channel: %d\n",
215 (int)hndl);
216 panic("\n");
217 }
218
219 while (len_left > 0) {
220 if (len_left > DMA_MAX_LEN) {
221 tmp_len = DMA_MAX_LEN;
222 len_left -= DMA_MAX_LEN;
223 } else {
224 tmp_len = len_left;
225 len_left = 0;
226 }
227
228 init_completion(&nand_comp);
229 dma_transfer_mem_to_mem(hndl, physPtr + offset,
230 REG_NAND_DATA_PADDR, tmp_len);
231 wait_for_completion(&nand_comp);
232
233 offset += tmp_len;
234 }
235
236 dma_free_channel(hndl);
237}
238
239#endif
240
241static int nand_dev_ready(struct mtd_info *mtd)
242{
243 return nand_bcm_umi_dev_ready();
244}
245
246/****************************************************************************
247*
248* bcm_umi_nand_inithw
249*
250* This routine does the necessary hardware (board-specific)
251* initializations. This includes setting up the timings, etc.
252*
253***************************************************************************/
254int bcm_umi_nand_inithw(void)
255{
256 /* Configure nand timing parameters */
257 REG_UMI_NAND_TCR &= ~0x7ffff;
258 REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
259
260#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
261 /* enable software control of CS */
262 REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
263#endif
264
265 /* keep NAND chip select asserted */
266 REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
267
268 REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
269 /* enable writes to flash */
270 REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
271
272 writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
273 nand_bcm_umi_wait_till_ready();
274
275#if NAND_ECC_BCH
276 nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES);
277#endif
278
279 return 0;
280}
281
282/* Used to turn latch the proper register for access. */
283static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd,
284 unsigned int ctrl)
285{
286 /* send command to hardware */
287 struct nand_chip *chip = mtd->priv;
288 if (ctrl & NAND_CTRL_CHANGE) {
289 if (ctrl & NAND_CLE) {
290 chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET;
291 goto CMD;
292 }
293 if (ctrl & NAND_ALE) {
294 chip->IO_ADDR_W =
295 bcm_umi_io_base + REG_NAND_ADDR_OFFSET;
296 goto CMD;
297 }
298 chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
299 }
300
301CMD:
302 /* Send command to chip directly */
303 if (cmd != NAND_CMD_NONE)
304 writeb(cmd, chip->IO_ADDR_W);
305}
306
307static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
308 int len)
309{
310 if (USE_DIRECT_IO(len)) {
311 /* Do it the old way if the buffer is small or too large.
312 * Probably quicker than starting and checking dma. */
313 int i;
314 struct nand_chip *this = mtd->priv;
315
316 for (i = 0; i < len; i++)
317 writeb(buf[i], this->IO_ADDR_W);
318 }
319#if USE_DMA
320 else
321 nand_dma_write(buf, len);
322#endif
323}
324
325static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
326{
327 if (USE_DIRECT_IO(len)) {
328 int i;
329 struct nand_chip *this = mtd->priv;
330
331 for (i = 0; i < len; i++)
332 buf[i] = readb(this->IO_ADDR_R);
333 }
334#if USE_DMA
335 else
336 nand_dma_read(buf, len);
337#endif
338}
339
340static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
341static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf,
342 int len)
343{
344 /*
345 * Try to readback page with ECC correction. This is necessary
346 * for MLC parts which may have permanently stuck bits.
347 */
348 struct nand_chip *chip = mtd->priv;
349 int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0);
350 if (ret < 0)
351 return -EFAULT;
352 else {
353 if (memcmp(readbackbuf, buf, len) == 0)
354 return 0;
355
356 return -EFAULT;
357 }
358 return 0;
359}
360
361static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
362{
363 struct nand_chip *this;
364 struct resource *r;
365 int err = 0;
366
367 printk(gBanner);
368
369 /* Allocate memory for MTD device structure and private data */
370 board_mtd =
371 kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
372 GFP_KERNEL);
373 if (!board_mtd) {
374 printk(KERN_WARNING
375 "Unable to allocate NAND MTD device structure.\n");
376 return -ENOMEM;
377 }
378
379 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
380
381 if (!r)
382 return -ENXIO;
383
384 /* map physical adress */
385 bcm_umi_io_base = ioremap(r->start, r->end - r->start + 1);
386
387 if (!bcm_umi_io_base) {
388 printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n");
389 kfree(board_mtd);
390 return -EIO;
391 }
392
393 /* Get pointer to private data */
394 this = (struct nand_chip *)(&board_mtd[1]);
395
396 /* Initialize structures */
397 memset((char *)board_mtd, 0, sizeof(struct mtd_info));
398 memset((char *)this, 0, sizeof(struct nand_chip));
399
400 /* Link the private data with the MTD structure */
401 board_mtd->priv = this;
402
403 /* Initialize the NAND hardware. */
404 if (bcm_umi_nand_inithw() < 0) {
405 printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n");
406 iounmap(bcm_umi_io_base);
407 kfree(board_mtd);
408 return -EIO;
409 }
410
411 /* Set address of NAND IO lines */
412 this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
413 this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
414
415 /* Set command delay time, see datasheet for correct value */
416 this->chip_delay = 0;
417 /* Assign the device ready function, if available */
418 this->dev_ready = nand_dev_ready;
419 this->options = 0;
420
421 this->write_buf = bcm_umi_nand_write_buf;
422 this->read_buf = bcm_umi_nand_read_buf;
423 this->verify_buf = bcm_umi_nand_verify_buf;
424
425 this->cmd_ctrl = bcm_umi_nand_hwcontrol;
426 this->ecc.mode = NAND_ECC_HW;
427 this->ecc.size = 512;
428 this->ecc.bytes = NAND_ECC_NUM_BYTES;
429#if NAND_ECC_BCH
430 this->ecc.read_page = bcm_umi_bch_read_page_hwecc;
431 this->ecc.write_page = bcm_umi_bch_write_page_hwecc;
432#else
433 this->ecc.correct = nand_correct_data512;
434 this->ecc.calculate = bcm_umi_hamming_get_hw_ecc;
435 this->ecc.hwctl = bcm_umi_hamming_enable_hwecc;
436#endif
437
438#if USE_DMA
439 err = nand_dma_init();
440 if (err != 0)
441 return err;
442#endif
443
444 /* Figure out the size of the device that we have.
445 * We need to do this to figure out which ECC
446 * layout we'll be using.
447 */
448
449 err = nand_scan_ident(board_mtd, 1);
450 if (err) {
451 printk(KERN_ERR "nand_scan failed: %d\n", err);
452 iounmap(bcm_umi_io_base);
453 kfree(board_mtd);
454 return err;
455 }
456
457 /* Now that we know the nand size, we can setup the ECC layout */
458
459 switch (board_mtd->writesize) { /* writesize is the pagesize */
460 case 4096:
461 this->ecc.layout = &nand_hw_eccoob_4096;
462 break;
463 case 2048:
464 this->ecc.layout = &nand_hw_eccoob_2048;
465 break;
466 case 512:
467 this->ecc.layout = &nand_hw_eccoob_512;
468 break;
469 default:
470 {
471 printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n",
472 board_mtd->writesize);
473 return -EINVAL;
474 }
475 }
476
477#if NAND_ECC_BCH
478 if (board_mtd->writesize > 512) {
479 if (this->options & NAND_USE_FLASH_BBT)
480 largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
481 this->badblock_pattern = &largepage_bbt;
482 }
483#endif
484
485 /* Now finish off the scan, now that ecc.layout has been initialized. */
486
487 err = nand_scan_tail(board_mtd);
488 if (err) {
489 printk(KERN_ERR "nand_scan failed: %d\n", err);
490 iounmap(bcm_umi_io_base);
491 kfree(board_mtd);
492 return err;
493 }
494
495 /* Register the partitions */
496 {
497 int nr_partitions;
498 struct mtd_partition *partition_info;
499
500 board_mtd->name = "bcm_umi-nand";
501 nr_partitions =
502 parse_mtd_partitions(board_mtd, part_probes,
503 &partition_info, 0);
504
505 if (nr_partitions <= 0) {
506 printk(KERN_ERR "BCM UMI NAND: Too few partitions - %d\n",
507 nr_partitions);
508 iounmap(bcm_umi_io_base);
509 kfree(board_mtd);
510 return -EIO;
511 }
512 add_mtd_partitions(board_mtd, partition_info, nr_partitions);
513 }
514
515 /* Return happy */
516 return 0;
517}
518
519static int bcm_umi_nand_remove(struct platform_device *pdev)
520{
521#if USE_DMA
522 nand_dma_term();
523#endif
524
525 /* Release resources, unregister device */
526 nand_release(board_mtd);
527
528 /* unmap physical adress */
529 iounmap(bcm_umi_io_base);
530
531 /* Free the MTD device structure */
532 kfree(board_mtd);
533
534 return 0;
535}
536
537#ifdef CONFIG_PM
538static int bcm_umi_nand_suspend(struct platform_device *pdev,
539 pm_message_t state)
540{
541 printk(KERN_ERR "MTD NAND suspend is being called\n");
542 return 0;
543}
544
545static int bcm_umi_nand_resume(struct platform_device *pdev)
546{
547 printk(KERN_ERR "MTD NAND resume is being called\n");
548 return 0;
549}
550#else
551#define bcm_umi_nand_suspend NULL
552#define bcm_umi_nand_resume NULL
553#endif
554
555static struct platform_driver nand_driver = {
556 .driver = {
557 .name = "bcm-nand",
558 .owner = THIS_MODULE,
559 },
560 .probe = bcm_umi_nand_probe,
561 .remove = bcm_umi_nand_remove,
562 .suspend = bcm_umi_nand_suspend,
563 .resume = bcm_umi_nand_resume,
564};
565
566static int __init nand_init(void)
567{
568 return platform_driver_register(&nand_driver);
569}
570
571static void __exit nand_exit(void)
572{
573 platform_driver_unregister(&nand_driver);
574}
575
576module_init(nand_init);
577module_exit(nand_exit);
578
579MODULE_LICENSE("GPL");
580MODULE_AUTHOR("Broadcom");
581MODULE_DESCRIPTION("BCM UMI MTD NAND driver");
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index f13f5b9afaf7..fe3eba87de40 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -591,6 +591,8 @@ static int __init nand_davinci_probe(struct platform_device *pdev)
591 591
592 /* options such as NAND_USE_FLASH_BBT or 16-bit widths */ 592 /* options such as NAND_USE_FLASH_BBT or 16-bit widths */
593 info->chip.options = pdata->options; 593 info->chip.options = pdata->options;
594 info->chip.bbt_td = pdata->bbt_td;
595 info->chip.bbt_md = pdata->bbt_md;
594 596
595 info->ioaddr = (uint32_t __force) vaddr; 597 info->ioaddr = (uint32_t __force) vaddr;
596 598
@@ -599,7 +601,7 @@ static int __init nand_davinci_probe(struct platform_device *pdev)
599 info->mask_chipsel = pdata->mask_chipsel; 601 info->mask_chipsel = pdata->mask_chipsel;
600 602
601 /* use nandboot-capable ALE/CLE masks by default */ 603 /* use nandboot-capable ALE/CLE masks by default */
602 info->mask_ale = pdata->mask_cle ? : MASK_ALE; 604 info->mask_ale = pdata->mask_ale ? : MASK_ALE;
603 info->mask_cle = pdata->mask_cle ? : MASK_CLE; 605 info->mask_cle = pdata->mask_cle ? : MASK_CLE;
604 606
605 /* Set address of hardware control function */ 607 /* Set address of hardware control function */
diff --git a/drivers/mtd/nand/excite_nandflash.c b/drivers/mtd/nand/excite_nandflash.c
index 72446fb48d4b..af6a6a5399e1 100644
--- a/drivers/mtd/nand/excite_nandflash.c
+++ b/drivers/mtd/nand/excite_nandflash.c
@@ -128,7 +128,7 @@ static int excite_nand_devready(struct mtd_info *mtd)
128 * The binding to the mtd and all allocated 128 * The binding to the mtd and all allocated
129 * resources are released. 129 * resources are released.
130 */ 130 */
131static int __exit excite_nand_remove(struct platform_device *dev) 131static int __devexit excite_nand_remove(struct platform_device *dev)
132{ 132{
133 struct excite_nand_drvdata * const this = platform_get_drvdata(dev); 133 struct excite_nand_drvdata * const this = platform_get_drvdata(dev);
134 134
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index ddd37d2554ed..ae30fb6eed97 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -237,12 +237,15 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
237 237
238 ctrl->use_mdr = 0; 238 ctrl->use_mdr = 0;
239 239
240 dev_vdbg(ctrl->dev, 240 if (ctrl->status != LTESR_CC) {
241 "fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n", 241 dev_info(ctrl->dev,
242 ctrl->status, ctrl->mdr, in_be32(&lbc->fmr)); 242 "command failed: fir %x fcr %x status %x mdr %x\n",
243 in_be32(&lbc->fir), in_be32(&lbc->fcr),
244 ctrl->status, ctrl->mdr);
245 return -EIO;
246 }
243 247
244 /* returns 0 on success otherwise non-zero) */ 248 return 0;
245 return ctrl->status == LTESR_CC ? 0 : -EIO;
246} 249}
247 250
248static void fsl_elbc_do_read(struct nand_chip *chip, int oob) 251static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
@@ -253,17 +256,17 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
253 256
254 if (priv->page_size) { 257 if (priv->page_size) {
255 out_be32(&lbc->fir, 258 out_be32(&lbc->fir,
256 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 259 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
257 (FIR_OP_CA << FIR_OP1_SHIFT) | 260 (FIR_OP_CA << FIR_OP1_SHIFT) |
258 (FIR_OP_PA << FIR_OP2_SHIFT) | 261 (FIR_OP_PA << FIR_OP2_SHIFT) |
259 (FIR_OP_CW1 << FIR_OP3_SHIFT) | 262 (FIR_OP_CM1 << FIR_OP3_SHIFT) |
260 (FIR_OP_RBW << FIR_OP4_SHIFT)); 263 (FIR_OP_RBW << FIR_OP4_SHIFT));
261 264
262 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | 265 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
263 (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); 266 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
264 } else { 267 } else {
265 out_be32(&lbc->fir, 268 out_be32(&lbc->fir,
266 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 269 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
267 (FIR_OP_CA << FIR_OP1_SHIFT) | 270 (FIR_OP_CA << FIR_OP1_SHIFT) |
268 (FIR_OP_PA << FIR_OP2_SHIFT) | 271 (FIR_OP_PA << FIR_OP2_SHIFT) |
269 (FIR_OP_RBW << FIR_OP3_SHIFT)); 272 (FIR_OP_RBW << FIR_OP3_SHIFT));
@@ -332,7 +335,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
332 case NAND_CMD_READID: 335 case NAND_CMD_READID:
333 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); 336 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
334 337
335 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) | 338 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
336 (FIR_OP_UA << FIR_OP1_SHIFT) | 339 (FIR_OP_UA << FIR_OP1_SHIFT) |
337 (FIR_OP_RBW << FIR_OP2_SHIFT)); 340 (FIR_OP_RBW << FIR_OP2_SHIFT));
338 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT); 341 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
@@ -359,16 +362,20 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
359 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); 362 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
360 363
361 out_be32(&lbc->fir, 364 out_be32(&lbc->fir,
362 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 365 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
363 (FIR_OP_PA << FIR_OP1_SHIFT) | 366 (FIR_OP_PA << FIR_OP1_SHIFT) |
364 (FIR_OP_CM1 << FIR_OP2_SHIFT)); 367 (FIR_OP_CM2 << FIR_OP2_SHIFT) |
368 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
369 (FIR_OP_RS << FIR_OP4_SHIFT));
365 370
366 out_be32(&lbc->fcr, 371 out_be32(&lbc->fcr,
367 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | 372 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
368 (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT)); 373 (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
374 (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
369 375
370 out_be32(&lbc->fbcr, 0); 376 out_be32(&lbc->fbcr, 0);
371 ctrl->read_bytes = 0; 377 ctrl->read_bytes = 0;
378 ctrl->use_mdr = 1;
372 379
373 fsl_elbc_run_command(mtd); 380 fsl_elbc_run_command(mtd);
374 return; 381 return;
@@ -383,40 +390,41 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
383 390
384 ctrl->column = column; 391 ctrl->column = column;
385 ctrl->oob = 0; 392 ctrl->oob = 0;
393 ctrl->use_mdr = 1;
386 394
387 if (priv->page_size) { 395 fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
388 fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) | 396 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) |
389 (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT); 397 (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
390 398
399 if (priv->page_size) {
391 out_be32(&lbc->fir, 400 out_be32(&lbc->fir,
392 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 401 (FIR_OP_CM2 << FIR_OP0_SHIFT) |
393 (FIR_OP_CA << FIR_OP1_SHIFT) | 402 (FIR_OP_CA << FIR_OP1_SHIFT) |
394 (FIR_OP_PA << FIR_OP2_SHIFT) | 403 (FIR_OP_PA << FIR_OP2_SHIFT) |
395 (FIR_OP_WB << FIR_OP3_SHIFT) | 404 (FIR_OP_WB << FIR_OP3_SHIFT) |
396 (FIR_OP_CW1 << FIR_OP4_SHIFT)); 405 (FIR_OP_CM3 << FIR_OP4_SHIFT) |
406 (FIR_OP_CW1 << FIR_OP5_SHIFT) |
407 (FIR_OP_RS << FIR_OP6_SHIFT));
397 } else { 408 } else {
398 fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
399 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
400
401 out_be32(&lbc->fir, 409 out_be32(&lbc->fir,
402 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 410 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
403 (FIR_OP_CM2 << FIR_OP1_SHIFT) | 411 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
404 (FIR_OP_CA << FIR_OP2_SHIFT) | 412 (FIR_OP_CA << FIR_OP2_SHIFT) |
405 (FIR_OP_PA << FIR_OP3_SHIFT) | 413 (FIR_OP_PA << FIR_OP3_SHIFT) |
406 (FIR_OP_WB << FIR_OP4_SHIFT) | 414 (FIR_OP_WB << FIR_OP4_SHIFT) |
407 (FIR_OP_CW1 << FIR_OP5_SHIFT)); 415 (FIR_OP_CM3 << FIR_OP5_SHIFT) |
416 (FIR_OP_CW1 << FIR_OP6_SHIFT) |
417 (FIR_OP_RS << FIR_OP7_SHIFT));
408 418
409 if (column >= mtd->writesize) { 419 if (column >= mtd->writesize) {
410 /* OOB area --> READOOB */ 420 /* OOB area --> READOOB */
411 column -= mtd->writesize; 421 column -= mtd->writesize;
412 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; 422 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
413 ctrl->oob = 1; 423 ctrl->oob = 1;
414 } else if (column < 256) { 424 } else {
425 WARN_ON(column != 0);
415 /* First 256 bytes --> READ0 */ 426 /* First 256 bytes --> READ0 */
416 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; 427 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
417 } else {
418 /* Second 256 bytes --> READ1 */
419 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
420 } 428 }
421 } 429 }
422 430
@@ -628,22 +636,6 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
628{ 636{
629 struct fsl_elbc_mtd *priv = chip->priv; 637 struct fsl_elbc_mtd *priv = chip->priv;
630 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 638 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
631 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
632
633 if (ctrl->status != LTESR_CC)
634 return NAND_STATUS_FAIL;
635
636 /* Use READ_STATUS command, but wait for the device to be ready */
637 ctrl->use_mdr = 0;
638 out_be32(&lbc->fir,
639 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
640 (FIR_OP_RBW << FIR_OP1_SHIFT));
641 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
642 out_be32(&lbc->fbcr, 1);
643 set_addr(mtd, 0, 0, 0);
644 ctrl->read_bytes = 1;
645
646 fsl_elbc_run_command(mtd);
647 639
648 if (ctrl->status != LTESR_CC) 640 if (ctrl->status != LTESR_CC)
649 return NAND_STATUS_FAIL; 641 return NAND_STATUS_FAIL;
@@ -651,8 +643,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
651 /* The chip always seems to report that it is 643 /* The chip always seems to report that it is
652 * write-protected, even when it is not. 644 * write-protected, even when it is not.
653 */ 645 */
654 setbits8(ctrl->addr, NAND_STATUS_WP); 646 return (ctrl->mdr & 0xff) | NAND_STATUS_WP;
655 return fsl_elbc_read_byte(mtd);
656} 647}
657 648
658static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) 649static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
@@ -946,6 +937,13 @@ static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
946{ 937{
947 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; 938 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
948 939
940 /*
941 * NAND transactions can tie up the bus for a long time, so set the
942 * bus timeout to max by clearing LBCR[BMT] (highest base counter
943 * value) and setting LBCR[BMTPS] to the highest prescaler value.
944 */
945 clrsetbits_be32(&lbc->lbcr, LBCR_BMT, 15);
946
949 /* clear event registers */ 947 /* clear event registers */
950 setbits32(&lbc->ltesr, LTESR_NAND_MASK); 948 setbits32(&lbc->ltesr, LTESR_NAND_MASK);
951 out_be32(&lbc->lteatr, 0); 949 out_be32(&lbc->lteatr, 0);
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index d120cd8d7267..071a60cb4204 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -112,7 +112,7 @@ static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
112 112
113 if (mchip_nr == -1) { 113 if (mchip_nr == -1) {
114 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); 114 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
115 } else if (mchip_nr >= 0) { 115 } else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
116 fun->mchip_number = mchip_nr; 116 fun->mchip_number = mchip_nr;
117 chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr]; 117 chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
118 chip->IO_ADDR_W = chip->IO_ADDR_R; 118 chip->IO_ADDR_W = chip->IO_ADDR_R;
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 65b26d5a5c0d..45dec5770da0 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -33,9 +33,13 @@
33 33
34#include <asm/mach/flash.h> 34#include <asm/mach/flash.h>
35#include <mach/mxc_nand.h> 35#include <mach/mxc_nand.h>
36#include <mach/hardware.h>
36 37
37#define DRIVER_NAME "mxc_nand" 38#define DRIVER_NAME "mxc_nand"
38 39
40#define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
41#define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27())
42
39/* Addresses for NFC registers */ 43/* Addresses for NFC registers */
40#define NFC_BUF_SIZE 0xE00 44#define NFC_BUF_SIZE 0xE00
41#define NFC_BUF_ADDR 0xE04 45#define NFC_BUF_ADDR 0xE04
@@ -46,24 +50,14 @@
46#define NFC_RSLTMAIN_AREA 0xE0E 50#define NFC_RSLTMAIN_AREA 0xE0E
47#define NFC_RSLTSPARE_AREA 0xE10 51#define NFC_RSLTSPARE_AREA 0xE10
48#define NFC_WRPROT 0xE12 52#define NFC_WRPROT 0xE12
49#define NFC_UNLOCKSTART_BLKADDR 0xE14 53#define NFC_V1_UNLOCKSTART_BLKADDR 0xe14
50#define NFC_UNLOCKEND_BLKADDR 0xE16 54#define NFC_V1_UNLOCKEND_BLKADDR 0xe16
55#define NFC_V21_UNLOCKSTART_BLKADDR 0xe20
56#define NFC_V21_UNLOCKEND_BLKADDR 0xe22
51#define NFC_NF_WRPRST 0xE18 57#define NFC_NF_WRPRST 0xE18
52#define NFC_CONFIG1 0xE1A 58#define NFC_CONFIG1 0xE1A
53#define NFC_CONFIG2 0xE1C 59#define NFC_CONFIG2 0xE1C
54 60
55/* Addresses for NFC RAM BUFFER Main area 0 */
56#define MAIN_AREA0 0x000
57#define MAIN_AREA1 0x200
58#define MAIN_AREA2 0x400
59#define MAIN_AREA3 0x600
60
61/* Addresses for NFC SPARE BUFFER Spare area 0 */
62#define SPARE_AREA0 0x800
63#define SPARE_AREA1 0x810
64#define SPARE_AREA2 0x820
65#define SPARE_AREA3 0x830
66
67/* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register 61/* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
68 * for Command operation */ 62 * for Command operation */
69#define NFC_CMD 0x1 63#define NFC_CMD 0x1
@@ -106,48 +100,66 @@ struct mxc_nand_host {
106 struct mtd_partition *parts; 100 struct mtd_partition *parts;
107 struct device *dev; 101 struct device *dev;
108 102
103 void *spare0;
104 void *main_area0;
105 void *main_area1;
106
107 void __iomem *base;
109 void __iomem *regs; 108 void __iomem *regs;
110 int spare_only;
111 int status_request; 109 int status_request;
112 int pagesize_2k;
113 uint16_t col_addr;
114 struct clk *clk; 110 struct clk *clk;
115 int clk_act; 111 int clk_act;
116 int irq; 112 int irq;
117 113
118 wait_queue_head_t irq_waitq; 114 wait_queue_head_t irq_waitq;
119};
120
121/* Define delays in microsec for NAND device operations */
122#define TROP_US_DELAY 2000
123/* Macros to get byte and bit positions of ECC */
124#define COLPOS(x) ((x) >> 3)
125#define BITPOS(x) ((x) & 0xf)
126 115
127/* Define single bit Error positions in Main & Spare area */ 116 uint8_t *data_buf;
128#define MAIN_SINGLEBIT_ERROR 0x4 117 unsigned int buf_start;
129#define SPARE_SINGLEBIT_ERROR 0x1 118 int spare_len;
130
131/* OOB placement block for use with hardware ecc generation */
132static struct nand_ecclayout nand_hw_eccoob_8 = {
133 .eccbytes = 5,
134 .eccpos = {6, 7, 8, 9, 10},
135 .oobfree = {{0, 5}, {11, 5}, }
136}; 119};
137 120
138static struct nand_ecclayout nand_hw_eccoob_16 = { 121/* OOB placement block for use with hardware ecc generation */
122static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
139 .eccbytes = 5, 123 .eccbytes = 5,
140 .eccpos = {6, 7, 8, 9, 10}, 124 .eccpos = {6, 7, 8, 9, 10},
141 .oobfree = {{0, 5}, {11, 5}, } 125 .oobfree = {{0, 5}, {12, 4}, }
142}; 126};
143 127
144static struct nand_ecclayout nand_hw_eccoob_64 = { 128static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
145 .eccbytes = 20, 129 .eccbytes = 20,
146 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, 130 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
147 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, 131 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
148 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } 132 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
149}; 133};
150 134
135/* OOB description for 512 byte pages with 16 byte OOB */
136static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
137 .eccbytes = 1 * 9,
138 .eccpos = {
139 7, 8, 9, 10, 11, 12, 13, 14, 15
140 },
141 .oobfree = {
142 {.offset = 0, .length = 5}
143 }
144};
145
146/* OOB description for 2048 byte pages with 64 byte OOB */
147static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
148 .eccbytes = 4 * 9,
149 .eccpos = {
150 7, 8, 9, 10, 11, 12, 13, 14, 15,
151 23, 24, 25, 26, 27, 28, 29, 30, 31,
152 39, 40, 41, 42, 43, 44, 45, 46, 47,
153 55, 56, 57, 58, 59, 60, 61, 62, 63
154 },
155 .oobfree = {
156 {.offset = 2, .length = 4},
157 {.offset = 16, .length = 7},
158 {.offset = 32, .length = 7},
159 {.offset = 48, .length = 7}
160 }
161};
162
151#ifdef CONFIG_MTD_PARTITIONS 163#ifdef CONFIG_MTD_PARTITIONS
152static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL }; 164static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
153#endif 165#endif
@@ -170,10 +182,10 @@ static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
170/* This function polls the NANDFC to wait for the basic operation to 182/* This function polls the NANDFC to wait for the basic operation to
171 * complete by checking the INT bit of config2 register. 183 * complete by checking the INT bit of config2 register.
172 */ 184 */
173static void wait_op_done(struct mxc_nand_host *host, int max_retries, 185static void wait_op_done(struct mxc_nand_host *host, int useirq)
174 uint16_t param, int useirq)
175{ 186{
176 uint32_t tmp; 187 uint32_t tmp;
188 int max_retries = 2000;
177 189
178 if (useirq) { 190 if (useirq) {
179 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) { 191 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
@@ -200,8 +212,8 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries,
200 udelay(1); 212 udelay(1);
201 } 213 }
202 if (max_retries < 0) 214 if (max_retries < 0)
203 DEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n", 215 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
204 __func__, param); 216 __func__);
205 } 217 }
206} 218}
207 219
@@ -215,7 +227,7 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
215 writew(NFC_CMD, host->regs + NFC_CONFIG2); 227 writew(NFC_CMD, host->regs + NFC_CONFIG2);
216 228
217 /* Wait for operation to complete */ 229 /* Wait for operation to complete */
218 wait_op_done(host, TROP_US_DELAY, cmd, useirq); 230 wait_op_done(host, useirq);
219} 231}
220 232
221/* This function sends an address (or partial address) to the 233/* This function sends an address (or partial address) to the
@@ -229,82 +241,47 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
229 writew(NFC_ADDR, host->regs + NFC_CONFIG2); 241 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
230 242
231 /* Wait for operation to complete */ 243 /* Wait for operation to complete */
232 wait_op_done(host, TROP_US_DELAY, addr, islast); 244 wait_op_done(host, islast);
233} 245}
234 246
235/* This function requests the NANDFC to initate the transfer 247static void send_page(struct mtd_info *mtd, unsigned int ops)
236 * of data currently in the NANDFC RAM buffer to the NAND device. */
237static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
238 int spare_only)
239{ 248{
240 DEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only); 249 struct nand_chip *nand_chip = mtd->priv;
241 250 struct mxc_nand_host *host = nand_chip->priv;
242 /* NANDFC buffer 0 is used for page read/write */ 251 int bufs, i;
243 writew(buf_id, host->regs + NFC_BUF_ADDR);
244
245 /* Configure spare or page+spare access */
246 if (!host->pagesize_2k) {
247 uint16_t config1 = readw(host->regs + NFC_CONFIG1);
248 if (spare_only)
249 config1 |= NFC_SP_EN;
250 else
251 config1 &= ~(NFC_SP_EN);
252 writew(config1, host->regs + NFC_CONFIG1);
253 }
254 252
255 writew(NFC_INPUT, host->regs + NFC_CONFIG2); 253 if (nfc_is_v1() && mtd->writesize > 512)
254 bufs = 4;
255 else
256 bufs = 1;
256 257
257 /* Wait for operation to complete */ 258 for (i = 0; i < bufs; i++) {
258 wait_op_done(host, TROP_US_DELAY, spare_only, true);
259}
260 259
261/* Requests NANDFC to initated the transfer of data from the 260 /* NANDFC buffer 0 is used for page read/write */
262 * NAND device into in the NANDFC ram buffer. */ 261 writew(i, host->regs + NFC_BUF_ADDR);
263static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
264 int spare_only)
265{
266 DEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
267 262
268 /* NANDFC buffer 0 is used for page read/write */ 263 writew(ops, host->regs + NFC_CONFIG2);
269 writew(buf_id, host->regs + NFC_BUF_ADDR);
270 264
271 /* Configure spare or page+spare access */ 265 /* Wait for operation to complete */
272 if (!host->pagesize_2k) { 266 wait_op_done(host, true);
273 uint32_t config1 = readw(host->regs + NFC_CONFIG1);
274 if (spare_only)
275 config1 |= NFC_SP_EN;
276 else
277 config1 &= ~NFC_SP_EN;
278 writew(config1, host->regs + NFC_CONFIG1);
279 } 267 }
280
281 writew(NFC_OUTPUT, host->regs + NFC_CONFIG2);
282
283 /* Wait for operation to complete */
284 wait_op_done(host, TROP_US_DELAY, spare_only, true);
285} 268}
286 269
287/* Request the NANDFC to perform a read of the NAND device ID. */ 270/* Request the NANDFC to perform a read of the NAND device ID. */
288static void send_read_id(struct mxc_nand_host *host) 271static void send_read_id(struct mxc_nand_host *host)
289{ 272{
290 struct nand_chip *this = &host->nand; 273 struct nand_chip *this = &host->nand;
291 uint16_t tmp;
292 274
293 /* NANDFC buffer 0 is used for device ID output */ 275 /* NANDFC buffer 0 is used for device ID output */
294 writew(0x0, host->regs + NFC_BUF_ADDR); 276 writew(0x0, host->regs + NFC_BUF_ADDR);
295 277
296 /* Read ID into main buffer */
297 tmp = readw(host->regs + NFC_CONFIG1);
298 tmp &= ~NFC_SP_EN;
299 writew(tmp, host->regs + NFC_CONFIG1);
300
301 writew(NFC_ID, host->regs + NFC_CONFIG2); 278 writew(NFC_ID, host->regs + NFC_CONFIG2);
302 279
303 /* Wait for operation to complete */ 280 /* Wait for operation to complete */
304 wait_op_done(host, TROP_US_DELAY, 0, true); 281 wait_op_done(host, true);
305 282
306 if (this->options & NAND_BUSWIDTH_16) { 283 if (this->options & NAND_BUSWIDTH_16) {
307 void __iomem *main_buf = host->regs + MAIN_AREA0; 284 void __iomem *main_buf = host->main_area0;
308 /* compress the ID info */ 285 /* compress the ID info */
309 writeb(readb(main_buf + 2), main_buf + 1); 286 writeb(readb(main_buf + 2), main_buf + 1);
310 writeb(readb(main_buf + 4), main_buf + 2); 287 writeb(readb(main_buf + 4), main_buf + 2);
@@ -312,15 +289,16 @@ static void send_read_id(struct mxc_nand_host *host)
312 writeb(readb(main_buf + 8), main_buf + 4); 289 writeb(readb(main_buf + 8), main_buf + 4);
313 writeb(readb(main_buf + 10), main_buf + 5); 290 writeb(readb(main_buf + 10), main_buf + 5);
314 } 291 }
292 memcpy(host->data_buf, host->main_area0, 16);
315} 293}
316 294
317/* This function requests the NANDFC to perform a read of the 295/* This function requests the NANDFC to perform a read of the
318 * NAND device status and returns the current status. */ 296 * NAND device status and returns the current status. */
319static uint16_t get_dev_status(struct mxc_nand_host *host) 297static uint16_t get_dev_status(struct mxc_nand_host *host)
320{ 298{
321 void __iomem *main_buf = host->regs + MAIN_AREA1; 299 void __iomem *main_buf = host->main_area1;
322 uint32_t store; 300 uint32_t store;
323 uint16_t ret, tmp; 301 uint16_t ret;
324 /* Issue status request to NAND device */ 302 /* Issue status request to NAND device */
325 303
326 /* store the main area1 first word, later do recovery */ 304 /* store the main area1 first word, later do recovery */
@@ -329,15 +307,10 @@ static uint16_t get_dev_status(struct mxc_nand_host *host)
329 * corruption of read/write buffer on status requests. */ 307 * corruption of read/write buffer on status requests. */
330 writew(1, host->regs + NFC_BUF_ADDR); 308 writew(1, host->regs + NFC_BUF_ADDR);
331 309
332 /* Read status into main buffer */
333 tmp = readw(host->regs + NFC_CONFIG1);
334 tmp &= ~NFC_SP_EN;
335 writew(tmp, host->regs + NFC_CONFIG1);
336
337 writew(NFC_STATUS, host->regs + NFC_CONFIG2); 310 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
338 311
339 /* Wait for operation to complete */ 312 /* Wait for operation to complete */
340 wait_op_done(host, TROP_US_DELAY, 0, true); 313 wait_op_done(host, true);
341 314
342 /* Status is placed in first word of main buffer */ 315 /* Status is placed in first word of main buffer */
343 /* get status, then recovery area 1 data */ 316 /* get status, then recovery area 1 data */
@@ -397,32 +370,14 @@ static u_char mxc_nand_read_byte(struct mtd_info *mtd)
397{ 370{
398 struct nand_chip *nand_chip = mtd->priv; 371 struct nand_chip *nand_chip = mtd->priv;
399 struct mxc_nand_host *host = nand_chip->priv; 372 struct mxc_nand_host *host = nand_chip->priv;
400 uint8_t ret = 0; 373 uint8_t ret;
401 uint16_t col, rd_word;
402 uint16_t __iomem *main_buf = host->regs + MAIN_AREA0;
403 uint16_t __iomem *spare_buf = host->regs + SPARE_AREA0;
404 374
405 /* Check for status request */ 375 /* Check for status request */
406 if (host->status_request) 376 if (host->status_request)
407 return get_dev_status(host) & 0xFF; 377 return get_dev_status(host) & 0xFF;
408 378
409 /* Get column for 16-bit access */ 379 ret = *(uint8_t *)(host->data_buf + host->buf_start);
410 col = host->col_addr >> 1; 380 host->buf_start++;
411
412 /* If we are accessing the spare region */
413 if (host->spare_only)
414 rd_word = readw(&spare_buf[col]);
415 else
416 rd_word = readw(&main_buf[col]);
417
418 /* Pick upper/lower byte of word from RAM buffer */
419 if (host->col_addr & 0x1)
420 ret = (rd_word >> 8) & 0xFF;
421 else
422 ret = rd_word & 0xFF;
423
424 /* Update saved column address */
425 host->col_addr++;
426 381
427 return ret; 382 return ret;
428} 383}
@@ -431,33 +386,10 @@ static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
431{ 386{
432 struct nand_chip *nand_chip = mtd->priv; 387 struct nand_chip *nand_chip = mtd->priv;
433 struct mxc_nand_host *host = nand_chip->priv; 388 struct mxc_nand_host *host = nand_chip->priv;
434 uint16_t col, rd_word, ret; 389 uint16_t ret;
435 uint16_t __iomem *p;
436
437 DEBUG(MTD_DEBUG_LEVEL3,
438 "mxc_nand_read_word(col = %d)\n", host->col_addr);
439
440 col = host->col_addr;
441 /* Adjust saved column address */
442 if (col < mtd->writesize && host->spare_only)
443 col += mtd->writesize;
444 390
445 if (col < mtd->writesize) 391 ret = *(uint16_t *)(host->data_buf + host->buf_start);
446 p = (host->regs + MAIN_AREA0) + (col >> 1); 392 host->buf_start += 2;
447 else
448 p = (host->regs + SPARE_AREA0) + ((col - mtd->writesize) >> 1);
449
450 if (col & 1) {
451 rd_word = readw(p);
452 ret = (rd_word >> 8) & 0xff;
453 rd_word = readw(&p[1]);
454 ret |= (rd_word << 8) & 0xff00;
455
456 } else
457 ret = readw(p);
458
459 /* Update saved column address */
460 host->col_addr = col + 2;
461 393
462 return ret; 394 return ret;
463} 395}
@@ -470,94 +402,14 @@ static void mxc_nand_write_buf(struct mtd_info *mtd,
470{ 402{
471 struct nand_chip *nand_chip = mtd->priv; 403 struct nand_chip *nand_chip = mtd->priv;
472 struct mxc_nand_host *host = nand_chip->priv; 404 struct mxc_nand_host *host = nand_chip->priv;
473 int n, col, i = 0; 405 u16 col = host->buf_start;
474 406 int n = mtd->oobsize + mtd->writesize - col;
475 DEBUG(MTD_DEBUG_LEVEL3,
476 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
477 len);
478
479 col = host->col_addr;
480 407
481 /* Adjust saved column address */ 408 n = min(n, len);
482 if (col < mtd->writesize && host->spare_only)
483 col += mtd->writesize;
484 409
485 n = mtd->writesize + mtd->oobsize - col; 410 memcpy(host->data_buf + col, buf, n);
486 n = min(len, n);
487
488 DEBUG(MTD_DEBUG_LEVEL3,
489 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
490
491 while (n) {
492 void __iomem *p;
493
494 if (col < mtd->writesize)
495 p = host->regs + MAIN_AREA0 + (col & ~3);
496 else
497 p = host->regs + SPARE_AREA0 -
498 mtd->writesize + (col & ~3);
499
500 DEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
501 __LINE__, p);
502
503 if (((col | (int)&buf[i]) & 3) || n < 16) {
504 uint32_t data = 0;
505
506 if (col & 3 || n < 4)
507 data = readl(p);
508
509 switch (col & 3) {
510 case 0:
511 if (n) {
512 data = (data & 0xffffff00) |
513 (buf[i++] << 0);
514 n--;
515 col++;
516 }
517 case 1:
518 if (n) {
519 data = (data & 0xffff00ff) |
520 (buf[i++] << 8);
521 n--;
522 col++;
523 }
524 case 2:
525 if (n) {
526 data = (data & 0xff00ffff) |
527 (buf[i++] << 16);
528 n--;
529 col++;
530 }
531 case 3:
532 if (n) {
533 data = (data & 0x00ffffff) |
534 (buf[i++] << 24);
535 n--;
536 col++;
537 }
538 }
539
540 writel(data, p);
541 } else {
542 int m = mtd->writesize - col;
543 411
544 if (col >= mtd->writesize) 412 host->buf_start += n;
545 m += mtd->oobsize;
546
547 m = min(n, m) & ~3;
548
549 DEBUG(MTD_DEBUG_LEVEL3,
550 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
551 __func__, __LINE__, n, m, i, col);
552
553 memcpy(p, &buf[i], m);
554 col += m;
555 i += m;
556 n -= m;
557 }
558 }
559 /* Update saved column address */
560 host->col_addr = col;
561} 413}
562 414
563/* Read the data buffer from the NAND Flash. To read the data from NAND 415/* Read the data buffer from the NAND Flash. To read the data from NAND
@@ -568,75 +420,14 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
568{ 420{
569 struct nand_chip *nand_chip = mtd->priv; 421 struct nand_chip *nand_chip = mtd->priv;
570 struct mxc_nand_host *host = nand_chip->priv; 422 struct mxc_nand_host *host = nand_chip->priv;
571 int n, col, i = 0; 423 u16 col = host->buf_start;
572 424 int n = mtd->oobsize + mtd->writesize - col;
573 DEBUG(MTD_DEBUG_LEVEL3,
574 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
575
576 col = host->col_addr;
577 425
578 /* Adjust saved column address */ 426 n = min(n, len);
579 if (col < mtd->writesize && host->spare_only)
580 col += mtd->writesize;
581 427
582 n = mtd->writesize + mtd->oobsize - col; 428 memcpy(buf, host->data_buf + col, len);
583 n = min(len, n);
584
585 while (n) {
586 void __iomem *p;
587
588 if (col < mtd->writesize)
589 p = host->regs + MAIN_AREA0 + (col & ~3);
590 else
591 p = host->regs + SPARE_AREA0 -
592 mtd->writesize + (col & ~3);
593
594 if (((col | (int)&buf[i]) & 3) || n < 16) {
595 uint32_t data;
596
597 data = readl(p);
598 switch (col & 3) {
599 case 0:
600 if (n) {
601 buf[i++] = (uint8_t) (data);
602 n--;
603 col++;
604 }
605 case 1:
606 if (n) {
607 buf[i++] = (uint8_t) (data >> 8);
608 n--;
609 col++;
610 }
611 case 2:
612 if (n) {
613 buf[i++] = (uint8_t) (data >> 16);
614 n--;
615 col++;
616 }
617 case 3:
618 if (n) {
619 buf[i++] = (uint8_t) (data >> 24);
620 n--;
621 col++;
622 }
623 }
624 } else {
625 int m = mtd->writesize - col;
626
627 if (col >= mtd->writesize)
628 m += mtd->oobsize;
629
630 m = min(n, m) & ~3;
631 memcpy(&buf[i], p, m);
632 col += m;
633 i += m;
634 n -= m;
635 }
636 }
637 /* Update saved column address */
638 host->col_addr = col;
639 429
430 host->buf_start += len;
640} 431}
641 432
642/* Used by the upper layer to verify the data in NAND Flash 433/* Used by the upper layer to verify the data in NAND Flash
@@ -654,23 +445,6 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
654 struct nand_chip *nand_chip = mtd->priv; 445 struct nand_chip *nand_chip = mtd->priv;
655 struct mxc_nand_host *host = nand_chip->priv; 446 struct mxc_nand_host *host = nand_chip->priv;
656 447
657#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
658 if (chip > 0) {
659 DEBUG(MTD_DEBUG_LEVEL0,
660 "ERROR: Illegal chip select (chip = %d)\n", chip);
661 return;
662 }
663
664 if (chip == -1) {
665 writew(readw(host->regs + NFC_CONFIG1) & ~NFC_CE,
666 host->regs + NFC_CONFIG1);
667 return;
668 }
669
670 writew(readw(host->regs + NFC_CONFIG1) | NFC_CE,
671 host->regs + NFC_CONFIG1);
672#endif
673
674 switch (chip) { 448 switch (chip) {
675 case -1: 449 case -1:
676 /* Disable the NFC clock */ 450 /* Disable the NFC clock */
@@ -692,94 +466,40 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
692 } 466 }
693} 467}
694 468
695/* Used by the upper layer to write command to NAND Flash for 469/*
696 * different operations to be carried out on NAND Flash */ 470 * Function to transfer data to/from spare area.
697static void mxc_nand_command(struct mtd_info *mtd, unsigned command, 471 */
698 int column, int page_addr) 472static void copy_spare(struct mtd_info *mtd, bool bfrom)
699{ 473{
700 struct nand_chip *nand_chip = mtd->priv; 474 struct nand_chip *this = mtd->priv;
701 struct mxc_nand_host *host = nand_chip->priv; 475 struct mxc_nand_host *host = this->priv;
702 int useirq = true; 476 u16 i, j;
703 477 u16 n = mtd->writesize >> 9;
704 DEBUG(MTD_DEBUG_LEVEL3, 478 u8 *d = host->data_buf + mtd->writesize;
705 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", 479 u8 *s = host->spare0;
706 command, column, page_addr); 480 u16 t = host->spare_len;
707 481
708 /* Reset command state information */ 482 j = (mtd->oobsize / n >> 1) << 1;
709 host->status_request = false; 483
710 484 if (bfrom) {
711 /* Command pre-processing step */ 485 for (i = 0; i < n - 1; i++)
712 switch (command) { 486 memcpy(d + i * j, s + i * t, j);
713 487
714 case NAND_CMD_STATUS: 488 /* the last section */
715 host->col_addr = 0; 489 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
716 host->status_request = true; 490 } else {
717 break; 491 for (i = 0; i < n - 1; i++)
718 492 memcpy(&s[i * t], &d[i * j], j);
719 case NAND_CMD_READ0:
720 host->col_addr = column;
721 host->spare_only = false;
722 useirq = false;
723 break;
724
725 case NAND_CMD_READOOB:
726 host->col_addr = column;
727 host->spare_only = true;
728 useirq = false;
729 if (host->pagesize_2k)
730 command = NAND_CMD_READ0; /* only READ0 is valid */
731 break;
732
733 case NAND_CMD_SEQIN:
734 if (column >= mtd->writesize) {
735 /*
736 * FIXME: before send SEQIN command for write OOB,
737 * We must read one page out.
738 * For K9F1GXX has no READ1 command to set current HW
739 * pointer to spare area, we must write the whole page
740 * including OOB together.
741 */
742 if (host->pagesize_2k)
743 /* call ourself to read a page */
744 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
745 page_addr);
746
747 host->col_addr = column - mtd->writesize;
748 host->spare_only = true;
749
750 /* Set program pointer to spare region */
751 if (!host->pagesize_2k)
752 send_cmd(host, NAND_CMD_READOOB, false);
753 } else {
754 host->spare_only = false;
755 host->col_addr = column;
756
757 /* Set program pointer to page start */
758 if (!host->pagesize_2k)
759 send_cmd(host, NAND_CMD_READ0, false);
760 }
761 useirq = false;
762 break;
763
764 case NAND_CMD_PAGEPROG:
765 send_prog_page(host, 0, host->spare_only);
766
767 if (host->pagesize_2k) {
768 /* data in 4 areas datas */
769 send_prog_page(host, 1, host->spare_only);
770 send_prog_page(host, 2, host->spare_only);
771 send_prog_page(host, 3, host->spare_only);
772 }
773
774 break;
775 493
776 case NAND_CMD_ERASE1: 494 /* the last section */
777 useirq = false; 495 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
778 break;
779 } 496 }
497}
780 498
781 /* Write out the command to the device. */ 499static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
782 send_cmd(host, command, useirq); 500{
501 struct nand_chip *nand_chip = mtd->priv;
502 struct mxc_nand_host *host = nand_chip->priv;
783 503
784 /* Write out column address, if necessary */ 504 /* Write out column address, if necessary */
785 if (column != -1) { 505 if (column != -1) {
@@ -791,7 +511,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
791 * the full page. 511 * the full page.
792 */ 512 */
793 send_addr(host, 0, page_addr == -1); 513 send_addr(host, 0, page_addr == -1);
794 if (host->pagesize_2k) 514 if (mtd->writesize > 512)
795 /* another col addr cycle for 2k page */ 515 /* another col addr cycle for 2k page */
796 send_addr(host, 0, false); 516 send_addr(host, 0, false);
797 } 517 }
@@ -801,7 +521,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
801 /* paddr_0 - p_addr_7 */ 521 /* paddr_0 - p_addr_7 */
802 send_addr(host, (page_addr & 0xff), false); 522 send_addr(host, (page_addr & 0xff), false);
803 523
804 if (host->pagesize_2k) { 524 if (mtd->writesize > 512) {
805 if (mtd->size >= 0x10000000) { 525 if (mtd->size >= 0x10000000) {
806 /* paddr_8 - paddr_15 */ 526 /* paddr_8 - paddr_15 */
807 send_addr(host, (page_addr >> 8) & 0xff, false); 527 send_addr(host, (page_addr >> 8) & 0xff, false);
@@ -820,52 +540,136 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
820 send_addr(host, (page_addr >> 8) & 0xff, true); 540 send_addr(host, (page_addr >> 8) & 0xff, true);
821 } 541 }
822 } 542 }
543}
544
545/* Used by the upper layer to write command to NAND Flash for
546 * different operations to be carried out on NAND Flash */
547static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
548 int column, int page_addr)
549{
550 struct nand_chip *nand_chip = mtd->priv;
551 struct mxc_nand_host *host = nand_chip->priv;
552
553 DEBUG(MTD_DEBUG_LEVEL3,
554 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
555 command, column, page_addr);
556
557 /* Reset command state information */
558 host->status_request = false;
823 559
824 /* Command post-processing step */ 560 /* Command pre-processing step */
825 switch (command) { 561 switch (command) {
826 562
827 case NAND_CMD_RESET: 563 case NAND_CMD_STATUS:
564 host->buf_start = 0;
565 host->status_request = true;
566
567 send_cmd(host, command, true);
568 mxc_do_addr_cycle(mtd, column, page_addr);
828 break; 569 break;
829 570
830 case NAND_CMD_READOOB:
831 case NAND_CMD_READ0: 571 case NAND_CMD_READ0:
832 if (host->pagesize_2k) { 572 case NAND_CMD_READOOB:
833 /* send read confirm command */ 573 if (command == NAND_CMD_READ0)
574 host->buf_start = column;
575 else
576 host->buf_start = column + mtd->writesize;
577
578 if (mtd->writesize > 512)
579 command = NAND_CMD_READ0; /* only READ0 is valid */
580
581 send_cmd(host, command, false);
582 mxc_do_addr_cycle(mtd, column, page_addr);
583
584 if (mtd->writesize > 512)
834 send_cmd(host, NAND_CMD_READSTART, true); 585 send_cmd(host, NAND_CMD_READSTART, true);
835 /* read for each AREA */ 586
836 send_read_page(host, 0, host->spare_only); 587 send_page(mtd, NFC_OUTPUT);
837 send_read_page(host, 1, host->spare_only); 588
838 send_read_page(host, 2, host->spare_only); 589 memcpy(host->data_buf, host->main_area0, mtd->writesize);
839 send_read_page(host, 3, host->spare_only); 590 copy_spare(mtd, true);
840 } else
841 send_read_page(host, 0, host->spare_only);
842 break; 591 break;
843 592
844 case NAND_CMD_READID: 593 case NAND_CMD_SEQIN:
845 host->col_addr = 0; 594 if (column >= mtd->writesize) {
846 send_read_id(host); 595 /*
596 * FIXME: before send SEQIN command for write OOB,
597 * We must read one page out.
598 * For K9F1GXX has no READ1 command to set current HW
599 * pointer to spare area, we must write the whole page
600 * including OOB together.
601 */
602 if (mtd->writesize > 512)
603 /* call ourself to read a page */
604 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
605 page_addr);
606
607 host->buf_start = column;
608
609 /* Set program pointer to spare region */
610 if (mtd->writesize == 512)
611 send_cmd(host, NAND_CMD_READOOB, false);
612 } else {
613 host->buf_start = column;
614
615 /* Set program pointer to page start */
616 if (mtd->writesize == 512)
617 send_cmd(host, NAND_CMD_READ0, false);
618 }
619
620 send_cmd(host, command, false);
621 mxc_do_addr_cycle(mtd, column, page_addr);
847 break; 622 break;
848 623
849 case NAND_CMD_PAGEPROG: 624 case NAND_CMD_PAGEPROG:
625 memcpy(host->main_area0, host->data_buf, mtd->writesize);
626 copy_spare(mtd, false);
627 send_page(mtd, NFC_INPUT);
628 send_cmd(host, command, true);
629 mxc_do_addr_cycle(mtd, column, page_addr);
850 break; 630 break;
851 631
852 case NAND_CMD_STATUS: 632 case NAND_CMD_READID:
633 send_cmd(host, command, true);
634 mxc_do_addr_cycle(mtd, column, page_addr);
635 send_read_id(host);
636 host->buf_start = column;
853 break; 637 break;
854 638
639 case NAND_CMD_ERASE1:
855 case NAND_CMD_ERASE2: 640 case NAND_CMD_ERASE2:
641 send_cmd(host, command, false);
642 mxc_do_addr_cycle(mtd, column, page_addr);
643
856 break; 644 break;
857 } 645 }
858} 646}
859 647
860/* Define some generic bad / good block scan pattern which are used 648/*
861 * while scanning a device for factory marked good / bad blocks. */ 649 * The generic flash bbt decriptors overlap with our ecc
862static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; 650 * hardware, so define some i.MX specific ones.
651 */
652static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
653static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
654
655static struct nand_bbt_descr bbt_main_descr = {
656 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
657 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
658 .offs = 0,
659 .len = 4,
660 .veroffs = 4,
661 .maxblocks = 4,
662 .pattern = bbt_pattern,
663};
863 664
864static struct nand_bbt_descr smallpage_memorybased = { 665static struct nand_bbt_descr bbt_mirror_descr = {
865 .options = NAND_BBT_SCAN2NDPAGE, 666 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
866 .offs = 5, 667 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
867 .len = 1, 668 .offs = 0,
868 .pattern = scan_ff_pattern 669 .len = 4,
670 .veroffs = 4,
671 .maxblocks = 4,
672 .pattern = mirror_pattern,
869}; 673};
870 674
871static int __init mxcnd_probe(struct platform_device *pdev) 675static int __init mxcnd_probe(struct platform_device *pdev)
@@ -877,12 +681,16 @@ static int __init mxcnd_probe(struct platform_device *pdev)
877 struct resource *res; 681 struct resource *res;
878 uint16_t tmp; 682 uint16_t tmp;
879 int err = 0, nr_parts = 0; 683 int err = 0, nr_parts = 0;
684 struct nand_ecclayout *oob_smallpage, *oob_largepage;
880 685
881 /* Allocate memory for MTD device structure and private data */ 686 /* Allocate memory for MTD device structure and private data */
882 host = kzalloc(sizeof(struct mxc_nand_host), GFP_KERNEL); 687 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
688 NAND_MAX_OOBSIZE, GFP_KERNEL);
883 if (!host) 689 if (!host)
884 return -ENOMEM; 690 return -ENOMEM;
885 691
692 host->data_buf = (uint8_t *)(host + 1);
693
886 host->dev = &pdev->dev; 694 host->dev = &pdev->dev;
887 /* structures must be linked */ 695 /* structures must be linked */
888 this = &host->nand; 696 this = &host->nand;
@@ -890,7 +698,7 @@ static int __init mxcnd_probe(struct platform_device *pdev)
890 mtd->priv = this; 698 mtd->priv = this;
891 mtd->owner = THIS_MODULE; 699 mtd->owner = THIS_MODULE;
892 mtd->dev.parent = &pdev->dev; 700 mtd->dev.parent = &pdev->dev;
893 mtd->name = "mxc_nand"; 701 mtd->name = DRIVER_NAME;
894 702
895 /* 50 us command delay time */ 703 /* 50 us command delay time */
896 this->chip_delay = 5; 704 this->chip_delay = 5;
@@ -920,62 +728,93 @@ static int __init mxcnd_probe(struct platform_device *pdev)
920 goto eres; 728 goto eres;
921 } 729 }
922 730
923 host->regs = ioremap(res->start, res->end - res->start + 1); 731 host->base = ioremap(res->start, resource_size(res));
924 if (!host->regs) { 732 if (!host->base) {
925 err = -ENOMEM; 733 err = -ENOMEM;
926 goto eres; 734 goto eres;
927 } 735 }
928 736
737 host->main_area0 = host->base;
738 host->main_area1 = host->base + 0x200;
739
740 if (nfc_is_v21()) {
741 host->regs = host->base + 0x1000;
742 host->spare0 = host->base + 0x1000;
743 host->spare_len = 64;
744 oob_smallpage = &nandv2_hw_eccoob_smallpage;
745 oob_largepage = &nandv2_hw_eccoob_largepage;
746 } else if (nfc_is_v1()) {
747 host->regs = host->base;
748 host->spare0 = host->base + 0x800;
749 host->spare_len = 16;
750 oob_smallpage = &nandv1_hw_eccoob_smallpage;
751 oob_largepage = &nandv1_hw_eccoob_largepage;
752 } else
753 BUG();
754
755 /* disable interrupt and spare enable */
929 tmp = readw(host->regs + NFC_CONFIG1); 756 tmp = readw(host->regs + NFC_CONFIG1);
930 tmp |= NFC_INT_MSK; 757 tmp |= NFC_INT_MSK;
758 tmp &= ~NFC_SP_EN;
931 writew(tmp, host->regs + NFC_CONFIG1); 759 writew(tmp, host->regs + NFC_CONFIG1);
932 760
933 init_waitqueue_head(&host->irq_waitq); 761 init_waitqueue_head(&host->irq_waitq);
934 762
935 host->irq = platform_get_irq(pdev, 0); 763 host->irq = platform_get_irq(pdev, 0);
936 764
937 err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host); 765 err = request_irq(host->irq, mxc_nfc_irq, 0, DRIVER_NAME, host);
938 if (err) 766 if (err)
939 goto eirq; 767 goto eirq;
940 768
769 /* Reset NAND */
770 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
771
772 /* preset operation */
773 /* Unlock the internal RAM Buffer */
774 writew(0x2, host->regs + NFC_CONFIG);
775
776 /* Blocks to be unlocked */
777 if (nfc_is_v21()) {
778 writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
779 writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
780 this->ecc.bytes = 9;
781 } else if (nfc_is_v1()) {
782 writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
783 writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
784 this->ecc.bytes = 3;
785 } else
786 BUG();
787
788 /* Unlock Block Command for given address range */
789 writew(0x4, host->regs + NFC_WRPROT);
790
791 this->ecc.size = 512;
792 this->ecc.layout = oob_smallpage;
793
941 if (pdata->hw_ecc) { 794 if (pdata->hw_ecc) {
942 this->ecc.calculate = mxc_nand_calculate_ecc; 795 this->ecc.calculate = mxc_nand_calculate_ecc;
943 this->ecc.hwctl = mxc_nand_enable_hwecc; 796 this->ecc.hwctl = mxc_nand_enable_hwecc;
944 this->ecc.correct = mxc_nand_correct_data; 797 this->ecc.correct = mxc_nand_correct_data;
945 this->ecc.mode = NAND_ECC_HW; 798 this->ecc.mode = NAND_ECC_HW;
946 this->ecc.size = 512;
947 this->ecc.bytes = 3;
948 tmp = readw(host->regs + NFC_CONFIG1); 799 tmp = readw(host->regs + NFC_CONFIG1);
949 tmp |= NFC_ECC_EN; 800 tmp |= NFC_ECC_EN;
950 writew(tmp, host->regs + NFC_CONFIG1); 801 writew(tmp, host->regs + NFC_CONFIG1);
951 } else { 802 } else {
952 this->ecc.size = 512;
953 this->ecc.bytes = 3;
954 this->ecc.layout = &nand_hw_eccoob_8;
955 this->ecc.mode = NAND_ECC_SOFT; 803 this->ecc.mode = NAND_ECC_SOFT;
956 tmp = readw(host->regs + NFC_CONFIG1); 804 tmp = readw(host->regs + NFC_CONFIG1);
957 tmp &= ~NFC_ECC_EN; 805 tmp &= ~NFC_ECC_EN;
958 writew(tmp, host->regs + NFC_CONFIG1); 806 writew(tmp, host->regs + NFC_CONFIG1);
959 } 807 }
960 808
961 /* Reset NAND */
962 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
963
964 /* preset operation */
965 /* Unlock the internal RAM Buffer */
966 writew(0x2, host->regs + NFC_CONFIG);
967
968 /* Blocks to be unlocked */
969 writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR);
970 writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR);
971
972 /* Unlock Block Command for given address range */
973 writew(0x4, host->regs + NFC_WRPROT);
974
975 /* NAND bus width determines access funtions used by upper layer */ 809 /* NAND bus width determines access funtions used by upper layer */
976 if (pdata->width == 2) { 810 if (pdata->width == 2)
977 this->options |= NAND_BUSWIDTH_16; 811 this->options |= NAND_BUSWIDTH_16;
978 this->ecc.layout = &nand_hw_eccoob_16; 812
813 if (pdata->flash_bbt) {
814 this->bbt_td = &bbt_main_descr;
815 this->bbt_md = &bbt_mirror_descr;
816 /* update flash based bbt */
817 this->options |= NAND_USE_FLASH_BBT;
979 } 818 }
980 819
981 /* first scan to find the device and get the page size */ 820 /* first scan to find the device and get the page size */
@@ -984,38 +823,8 @@ static int __init mxcnd_probe(struct platform_device *pdev)
984 goto escan; 823 goto escan;
985 } 824 }
986 825
987 if (mtd->writesize == 2048) { 826 if (mtd->writesize == 2048)
988 host->pagesize_2k = 1; 827 this->ecc.layout = oob_largepage;
989 this->badblock_pattern = &smallpage_memorybased;
990 }
991
992 if (this->ecc.mode == NAND_ECC_HW) {
993 switch (mtd->oobsize) {
994 case 8:
995 this->ecc.layout = &nand_hw_eccoob_8;
996 break;
997 case 16:
998 this->ecc.layout = &nand_hw_eccoob_16;
999 break;
1000 case 64:
1001 this->ecc.layout = &nand_hw_eccoob_64;
1002 break;
1003 default:
1004 /* page size not handled by HW ECC */
1005 /* switching back to soft ECC */
1006 this->ecc.size = 512;
1007 this->ecc.bytes = 3;
1008 this->ecc.layout = &nand_hw_eccoob_8;
1009 this->ecc.mode = NAND_ECC_SOFT;
1010 this->ecc.calculate = NULL;
1011 this->ecc.correct = NULL;
1012 this->ecc.hwctl = NULL;
1013 tmp = readw(host->regs + NFC_CONFIG1);
1014 tmp &= ~NFC_ECC_EN;
1015 writew(tmp, host->regs + NFC_CONFIG1);
1016 break;
1017 }
1018 }
1019 828
1020 /* second phase scan */ 829 /* second phase scan */
1021 if (nand_scan_tail(mtd)) { 830 if (nand_scan_tail(mtd)) {
@@ -1043,7 +852,7 @@ static int __init mxcnd_probe(struct platform_device *pdev)
1043escan: 852escan:
1044 free_irq(host->irq, host); 853 free_irq(host->irq, host);
1045eirq: 854eirq:
1046 iounmap(host->regs); 855 iounmap(host->base);
1047eres: 856eres:
1048 clk_put(host->clk); 857 clk_put(host->clk);
1049eclk: 858eclk:
@@ -1062,7 +871,7 @@ static int __devexit mxcnd_remove(struct platform_device *pdev)
1062 871
1063 nand_release(&host->mtd); 872 nand_release(&host->mtd);
1064 free_irq(host->irq, host); 873 free_irq(host->irq, host);
1065 iounmap(host->regs); 874 iounmap(host->base);
1066 kfree(host); 875 kfree(host);
1067 876
1068 return 0; 877 return 0;
@@ -1113,7 +922,7 @@ static struct platform_driver mxcnd_driver = {
1113 .driver = { 922 .driver = {
1114 .name = DRIVER_NAME, 923 .name = DRIVER_NAME,
1115 }, 924 },
1116 .remove = __exit_p(mxcnd_remove), 925 .remove = __devexit_p(mxcnd_remove),
1117 .suspend = mxcnd_suspend, 926 .suspend = mxcnd_suspend,
1118 .resume = mxcnd_resume, 927 .resume = mxcnd_resume,
1119}; 928};
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 2957cc70da3d..8f2958fe2148 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -428,6 +428,28 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
428 return nand_isbad_bbt(mtd, ofs, allowbbt); 428 return nand_isbad_bbt(mtd, ofs, allowbbt);
429} 429}
430 430
431/**
432 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
433 * @mtd: MTD device structure
434 * @timeo: Timeout
435 *
436 * Helper function for nand_wait_ready used when needing to wait in interrupt
437 * context.
438 */
439static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
440{
441 struct nand_chip *chip = mtd->priv;
442 int i;
443
444 /* Wait for the device to get ready */
445 for (i = 0; i < timeo; i++) {
446 if (chip->dev_ready(mtd))
447 break;
448 touch_softlockup_watchdog();
449 mdelay(1);
450 }
451}
452
431/* 453/*
432 * Wait for the ready pin, after a command 454 * Wait for the ready pin, after a command
433 * The timeout is catched later. 455 * The timeout is catched later.
@@ -437,6 +459,10 @@ void nand_wait_ready(struct mtd_info *mtd)
437 struct nand_chip *chip = mtd->priv; 459 struct nand_chip *chip = mtd->priv;
438 unsigned long timeo = jiffies + 2; 460 unsigned long timeo = jiffies + 2;
439 461
462 /* 400ms timeout */
463 if (in_interrupt() || oops_in_progress)
464 return panic_nand_wait_ready(mtd, 400);
465
440 led_trigger_event(nand_led_trigger, LED_FULL); 466 led_trigger_event(nand_led_trigger, LED_FULL);
441 /* wait until command is processed or timeout occures */ 467 /* wait until command is processed or timeout occures */
442 do { 468 do {
@@ -672,6 +698,22 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
672} 698}
673 699
674/** 700/**
701 * panic_nand_get_device - [GENERIC] Get chip for selected access
702 * @chip: the nand chip descriptor
703 * @mtd: MTD device structure
704 * @new_state: the state which is requested
705 *
706 * Used when in panic, no locks are taken.
707 */
708static void panic_nand_get_device(struct nand_chip *chip,
709 struct mtd_info *mtd, int new_state)
710{
711 /* Hardware controller shared among independend devices */
712 chip->controller->active = chip;
713 chip->state = new_state;
714}
715
716/**
675 * nand_get_device - [GENERIC] Get chip for selected access 717 * nand_get_device - [GENERIC] Get chip for selected access
676 * @chip: the nand chip descriptor 718 * @chip: the nand chip descriptor
677 * @mtd: MTD device structure 719 * @mtd: MTD device structure
@@ -698,8 +740,14 @@ nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
698 return 0; 740 return 0;
699 } 741 }
700 if (new_state == FL_PM_SUSPENDED) { 742 if (new_state == FL_PM_SUSPENDED) {
701 spin_unlock(lock); 743 if (chip->controller->active->state == FL_PM_SUSPENDED) {
702 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; 744 chip->state = FL_PM_SUSPENDED;
745 spin_unlock(lock);
746 return 0;
747 } else {
748 spin_unlock(lock);
749 return -EAGAIN;
750 }
703 } 751 }
704 set_current_state(TASK_UNINTERRUPTIBLE); 752 set_current_state(TASK_UNINTERRUPTIBLE);
705 add_wait_queue(wq, &wait); 753 add_wait_queue(wq, &wait);
@@ -710,6 +758,32 @@ nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
710} 758}
711 759
712/** 760/**
761 * panic_nand_wait - [GENERIC] wait until the command is done
762 * @mtd: MTD device structure
763 * @chip: NAND chip structure
764 * @timeo: Timeout
765 *
766 * Wait for command done. This is a helper function for nand_wait used when
767 * we are in interrupt context. May happen when in panic and trying to write
768 * an oops trough mtdoops.
769 */
770static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
771 unsigned long timeo)
772{
773 int i;
774 for (i = 0; i < timeo; i++) {
775 if (chip->dev_ready) {
776 if (chip->dev_ready(mtd))
777 break;
778 } else {
779 if (chip->read_byte(mtd) & NAND_STATUS_READY)
780 break;
781 }
782 mdelay(1);
783 }
784}
785
786/**
713 * nand_wait - [DEFAULT] wait until the command is done 787 * nand_wait - [DEFAULT] wait until the command is done
714 * @mtd: MTD device structure 788 * @mtd: MTD device structure
715 * @chip: NAND chip structure 789 * @chip: NAND chip structure
@@ -740,15 +814,19 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
740 else 814 else
741 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); 815 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
742 816
743 while (time_before(jiffies, timeo)) { 817 if (in_interrupt() || oops_in_progress)
744 if (chip->dev_ready) { 818 panic_nand_wait(mtd, chip, timeo);
745 if (chip->dev_ready(mtd)) 819 else {
746 break; 820 while (time_before(jiffies, timeo)) {
747 } else { 821 if (chip->dev_ready) {
748 if (chip->read_byte(mtd) & NAND_STATUS_READY) 822 if (chip->dev_ready(mtd))
749 break; 823 break;
824 } else {
825 if (chip->read_byte(mtd) & NAND_STATUS_READY)
826 break;
827 }
828 cond_resched();
750 } 829 }
751 cond_resched();
752 } 830 }
753 led_trigger_event(nand_led_trigger, LED_OFF); 831 led_trigger_event(nand_led_trigger, LED_OFF);
754 832
@@ -1949,6 +2027,45 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1949} 2027}
1950 2028
1951/** 2029/**
2030 * panic_nand_write - [MTD Interface] NAND write with ECC
2031 * @mtd: MTD device structure
2032 * @to: offset to write to
2033 * @len: number of bytes to write
2034 * @retlen: pointer to variable to store the number of written bytes
2035 * @buf: the data to write
2036 *
2037 * NAND write with ECC. Used when performing writes in interrupt context, this
2038 * may for example be called by mtdoops when writing an oops while in panic.
2039 */
2040static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2041 size_t *retlen, const uint8_t *buf)
2042{
2043 struct nand_chip *chip = mtd->priv;
2044 int ret;
2045
2046 /* Do not allow reads past end of device */
2047 if ((to + len) > mtd->size)
2048 return -EINVAL;
2049 if (!len)
2050 return 0;
2051
2052 /* Wait for the device to get ready. */
2053 panic_nand_wait(mtd, chip, 400);
2054
2055 /* Grab the device. */
2056 panic_nand_get_device(chip, mtd, FL_WRITING);
2057
2058 chip->ops.len = len;
2059 chip->ops.datbuf = (uint8_t *)buf;
2060 chip->ops.oobbuf = NULL;
2061
2062 ret = nand_do_write_ops(mtd, to, &chip->ops);
2063
2064 *retlen = chip->ops.retlen;
2065 return ret;
2066}
2067
2068/**
1952 * nand_write - [MTD Interface] NAND write with ECC 2069 * nand_write - [MTD Interface] NAND write with ECC
1953 * @mtd: MTD device structure 2070 * @mtd: MTD device structure
1954 * @to: offset to write to 2071 * @to: offset to write to
@@ -2645,7 +2762,8 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2645 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id); 2762 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2646 2763
2647 if (IS_ERR(type)) { 2764 if (IS_ERR(type)) {
2648 printk(KERN_WARNING "No NAND device found!!!\n"); 2765 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
2766 printk(KERN_WARNING "No NAND device found.\n");
2649 chip->select_chip(mtd, -1); 2767 chip->select_chip(mtd, -1);
2650 return PTR_ERR(type); 2768 return PTR_ERR(type);
2651 } 2769 }
@@ -2877,6 +2995,7 @@ int nand_scan_tail(struct mtd_info *mtd)
2877 mtd->unpoint = NULL; 2995 mtd->unpoint = NULL;
2878 mtd->read = nand_read; 2996 mtd->read = nand_read;
2879 mtd->write = nand_write; 2997 mtd->write = nand_write;
2998 mtd->panic_write = panic_nand_write;
2880 mtd->read_oob = nand_read_oob; 2999 mtd->read_oob = nand_read_oob;
2881 mtd->write_oob = nand_write_oob; 3000 mtd->write_oob = nand_write_oob;
2882 mtd->sync = nand_sync; 3001 mtd->sync = nand_sync;
diff --git a/drivers/mtd/nand/nand_bcm_umi.c b/drivers/mtd/nand/nand_bcm_umi.c
new file mode 100644
index 000000000000..46a6bc9c4b74
--- /dev/null
+++ b/drivers/mtd/nand/nand_bcm_umi.c
@@ -0,0 +1,149 @@
1/*****************************************************************************
2* Copyright 2004 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/* ---- Include Files ---------------------------------------------------- */
16#include <mach/reg_umi.h>
17#include "nand_bcm_umi.h"
18#ifdef BOOT0_BUILD
19#include <uart.h>
20#endif
21
22/* ---- External Variable Declarations ----------------------------------- */
23/* ---- External Function Prototypes ------------------------------------- */
24/* ---- Public Variables ------------------------------------------------- */
25/* ---- Private Constants and Types -------------------------------------- */
26/* ---- Private Function Prototypes -------------------------------------- */
27/* ---- Private Variables ------------------------------------------------ */
28/* ---- Private Functions ------------------------------------------------ */
29
30#if NAND_ECC_BCH
31/****************************************************************************
32* nand_bch_ecc_flip_bit - Routine to flip an errored bit
33*
34* PURPOSE:
35* This is a helper routine that flips the bit (0 -> 1 or 1 -> 0) of the
36* errored bit specified
37*
38* PARAMETERS:
39* datap - Container that holds the 512 byte data
40* errorLocation - Location of the bit that needs to be flipped
41*
42* RETURNS:
43* None
44****************************************************************************/
45static void nand_bcm_umi_bch_ecc_flip_bit(uint8_t *datap, int errorLocation)
46{
47 int locWithinAByte = (errorLocation & REG_UMI_BCH_ERR_LOC_BYTE) >> 0;
48 int locWithinAWord = (errorLocation & REG_UMI_BCH_ERR_LOC_WORD) >> 3;
49 int locWithinAPage = (errorLocation & REG_UMI_BCH_ERR_LOC_PAGE) >> 5;
50
51 uint8_t errorByte = 0;
52 uint8_t byteMask = 1 << locWithinAByte;
53
54 /* BCH uses big endian, need to change the location
55 * bits to little endian */
56 locWithinAWord = 3 - locWithinAWord;
57
58 errorByte = datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord];
59
60#ifdef BOOT0_BUILD
61 puthexs("\nECC Correct Offset: ",
62 locWithinAPage * sizeof(uint32_t) + locWithinAWord);
63 puthexs(" errorByte:", errorByte);
64 puthex8(" Bit: ", locWithinAByte);
65#endif
66
67 if (errorByte & byteMask) {
68 /* bit needs to be cleared */
69 errorByte &= ~byteMask;
70 } else {
71 /* bit needs to be set */
72 errorByte |= byteMask;
73 }
74
75 /* write back the value with the fixed bit */
76 datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord] = errorByte;
77}
78
79/****************************************************************************
80* nand_correct_page_bch - Routine to correct bit errors when reading NAND
81*
82* PURPOSE:
83* This routine reads the BCH registers to determine if there are any bit
84* errors during the read of the last 512 bytes of data + ECC bytes. If
85* errors exists, the routine fixes it.
86*
87* PARAMETERS:
88* datap - Container that holds the 512 byte data
89*
90* RETURNS:
91* 0 or greater = Number of errors corrected
92* (No errors are found or errors have been fixed)
93* -1 = Error(s) cannot be fixed
94****************************************************************************/
95int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
96 int numEccBytes)
97{
98 int numErrors;
99 int errorLocation;
100 int idx;
101 uint32_t regValue;
102
103 /* wait for read ECC to be valid */
104 regValue = nand_bcm_umi_bch_poll_read_ecc_calc();
105
106 /*
107 * read the control status register to determine if there
108 * are error'ed bits
109 * see if errors are correctible
110 */
111 if ((regValue & REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR) > 0) {
112 int i;
113
114 for (i = 0; i < numEccBytes; i++) {
115 if (readEccData[i] != 0xff) {
116 /* errors cannot be fixed, return -1 */
117 return -1;
118 }
119 }
120 /* If ECC is unprogrammed then we can't correct,
121 * assume everything OK */
122 return 0;
123 }
124
125 if ((regValue & REG_UMI_BCH_CTRL_STATUS_CORR_ERR) == 0) {
126 /* no errors */
127 return 0;
128 }
129
130 /*
131 * Fix errored bits by doing the following:
132 * 1. Read the number of errors in the control and status register
133 * 2. Read the error location registers that corresponds to the number
134 * of errors reported
135 * 3. Invert the bit in the data
136 */
137 numErrors = (regValue & REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR) >> 20;
138
139 for (idx = 0; idx < numErrors; idx++) {
140 errorLocation =
141 REG_UMI_BCH_ERR_LOC_ADDR(idx) & REG_UMI_BCH_ERR_LOC_MASK;
142
143 /* Flip bit */
144 nand_bcm_umi_bch_ecc_flip_bit(datap, errorLocation);
145 }
146 /* Errors corrected */
147 return numErrors;
148}
149#endif
diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h
new file mode 100644
index 000000000000..7cec2cd97854
--- /dev/null
+++ b/drivers/mtd/nand/nand_bcm_umi.h
@@ -0,0 +1,358 @@
1/*****************************************************************************
2* Copyright 2003 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14#ifndef NAND_BCM_UMI_H
15#define NAND_BCM_UMI_H
16
17/* ---- Include Files ---------------------------------------------------- */
18#include <mach/reg_umi.h>
19#include <mach/reg_nand.h>
20#include <cfg_global.h>
21
22/* ---- Constants and Types ---------------------------------------------- */
23#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
24#define NAND_ECC_BCH (CFG_GLOBAL_CHIP_REV > 0xA0)
25#else
26#define NAND_ECC_BCH 0
27#endif
28
29#define CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES 13
30
31#if NAND_ECC_BCH
32#ifdef BOOT0_BUILD
33#define NAND_ECC_NUM_BYTES 13
34#else
35#define NAND_ECC_NUM_BYTES CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES
36#endif
37#else
38#define NAND_ECC_NUM_BYTES 3
39#endif
40
41#define NAND_DATA_ACCESS_SIZE 512
42
43/* ---- Variable Externs ------------------------------------------ */
44/* ---- Function Prototypes --------------------------------------- */
45int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
46 int numEccBytes);
47
48/* Check in device is ready */
49static inline int nand_bcm_umi_dev_ready(void)
50{
51 return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
52}
53
54/* Wait until device is ready */
55static inline void nand_bcm_umi_wait_till_ready(void)
56{
57 while (nand_bcm_umi_dev_ready() == 0)
58 ;
59}
60
61/* Enable Hamming ECC */
62static inline void nand_bcm_umi_hamming_enable_hwecc(void)
63{
64 /* disable and reset ECC, 512 byte page */
65 REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
66 REG_UMI_NAND_ECC_CSR_256BYTE);
67 /* enable ECC */
68 REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
69}
70
71#if NAND_ECC_BCH
72/* BCH ECC specifics */
73#define ECC_BITS_PER_CORRECTABLE_BIT 13
74
75/* Enable BCH Read ECC */
76static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
77{
78 /* disable and reset ECC */
79 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
80 /* Turn on ECC */
81 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
82}
83
84/* Enable BCH Write ECC */
85static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
86{
87 /* disable and reset ECC */
88 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
89 /* Turn on ECC */
90 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
91}
92
93/* Config number of BCH ECC bytes */
94static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
95{
96 uint32_t nValue;
97 uint32_t tValue;
98 uint32_t kValue;
99 uint32_t numBits = numEccBytes * 8;
100
101 /* disable and reset ECC */
102 REG_UMI_BCH_CTRL_STATUS =
103 REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
104 REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
105
106 /* Every correctible bit requires 13 ECC bits */
107 tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
108
109 /* Total data in number of bits for generating and computing BCH ECC */
110 nValue = (NAND_DATA_ACCESS_SIZE + numEccBytes) * 8;
111
112 /* K parameter is used internally. K = N - (T * 13) */
113 kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
114
115 /* Write the settings */
116 REG_UMI_BCH_N = nValue;
117 REG_UMI_BCH_T = tValue;
118 REG_UMI_BCH_K = kValue;
119}
120
121/* Pause during ECC read calculation to skip bytes in OOB */
122static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
123{
124 REG_UMI_BCH_CTRL_STATUS =
125 REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
126 REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
127}
128
129/* Resume during ECC read calculation after skipping bytes in OOB */
130static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
131{
132 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
133}
134
135/* Poll read ECC calc to check when hardware completes */
136static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
137{
138 uint32_t regVal;
139
140 do {
141 /* wait for ECC to be valid */
142 regVal = REG_UMI_BCH_CTRL_STATUS;
143 } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
144
145 return regVal;
146}
147
148/* Poll write ECC calc to check when hardware completes */
149static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
150{
151 /* wait for ECC to be valid */
152 while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
153 == 0)
154 ;
155}
156
157/* Read the OOB and ECC, for kernel write OOB to a buffer */
158#if defined(__KERNEL__) && !defined(STANDALONE)
159static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
160 uint8_t *eccCalc, int numEccBytes, uint8_t *oobp)
161#else
162static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
163 uint8_t *eccCalc, int numEccBytes)
164#endif
165{
166 int eccPos = 0;
167 int numToRead = 16; /* There are 16 bytes per sector in the OOB */
168
169 /* ECC is already paused when this function is called */
170
171 if (pageSize == NAND_DATA_ACCESS_SIZE) {
172 while (numToRead > numEccBytes) {
173 /* skip free oob region */
174#if defined(__KERNEL__) && !defined(STANDALONE)
175 *oobp++ = REG_NAND_DATA8;
176#else
177 REG_NAND_DATA8;
178#endif
179 numToRead--;
180 }
181
182 /* read ECC bytes before BI */
183 nand_bcm_umi_bch_resume_read_ecc_calc();
184
185 while (numToRead > 11) {
186#if defined(__KERNEL__) && !defined(STANDALONE)
187 *oobp = REG_NAND_DATA8;
188 eccCalc[eccPos++] = *oobp;
189 oobp++;
190#else
191 eccCalc[eccPos++] = REG_NAND_DATA8;
192#endif
193 }
194
195 nand_bcm_umi_bch_pause_read_ecc_calc();
196
197 if (numToRead == 11) {
198 /* read BI */
199#if defined(__KERNEL__) && !defined(STANDALONE)
200 *oobp++ = REG_NAND_DATA8;
201#else
202 REG_NAND_DATA8;
203#endif
204 numToRead--;
205 }
206
207 /* read ECC bytes */
208 nand_bcm_umi_bch_resume_read_ecc_calc();
209 while (numToRead) {
210#if defined(__KERNEL__) && !defined(STANDALONE)
211 *oobp = REG_NAND_DATA8;
212 eccCalc[eccPos++] = *oobp;
213 oobp++;
214#else
215 eccCalc[eccPos++] = REG_NAND_DATA8;
216#endif
217 numToRead--;
218 }
219 } else {
220 /* skip BI */
221#if defined(__KERNEL__) && !defined(STANDALONE)
222 *oobp++ = REG_NAND_DATA8;
223#else
224 REG_NAND_DATA8;
225#endif
226 numToRead--;
227
228 while (numToRead > numEccBytes) {
229 /* skip free oob region */
230#if defined(__KERNEL__) && !defined(STANDALONE)
231 *oobp++ = REG_NAND_DATA8;
232#else
233 REG_NAND_DATA8;
234#endif
235 numToRead--;
236 }
237
238 /* read ECC bytes */
239 nand_bcm_umi_bch_resume_read_ecc_calc();
240 while (numToRead) {
241#if defined(__KERNEL__) && !defined(STANDALONE)
242 *oobp = REG_NAND_DATA8;
243 eccCalc[eccPos++] = *oobp;
244 oobp++;
245#else
246 eccCalc[eccPos++] = REG_NAND_DATA8;
247#endif
248 numToRead--;
249 }
250 }
251}
252
253/* Helper function to write ECC */
254static inline void NAND_BCM_UMI_ECC_WRITE(int numEccBytes, int eccBytePos,
255 uint8_t *oobp, uint8_t eccVal)
256{
257 if (eccBytePos <= numEccBytes)
258 *oobp = eccVal;
259}
260
261/* Write OOB with ECC */
262static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
263 uint8_t *oobp, int numEccBytes)
264{
265 uint32_t eccVal = 0xffffffff;
266
267 /* wait for write ECC to be valid */
268 nand_bcm_umi_bch_poll_write_ecc_calc();
269
270 /*
271 ** Get the hardware ecc from the 32-bit result registers.
272 ** Read after 512 byte accesses. Format B3B2B1B0
273 ** where B3 = ecc3, etc.
274 */
275
276 if (pageSize == NAND_DATA_ACCESS_SIZE) {
277 /* Now fill in the ECC bytes */
278 if (numEccBytes >= 13)
279 eccVal = REG_UMI_BCH_WR_ECC_3;
280
281 /* Usually we skip CM in oob[0,1] */
282 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
283 (eccVal >> 16) & 0xff);
284 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[1],
285 (eccVal >> 8) & 0xff);
286
287 /* Write ECC in oob[2,3,4] */
288 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[2],
289 eccVal & 0xff); /* ECC 12 */
290
291 if (numEccBytes >= 9)
292 eccVal = REG_UMI_BCH_WR_ECC_2;
293
294 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
295 (eccVal >> 24) & 0xff); /* ECC11 */
296 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[4],
297 (eccVal >> 16) & 0xff); /* ECC10 */
298
299 /* Always Skip BI in oob[5] */
300 } else {
301 /* Always Skip BI in oob[0] */
302
303 /* Now fill in the ECC bytes */
304 if (numEccBytes >= 13)
305 eccVal = REG_UMI_BCH_WR_ECC_3;
306
307 /* Usually skip CM in oob[1,2] */
308 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
309 (eccVal >> 16) & 0xff);
310 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[2],
311 (eccVal >> 8) & 0xff);
312
313 /* Write ECC in oob[3-15] */
314 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[3],
315 eccVal & 0xff); /* ECC12 */
316
317 if (numEccBytes >= 9)
318 eccVal = REG_UMI_BCH_WR_ECC_2;
319
320 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
321 (eccVal >> 24) & 0xff); /* ECC11 */
322 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[5],
323 (eccVal >> 16) & 0xff); /* ECC10 */
324 }
325
326 /* Fill in the remainder of ECC locations */
327 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 10, &oobp[6],
328 (eccVal >> 8) & 0xff); /* ECC9 */
329 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 9, &oobp[7],
330 eccVal & 0xff); /* ECC8 */
331
332 if (numEccBytes >= 5)
333 eccVal = REG_UMI_BCH_WR_ECC_1;
334
335 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
336 (eccVal >> 24) & 0xff); /* ECC7 */
337 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 7, &oobp[9],
338 (eccVal >> 16) & 0xff); /* ECC6 */
339 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 6, &oobp[10],
340 (eccVal >> 8) & 0xff); /* ECC5 */
341 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 5, &oobp[11],
342 eccVal & 0xff); /* ECC4 */
343
344 if (numEccBytes >= 1)
345 eccVal = REG_UMI_BCH_WR_ECC_0;
346
347 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
348 (eccVal >> 24) & 0xff); /* ECC3 */
349 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 3, &oobp[13],
350 (eccVal >> 16) & 0xff); /* ECC2 */
351 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 2, &oobp[14],
352 (eccVal >> 8) & 0xff); /* ECC1 */
353 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 1, &oobp[15],
354 eccVal & 0xff); /* ECC0 */
355}
356#endif
357
358#endif /* NAND_BCM_UMI_H */
diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c
index 92320a643275..271b8e735e8f 100644
--- a/drivers/mtd/nand/nand_ecc.c
+++ b/drivers/mtd/nand/nand_ecc.c
@@ -150,20 +150,19 @@ static const char addressbits[256] = {
150}; 150};
151 151
152/** 152/**
153 * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256/512-byte 153 * __nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256/512-byte
154 * block 154 * block
155 * @mtd: MTD block structure
156 * @buf: input buffer with raw data 155 * @buf: input buffer with raw data
156 * @eccsize: data bytes per ecc step (256 or 512)
157 * @code: output buffer with ECC 157 * @code: output buffer with ECC
158 */ 158 */
159int nand_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf, 159void __nand_calculate_ecc(const unsigned char *buf, unsigned int eccsize,
160 unsigned char *code) 160 unsigned char *code)
161{ 161{
162 int i; 162 int i;
163 const uint32_t *bp = (uint32_t *)buf; 163 const uint32_t *bp = (uint32_t *)buf;
164 /* 256 or 512 bytes/ecc */ 164 /* 256 or 512 bytes/ecc */
165 const uint32_t eccsize_mult = 165 const uint32_t eccsize_mult = eccsize >> 8;
166 (((struct nand_chip *)mtd->priv)->ecc.size) >> 8;
167 uint32_t cur; /* current value in buffer */ 166 uint32_t cur; /* current value in buffer */
168 /* rp0..rp15..rp17 are the various accumulated parities (per byte) */ 167 /* rp0..rp15..rp17 are the various accumulated parities (per byte) */
169 uint32_t rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7; 168 uint32_t rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7;
@@ -412,6 +411,22 @@ int nand_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf,
412 (invparity[par & 0x55] << 2) | 411 (invparity[par & 0x55] << 2) |
413 (invparity[rp17] << 1) | 412 (invparity[rp17] << 1) |
414 (invparity[rp16] << 0); 413 (invparity[rp16] << 0);
414}
415EXPORT_SYMBOL(__nand_calculate_ecc);
416
417/**
418 * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256/512-byte
419 * block
420 * @mtd: MTD block structure
421 * @buf: input buffer with raw data
422 * @code: output buffer with ECC
423 */
424int nand_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf,
425 unsigned char *code)
426{
427 __nand_calculate_ecc(buf,
428 ((struct nand_chip *)mtd->priv)->ecc.size, code);
429
415 return 0; 430 return 0;
416} 431}
417EXPORT_SYMBOL(nand_calculate_ecc); 432EXPORT_SYMBOL(nand_calculate_ecc);
diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c
index cd0711b83ac4..7281000fef2d 100644
--- a/drivers/mtd/nand/nandsim.c
+++ b/drivers/mtd/nand/nandsim.c
@@ -161,7 +161,7 @@ MODULE_PARM_DESC(overridesize, "Specifies the NAND Flash size overriding the I
161MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory"); 161MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory");
162 162
163/* The largest possible page size */ 163/* The largest possible page size */
164#define NS_LARGEST_PAGE_SIZE 2048 164#define NS_LARGEST_PAGE_SIZE 4096
165 165
166/* The prefix for simulator output */ 166/* The prefix for simulator output */
167#define NS_OUTPUT_PREFIX "[nandsim]" 167#define NS_OUTPUT_PREFIX "[nandsim]"
@@ -259,7 +259,8 @@ MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of mem
259#define OPT_SMARTMEDIA 0x00000010 /* SmartMedia technology chips */ 259#define OPT_SMARTMEDIA 0x00000010 /* SmartMedia technology chips */
260#define OPT_AUTOINCR 0x00000020 /* page number auto inctimentation is possible */ 260#define OPT_AUTOINCR 0x00000020 /* page number auto inctimentation is possible */
261#define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */ 261#define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */
262#define OPT_LARGEPAGE (OPT_PAGE2048) /* 2048-byte page chips */ 262#define OPT_PAGE4096 0x00000080 /* 4096-byte page chips */
263#define OPT_LARGEPAGE (OPT_PAGE2048 | OPT_PAGE4096) /* 2048 & 4096-byte page chips */
263#define OPT_SMALLPAGE (OPT_PAGE256 | OPT_PAGE512) /* 256 and 512-byte page chips */ 264#define OPT_SMALLPAGE (OPT_PAGE256 | OPT_PAGE512) /* 256 and 512-byte page chips */
264 265
265/* Remove action bits ftom state */ 266/* Remove action bits ftom state */
@@ -588,6 +589,8 @@ static int init_nandsim(struct mtd_info *mtd)
588 ns->options |= OPT_PAGE512_8BIT; 589 ns->options |= OPT_PAGE512_8BIT;
589 } else if (ns->geom.pgsz == 2048) { 590 } else if (ns->geom.pgsz == 2048) {
590 ns->options |= OPT_PAGE2048; 591 ns->options |= OPT_PAGE2048;
592 } else if (ns->geom.pgsz == 4096) {
593 ns->options |= OPT_PAGE4096;
591 } else { 594 } else {
592 NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz); 595 NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz);
593 return -EIO; 596 return -EIO;
diff --git a/drivers/mtd/nand/plat_nand.c b/drivers/mtd/nand/plat_nand.c
index 4e16c6f5bdd5..8d467315f02b 100644
--- a/drivers/mtd/nand/plat_nand.c
+++ b/drivers/mtd/nand/plat_nand.c
@@ -34,7 +34,12 @@ static int __devinit plat_nand_probe(struct platform_device *pdev)
34{ 34{
35 struct platform_nand_data *pdata = pdev->dev.platform_data; 35 struct platform_nand_data *pdata = pdev->dev.platform_data;
36 struct plat_nand_data *data; 36 struct plat_nand_data *data;
37 int res = 0; 37 struct resource *res;
38 int err = 0;
39
40 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
41 if (!res)
42 return -ENXIO;
38 43
39 /* Allocate memory for the device structure (and zero it) */ 44 /* Allocate memory for the device structure (and zero it) */
40 data = kzalloc(sizeof(struct plat_nand_data), GFP_KERNEL); 45 data = kzalloc(sizeof(struct plat_nand_data), GFP_KERNEL);
@@ -43,12 +48,18 @@ static int __devinit plat_nand_probe(struct platform_device *pdev)
43 return -ENOMEM; 48 return -ENOMEM;
44 } 49 }
45 50
46 data->io_base = ioremap(pdev->resource[0].start, 51 if (!request_mem_region(res->start, resource_size(res),
47 pdev->resource[0].end - pdev->resource[0].start + 1); 52 dev_name(&pdev->dev))) {
53 dev_err(&pdev->dev, "request_mem_region failed\n");
54 err = -EBUSY;
55 goto out_free;
56 }
57
58 data->io_base = ioremap(res->start, resource_size(res));
48 if (data->io_base == NULL) { 59 if (data->io_base == NULL) {
49 dev_err(&pdev->dev, "ioremap failed\n"); 60 dev_err(&pdev->dev, "ioremap failed\n");
50 kfree(data); 61 err = -EIO;
51 return -EIO; 62 goto out_release_io;
52 } 63 }
53 64
54 data->chip.priv = &data; 65 data->chip.priv = &data;
@@ -74,24 +85,24 @@ static int __devinit plat_nand_probe(struct platform_device *pdev)
74 85
75 /* Handle any platform specific setup */ 86 /* Handle any platform specific setup */
76 if (pdata->ctrl.probe) { 87 if (pdata->ctrl.probe) {
77 res = pdata->ctrl.probe(pdev); 88 err = pdata->ctrl.probe(pdev);
78 if (res) 89 if (err)
79 goto out; 90 goto out;
80 } 91 }
81 92
82 /* Scan to find existance of the device */ 93 /* Scan to find existance of the device */
83 if (nand_scan(&data->mtd, 1)) { 94 if (nand_scan(&data->mtd, 1)) {
84 res = -ENXIO; 95 err = -ENXIO;
85 goto out; 96 goto out;
86 } 97 }
87 98
88#ifdef CONFIG_MTD_PARTITIONS 99#ifdef CONFIG_MTD_PARTITIONS
89 if (pdata->chip.part_probe_types) { 100 if (pdata->chip.part_probe_types) {
90 res = parse_mtd_partitions(&data->mtd, 101 err = parse_mtd_partitions(&data->mtd,
91 pdata->chip.part_probe_types, 102 pdata->chip.part_probe_types,
92 &data->parts, 0); 103 &data->parts, 0);
93 if (res > 0) { 104 if (err > 0) {
94 add_mtd_partitions(&data->mtd, data->parts, res); 105 add_mtd_partitions(&data->mtd, data->parts, err);
95 return 0; 106 return 0;
96 } 107 }
97 } 108 }
@@ -99,14 +110,14 @@ static int __devinit plat_nand_probe(struct platform_device *pdev)
99 pdata->chip.set_parts(data->mtd.size, &pdata->chip); 110 pdata->chip.set_parts(data->mtd.size, &pdata->chip);
100 if (pdata->chip.partitions) { 111 if (pdata->chip.partitions) {
101 data->parts = pdata->chip.partitions; 112 data->parts = pdata->chip.partitions;
102 res = add_mtd_partitions(&data->mtd, data->parts, 113 err = add_mtd_partitions(&data->mtd, data->parts,
103 pdata->chip.nr_partitions); 114 pdata->chip.nr_partitions);
104 } else 115 } else
105#endif 116#endif
106 res = add_mtd_device(&data->mtd); 117 err = add_mtd_device(&data->mtd);
107 118
108 if (!res) 119 if (!err)
109 return res; 120 return err;
110 121
111 nand_release(&data->mtd); 122 nand_release(&data->mtd);
112out: 123out:
@@ -114,8 +125,11 @@ out:
114 pdata->ctrl.remove(pdev); 125 pdata->ctrl.remove(pdev);
115 platform_set_drvdata(pdev, NULL); 126 platform_set_drvdata(pdev, NULL);
116 iounmap(data->io_base); 127 iounmap(data->io_base);
128out_release_io:
129 release_mem_region(res->start, resource_size(res));
130out_free:
117 kfree(data); 131 kfree(data);
118 return res; 132 return err;
119} 133}
120 134
121/* 135/*
@@ -125,6 +139,9 @@ static int __devexit plat_nand_remove(struct platform_device *pdev)
125{ 139{
126 struct plat_nand_data *data = platform_get_drvdata(pdev); 140 struct plat_nand_data *data = platform_get_drvdata(pdev);
127 struct platform_nand_data *pdata = pdev->dev.platform_data; 141 struct platform_nand_data *pdata = pdev->dev.platform_data;
142 struct resource *res;
143
144 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
128 145
129 nand_release(&data->mtd); 146 nand_release(&data->mtd);
130#ifdef CONFIG_MTD_PARTITIONS 147#ifdef CONFIG_MTD_PARTITIONS
@@ -134,6 +151,7 @@ static int __devexit plat_nand_remove(struct platform_device *pdev)
134 if (pdata->ctrl.remove) 151 if (pdata->ctrl.remove)
135 pdata->ctrl.remove(pdev); 152 pdata->ctrl.remove(pdev);
136 iounmap(data->io_base); 153 iounmap(data->io_base);
154 release_mem_region(res->start, resource_size(res));
137 kfree(data); 155 kfree(data);
138 156
139 return 0; 157 return 0;
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
index 68b5b3a486a9..fa6e9c7fe511 100644
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -774,7 +774,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
774 chip->select_chip = s3c2410_nand_select_chip; 774 chip->select_chip = s3c2410_nand_select_chip;
775 chip->chip_delay = 50; 775 chip->chip_delay = 50;
776 chip->priv = nmtd; 776 chip->priv = nmtd;
777 chip->options = 0; 777 chip->options = set->options;
778 chip->controller = &info->controller; 778 chip->controller = &info->controller;
779 779
780 switch (info->cpu_type) { 780 switch (info->cpu_type) {
diff --git a/drivers/mtd/nand/txx9ndfmc.c b/drivers/mtd/nand/txx9ndfmc.c
index 73af8324d0d0..863513c3b69a 100644
--- a/drivers/mtd/nand/txx9ndfmc.c
+++ b/drivers/mtd/nand/txx9ndfmc.c
@@ -429,11 +429,10 @@ static int __exit txx9ndfmc_remove(struct platform_device *dev)
429 chip = mtd->priv; 429 chip = mtd->priv;
430 txx9_priv = chip->priv; 430 txx9_priv = chip->priv;
431 431
432 nand_release(mtd);
432#ifdef CONFIG_MTD_PARTITIONS 433#ifdef CONFIG_MTD_PARTITIONS
433 del_mtd_partitions(mtd);
434 kfree(drvdata->parts[i]); 434 kfree(drvdata->parts[i]);
435#endif 435#endif
436 del_mtd_device(mtd);
437 kfree(txx9_priv->mtdname); 436 kfree(txx9_priv->mtdname);
438 kfree(txx9_priv); 437 kfree(txx9_priv);
439 } 438 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 12:50:30 -0500