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authorKaiGai Kohei <kaigai@ak.jp.nec.com>2006-05-18 11:43:53 -0400
committerKaiGai Kohei <kaigai@ak.jp.nec.com>2006-05-18 11:43:53 -0400
commit20a92fc74c5c91c7bc5693d51acc2b99aceb0465 (patch)
tree41bf535f38ff1a29c560bcf622e9b4ef03c2c106 /drivers/mtd/nand/spia.c
parent21b9879bf2817aca343cdda11ade6a87f5373e74 (diff)
parentf6a673b3f4f93c1c50e1b18f29254b0531b722a8 (diff)
Merge git://git.infradead.org/mtd-2.6
Diffstat (limited to 'drivers/mtd/nand/spia.c')
-rw-r--r--drivers/mtd/nand/spia.c78
1 files changed, 38 insertions, 40 deletions
diff --git a/drivers/mtd/nand/spia.c b/drivers/mtd/nand/spia.c
index 9cf1ce718ec1..9737f1d67c3c 100644
--- a/drivers/mtd/nand/spia.c
+++ b/drivers/mtd/nand/spia.c
@@ -39,16 +39,16 @@ static struct mtd_info *spia_mtd = NULL;
39 */ 39 */
40#define SPIA_IO_BASE 0xd0000000 /* Start of EP7212 IO address space */ 40#define SPIA_IO_BASE 0xd0000000 /* Start of EP7212 IO address space */
41#define SPIA_FIO_BASE 0xf0000000 /* Address where flash is mapped */ 41#define SPIA_FIO_BASE 0xf0000000 /* Address where flash is mapped */
42#define SPIA_PEDR 0x0080 /* 42#define SPIA_PEDR 0x0080 /*
43 * IO offset to Port E data register 43 * IO offset to Port E data register
44 * where the CLE, ALE and NCE pins 44 * where the CLE, ALE and NCE pins
45 * are wired to. 45 * are wired to.
46 */ 46 */
47#define SPIA_PEDDR 0x00c0 /* 47#define SPIA_PEDDR 0x00c0 /*
48 * IO offset to Port E data direction 48 * IO offset to Port E data direction
49 * register so we can control the IO 49 * register so we can control the IO
50 * lines. 50 * lines.
51 */ 51 */
52 52
53/* 53/*
54 * Module stuff 54 * Module stuff
@@ -69,25 +69,23 @@ module_param(spia_peddr, int, 0);
69 */ 69 */
70static const struct mtd_partition partition_info[] = { 70static const struct mtd_partition partition_info[] = {
71 { 71 {
72 .name = "SPIA flash partition 1", 72 .name = "SPIA flash partition 1",
73 .offset = 0, 73 .offset = 0,
74 .size = 2*1024*1024 74 .size = 2 * 1024 * 1024},
75 },
76 { 75 {
77 .name = "SPIA flash partition 2", 76 .name = "SPIA flash partition 2",
78 .offset = 2*1024*1024, 77 .offset = 2 * 1024 * 1024,
79 .size = 6*1024*1024 78 .size = 6 * 1024 * 1024}
80 }
81}; 79};
82#define NUM_PARTITIONS 2
83 80
81#define NUM_PARTITIONS 2
84 82
85/* 83/*
86 * hardware specific access to control-lines 84 * hardware specific access to control-lines
87*/ 85*/
88static void spia_hwcontrol(struct mtd_info *mtd, int cmd){ 86static void spia_hwcontrol(struct mtd_info *mtd, int cmd)
89 87{
90 switch(cmd){ 88 switch (cmd) {
91 89
92 case NAND_CTL_SETCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x01; break; 90 case NAND_CTL_SETCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x01; break;
93 case NAND_CTL_CLRCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x01; break; 91 case NAND_CTL_CLRCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x01; break;
@@ -97,51 +95,51 @@ static void spia_hwcontrol(struct mtd_info *mtd, int cmd){
97 95
98 case NAND_CTL_SETNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x04; break; 96 case NAND_CTL_SETNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x04; break;
99 case NAND_CTL_CLRNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x04; break; 97 case NAND_CTL_CLRNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x04; break;
100 } 98 }
101} 99}
102 100
103/* 101/*
104 * Main initialization routine 102 * Main initialization routine
105 */ 103 */
106int __init spia_init (void) 104static int __init spia_init(void)
107{ 105{
108 struct nand_chip *this; 106 struct nand_chip *this;
109 107
110 /* Allocate memory for MTD device structure and private data */ 108 /* Allocate memory for MTD device structure and private data */
111 spia_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip), 109 spia_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
112 GFP_KERNEL);
113 if (!spia_mtd) { 110 if (!spia_mtd) {
114 printk ("Unable to allocate SPIA NAND MTD device structure.\n"); 111 printk("Unable to allocate SPIA NAND MTD device structure.\n");
115 return -ENOMEM; 112 return -ENOMEM;
116 } 113 }
117 114
118 /* Get pointer to private data */ 115 /* Get pointer to private data */
119 this = (struct nand_chip *) (&spia_mtd[1]); 116 this = (struct nand_chip *)(&spia_mtd[1]);
120 117
121 /* Initialize structures */ 118 /* Initialize structures */
122 memset((char *) spia_mtd, 0, sizeof(struct mtd_info)); 119 memset(spia_mtd, 0, sizeof(struct mtd_info));
123 memset((char *) this, 0, sizeof(struct nand_chip)); 120 memset(this, 0, sizeof(struct nand_chip));
124 121
125 /* Link the private data with the MTD structure */ 122 /* Link the private data with the MTD structure */
126 spia_mtd->priv = this; 123 spia_mtd->priv = this;
124 spia_mtd->owner = THIS_MODULE;
127 125
128 /* 126 /*
129 * Set GPIO Port E control register so that the pins are configured 127 * Set GPIO Port E control register so that the pins are configured
130 * to be outputs for controlling the NAND flash. 128 * to be outputs for controlling the NAND flash.
131 */ 129 */
132 (*(volatile unsigned char *) (spia_io_base + spia_peddr)) = 0x07; 130 (*(volatile unsigned char *)(spia_io_base + spia_peddr)) = 0x07;
133 131
134 /* Set address of NAND IO lines */ 132 /* Set address of NAND IO lines */
135 this->IO_ADDR_R = (void __iomem *) spia_fio_base; 133 this->IO_ADDR_R = (void __iomem *)spia_fio_base;
136 this->IO_ADDR_W = (void __iomem *) spia_fio_base; 134 this->IO_ADDR_W = (void __iomem *)spia_fio_base;
137 /* Set address of hardware control function */ 135 /* Set address of hardware control function */
138 this->hwcontrol = spia_hwcontrol; 136 this->hwcontrol = spia_hwcontrol;
139 /* 15 us command delay time */ 137 /* 15 us command delay time */
140 this->chip_delay = 15; 138 this->chip_delay = 15;
141 139
142 /* Scan to find existence of the device */ 140 /* Scan to find existence of the device */
143 if (nand_scan (spia_mtd, 1)) { 141 if (nand_scan(spia_mtd, 1)) {
144 kfree (spia_mtd); 142 kfree(spia_mtd);
145 return -ENXIO; 143 return -ENXIO;
146 } 144 }
147 145
@@ -151,22 +149,22 @@ int __init spia_init (void)
151 /* Return happy */ 149 /* Return happy */
152 return 0; 150 return 0;
153} 151}
152
154module_init(spia_init); 153module_init(spia_init);
155 154
156/* 155/*
157 * Clean up routine 156 * Clean up routine
158 */ 157 */
159#ifdef MODULE 158static void __exit spia_cleanup(void)
160static void __exit spia_cleanup (void)
161{ 159{
162 /* Release resources, unregister device */ 160 /* Release resources, unregister device */
163 nand_release (spia_mtd); 161 nand_release(spia_mtd);
164 162
165 /* Free the MTD device structure */ 163 /* Free the MTD device structure */
166 kfree (spia_mtd); 164 kfree(spia_mtd);
167} 165}
166
168module_exit(spia_cleanup); 167module_exit(spia_cleanup);
169#endif
170 168
171MODULE_LICENSE("GPL"); 169MODULE_LICENSE("GPL");
172MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com"); 170MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com");