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authorThomas Gleixner <tglx@cruncher.tec.linutronix.de>2006-05-23 17:25:53 -0400
committerThomas Gleixner <tglx@cruncher.tec.linutronix.de>2006-05-23 17:25:53 -0400
commit7abd3ef9875eb2afcdcd4f450680298a2983a55e (patch)
tree64c19d2e5ecca182938acfcb8a172efb7d907d85 /drivers/mtd/nand/spia.c
parent3821720d51b5f304d2c33021a82c8da70f6d6ac9 (diff)
[MTD] Refactor NAND hwcontrol to cmd_ctrl
The hwcontrol function enforced a step by step state machine for any kind of hardware chip access. Let the hardware driver know which control bits are set and inform it about a change of the control lines. Let the hardware driver write out the command and address bytes directly. This gives a peformance advantage for address bus controlled chips and simplifies the quirks in the hardware drivers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/mtd/nand/spia.c')
-rw-r--r--drivers/mtd/nand/spia.c27
1 files changed, 17 insertions, 10 deletions
diff --git a/drivers/mtd/nand/spia.c b/drivers/mtd/nand/spia.c
index 9737f1d67c3c..1f6d429b1583 100644
--- a/drivers/mtd/nand/spia.c
+++ b/drivers/mtd/nand/spia.c
@@ -82,20 +82,27 @@ static const struct mtd_partition partition_info[] = {
82 82
83/* 83/*
84 * hardware specific access to control-lines 84 * hardware specific access to control-lines
85*/ 85 *
86 * ctrl:
87 * NAND_CNE: bit 0 -> bit 2
88 * NAND_CLE: bit 1 -> bit 0
89 * NAND_ALE: bit 2 -> bit 1
90 */
86static void spia_hwcontrol(struct mtd_info *mtd, int cmd) 91static void spia_hwcontrol(struct mtd_info *mtd, int cmd)
87{ 92{
88 switch (cmd) { 93 struct nand_chip *chip = mtd->priv;
89 94
90 case NAND_CTL_SETCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x01; break; 95 if (ctrl & NAND_CTRL_CHANGE) {
91 case NAND_CTL_CLRCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x01; break; 96 void __iomem *addr = spia_io_base + spia_pedr;
97 unsigned char bits;
92 98
93 case NAND_CTL_SETALE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x02; break; 99 bits = (ctrl & NAND_CNE) << 2;
94 case NAND_CTL_CLRALE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x02; break; 100 bits |= (ctrl & NAND_CLE | NAND_ALE) >> 1;
95 101 writeb((readb(addr) & ~0x7) | bits, addr);
96 case NAND_CTL_SETNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x04; break;
97 case NAND_CTL_CLRNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x04; break;
98 } 102 }
103
104 if (cmd != NAND_CMD_NONE)
105 writeb(cmd, chip->IO_ADDR_W);
99} 106}
100 107
101/* 108/*
@@ -133,7 +140,7 @@ static int __init spia_init(void)
133 this->IO_ADDR_R = (void __iomem *)spia_fio_base; 140 this->IO_ADDR_R = (void __iomem *)spia_fio_base;
134 this->IO_ADDR_W = (void __iomem *)spia_fio_base; 141 this->IO_ADDR_W = (void __iomem *)spia_fio_base;
135 /* Set address of hardware control function */ 142 /* Set address of hardware control function */
136 this->hwcontrol = spia_hwcontrol; 143 this->cmd_ctrl = spia_hwcontrol;
137 /* 15 us command delay time */ 144 /* 15 us command delay time */
138 this->chip_delay = 15; 145 this->chip_delay = 15;
139 146