diff options
author | David Woodhouse <dwmw2@infradead.org> | 2006-05-13 13:07:53 -0400 |
---|---|---|
committer | David Woodhouse <dwmw2@infradead.org> | 2006-05-13 13:07:53 -0400 |
commit | e0c7d7675331140e5186d2d1a0efce1d3877d379 (patch) | |
tree | 45247eb5029382c64392aa641e8b0e5506ed152f /drivers/mtd/nand/spia.c | |
parent | 6943f8af7d6583be57d67bba8b2644371f6a10ca (diff) |
[MTD NAND] Indent all of drivers/mtd/nand/*.c.
It was just too painful to deal with.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Diffstat (limited to 'drivers/mtd/nand/spia.c')
-rw-r--r-- | drivers/mtd/nand/spia.c | 75 |
1 files changed, 37 insertions, 38 deletions
diff --git a/drivers/mtd/nand/spia.c b/drivers/mtd/nand/spia.c index 9cf1ce718ec1..a11354b9afa2 100644 --- a/drivers/mtd/nand/spia.c +++ b/drivers/mtd/nand/spia.c | |||
@@ -39,16 +39,16 @@ static struct mtd_info *spia_mtd = NULL; | |||
39 | */ | 39 | */ |
40 | #define SPIA_IO_BASE 0xd0000000 /* Start of EP7212 IO address space */ | 40 | #define SPIA_IO_BASE 0xd0000000 /* Start of EP7212 IO address space */ |
41 | #define SPIA_FIO_BASE 0xf0000000 /* Address where flash is mapped */ | 41 | #define SPIA_FIO_BASE 0xf0000000 /* Address where flash is mapped */ |
42 | #define SPIA_PEDR 0x0080 /* | 42 | #define SPIA_PEDR 0x0080 /* |
43 | * IO offset to Port E data register | 43 | * IO offset to Port E data register |
44 | * where the CLE, ALE and NCE pins | 44 | * where the CLE, ALE and NCE pins |
45 | * are wired to. | 45 | * are wired to. |
46 | */ | 46 | */ |
47 | #define SPIA_PEDDR 0x00c0 /* | 47 | #define SPIA_PEDDR 0x00c0 /* |
48 | * IO offset to Port E data direction | 48 | * IO offset to Port E data direction |
49 | * register so we can control the IO | 49 | * register so we can control the IO |
50 | * lines. | 50 | * lines. |
51 | */ | 51 | */ |
52 | 52 | ||
53 | /* | 53 | /* |
54 | * Module stuff | 54 | * Module stuff |
@@ -69,25 +69,23 @@ module_param(spia_peddr, int, 0); | |||
69 | */ | 69 | */ |
70 | static const struct mtd_partition partition_info[] = { | 70 | static const struct mtd_partition partition_info[] = { |
71 | { | 71 | { |
72 | .name = "SPIA flash partition 1", | 72 | .name = "SPIA flash partition 1", |
73 | .offset = 0, | 73 | .offset = 0, |
74 | .size = 2*1024*1024 | 74 | .size = 2 * 1024 * 1024}, |
75 | }, | ||
76 | { | 75 | { |
77 | .name = "SPIA flash partition 2", | 76 | .name = "SPIA flash partition 2", |
78 | .offset = 2*1024*1024, | 77 | .offset = 2 * 1024 * 1024, |
79 | .size = 6*1024*1024 | 78 | .size = 6 * 1024 * 1024} |
80 | } | ||
81 | }; | 79 | }; |
82 | #define NUM_PARTITIONS 2 | ||
83 | 80 | ||
81 | #define NUM_PARTITIONS 2 | ||
84 | 82 | ||
85 | /* | 83 | /* |
86 | * hardware specific access to control-lines | 84 | * hardware specific access to control-lines |
87 | */ | 85 | */ |
88 | static void spia_hwcontrol(struct mtd_info *mtd, int cmd){ | 86 | static void spia_hwcontrol(struct mtd_info *mtd, int cmd) |
89 | 87 | { | |
90 | switch(cmd){ | 88 | switch (cmd) { |
91 | 89 | ||
92 | case NAND_CTL_SETCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x01; break; | 90 | case NAND_CTL_SETCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x01; break; |
93 | case NAND_CTL_CLRCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x01; break; | 91 | case NAND_CTL_CLRCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x01; break; |
@@ -97,30 +95,29 @@ static void spia_hwcontrol(struct mtd_info *mtd, int cmd){ | |||
97 | 95 | ||
98 | case NAND_CTL_SETNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x04; break; | 96 | case NAND_CTL_SETNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x04; break; |
99 | case NAND_CTL_CLRNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x04; break; | 97 | case NAND_CTL_CLRNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x04; break; |
100 | } | 98 | } |
101 | } | 99 | } |
102 | 100 | ||
103 | /* | 101 | /* |
104 | * Main initialization routine | 102 | * Main initialization routine |
105 | */ | 103 | */ |
106 | int __init spia_init (void) | 104 | int __init spia_init(void) |
107 | { | 105 | { |
108 | struct nand_chip *this; | 106 | struct nand_chip *this; |
109 | 107 | ||
110 | /* Allocate memory for MTD device structure and private data */ | 108 | /* Allocate memory for MTD device structure and private data */ |
111 | spia_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip), | 109 | spia_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); |
112 | GFP_KERNEL); | ||
113 | if (!spia_mtd) { | 110 | if (!spia_mtd) { |
114 | printk ("Unable to allocate SPIA NAND MTD device structure.\n"); | 111 | printk("Unable to allocate SPIA NAND MTD device structure.\n"); |
115 | return -ENOMEM; | 112 | return -ENOMEM; |
116 | } | 113 | } |
117 | 114 | ||
118 | /* Get pointer to private data */ | 115 | /* Get pointer to private data */ |
119 | this = (struct nand_chip *) (&spia_mtd[1]); | 116 | this = (struct nand_chip *)(&spia_mtd[1]); |
120 | 117 | ||
121 | /* Initialize structures */ | 118 | /* Initialize structures */ |
122 | memset((char *) spia_mtd, 0, sizeof(struct mtd_info)); | 119 | memset(spia_mtd, 0, sizeof(struct mtd_info)); |
123 | memset((char *) this, 0, sizeof(struct nand_chip)); | 120 | memset(this, 0, sizeof(struct nand_chip)); |
124 | 121 | ||
125 | /* Link the private data with the MTD structure */ | 122 | /* Link the private data with the MTD structure */ |
126 | spia_mtd->priv = this; | 123 | spia_mtd->priv = this; |
@@ -129,19 +126,19 @@ int __init spia_init (void) | |||
129 | * Set GPIO Port E control register so that the pins are configured | 126 | * Set GPIO Port E control register so that the pins are configured |
130 | * to be outputs for controlling the NAND flash. | 127 | * to be outputs for controlling the NAND flash. |
131 | */ | 128 | */ |
132 | (*(volatile unsigned char *) (spia_io_base + spia_peddr)) = 0x07; | 129 | (*(volatile unsigned char *)(spia_io_base + spia_peddr)) = 0x07; |
133 | 130 | ||
134 | /* Set address of NAND IO lines */ | 131 | /* Set address of NAND IO lines */ |
135 | this->IO_ADDR_R = (void __iomem *) spia_fio_base; | 132 | this->IO_ADDR_R = (void __iomem *)spia_fio_base; |
136 | this->IO_ADDR_W = (void __iomem *) spia_fio_base; | 133 | this->IO_ADDR_W = (void __iomem *)spia_fio_base; |
137 | /* Set address of hardware control function */ | 134 | /* Set address of hardware control function */ |
138 | this->hwcontrol = spia_hwcontrol; | 135 | this->hwcontrol = spia_hwcontrol; |
139 | /* 15 us command delay time */ | 136 | /* 15 us command delay time */ |
140 | this->chip_delay = 15; | 137 | this->chip_delay = 15; |
141 | 138 | ||
142 | /* Scan to find existence of the device */ | 139 | /* Scan to find existence of the device */ |
143 | if (nand_scan (spia_mtd, 1)) { | 140 | if (nand_scan(spia_mtd, 1)) { |
144 | kfree (spia_mtd); | 141 | kfree(spia_mtd); |
145 | return -ENXIO; | 142 | return -ENXIO; |
146 | } | 143 | } |
147 | 144 | ||
@@ -151,20 +148,22 @@ int __init spia_init (void) | |||
151 | /* Return happy */ | 148 | /* Return happy */ |
152 | return 0; | 149 | return 0; |
153 | } | 150 | } |
151 | |||
154 | module_init(spia_init); | 152 | module_init(spia_init); |
155 | 153 | ||
156 | /* | 154 | /* |
157 | * Clean up routine | 155 | * Clean up routine |
158 | */ | 156 | */ |
159 | #ifdef MODULE | 157 | #ifdef MODULE |
160 | static void __exit spia_cleanup (void) | 158 | static void __exit spia_cleanup(void) |
161 | { | 159 | { |
162 | /* Release resources, unregister device */ | 160 | /* Release resources, unregister device */ |
163 | nand_release (spia_mtd); | 161 | nand_release(spia_mtd); |
164 | 162 | ||
165 | /* Free the MTD device structure */ | 163 | /* Free the MTD device structure */ |
166 | kfree (spia_mtd); | 164 | kfree(spia_mtd); |
167 | } | 165 | } |
166 | |||
168 | module_exit(spia_cleanup); | 167 | module_exit(spia_cleanup); |
169 | #endif | 168 | #endif |
170 | 169 | ||