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authorThomas Gleixner <tglx@cruncher.tec.linutronix.de>2006-05-23 17:25:53 -0400
committerThomas Gleixner <tglx@cruncher.tec.linutronix.de>2006-05-23 17:25:53 -0400
commit7abd3ef9875eb2afcdcd4f450680298a2983a55e (patch)
tree64c19d2e5ecca182938acfcb8a172efb7d907d85 /drivers/mtd/nand/s3c2410.c
parent3821720d51b5f304d2c33021a82c8da70f6d6ac9 (diff)
[MTD] Refactor NAND hwcontrol to cmd_ctrl
The hwcontrol function enforced a step by step state machine for any kind of hardware chip access. Let the hardware driver know which control bits are set and inform it about a change of the control lines. Let the hardware driver write out the command and address bytes directly. This gives a peformance advantage for address bus controlled chips and simplifies the quirks in the hardware drivers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/mtd/nand/s3c2410.c')
-rw-r--r--drivers/mtd/nand/s3c2410.c64
1 files changed, 20 insertions, 44 deletions
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
index 608340a25278..215227d1a65c 100644
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -256,60 +256,36 @@ static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
256 * 256 *
257*/ 257*/
258 258
259static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd) 259static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
260 unsigend int ctrl)
260{ 261{
261 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 262 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
262 struct nand_chip *chip = mtd->priv; 263 struct nand_chip *chip = mtd->priv;
263 264
264 switch (cmd) { 265 if (cmd == NAND_CMD_NONE)
265 case NAND_CTL_SETNCE: 266 return;
266 case NAND_CTL_CLRNCE: 267
267 printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__); 268 if (cmd & NAND_CLE)
268 break; 269 writeb(cmd, info->regs + S3C2410_NFCMD);
269 270 else
270 case NAND_CTL_SETCLE: 271 writeb(cmd, info->regs + S3C2410_NFADDR);
271 chip->IO_ADDR_W = info->regs + S3C2410_NFCMD;
272 break;
273
274 case NAND_CTL_SETALE:
275 chip->IO_ADDR_W = info->regs + S3C2410_NFADDR;
276 break;
277
278 /* NAND_CTL_CLRCLE: */
279 /* NAND_CTL_CLRALE: */
280 default:
281 chip->IO_ADDR_W = info->regs + S3C2410_NFDATA;
282 break;
283 }
284} 272}
285 273
286/* command and control functions */ 274/* command and control functions */
287 275
288static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd) 276static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
277 unsigend int ctrl)
289{ 278{
290 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 279 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
291 struct nand_chip *chip = mtd->priv; 280 struct nand_chip *chip = mtd->priv;
292 281
293 switch (cmd) { 282 if (cmd == NAND_CMD_NONE)
294 case NAND_CTL_SETNCE: 283 return;
295 case NAND_CTL_CLRNCE: 284
296 printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__); 285 if (cmd & NAND_CLE)
297 break; 286 writeb(cmd, info->regs + S3C2440_NFCMD);
298 287 else
299 case NAND_CTL_SETCLE: 288 writeb(cmd, info->regs + S3C2440_NFADDR);
300 chip->IO_ADDR_W = info->regs + S3C2440_NFCMD;
301 break;
302
303 case NAND_CTL_SETALE:
304 chip->IO_ADDR_W = info->regs + S3C2440_NFADDR;
305 break;
306
307 /* NAND_CTL_CLRCLE: */
308 /* NAND_CTL_CLRALE: */
309 default:
310 chip->IO_ADDR_W = info->regs + S3C2440_NFDATA;
311 break;
312 }
313} 289}
314 290
315/* s3c2410_nand_devready() 291/* s3c2410_nand_devready()
@@ -498,7 +474,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
498 474
499 chip->IO_ADDR_R = info->regs + S3C2410_NFDATA; 475 chip->IO_ADDR_R = info->regs + S3C2410_NFDATA;
500 chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; 476 chip->IO_ADDR_W = info->regs + S3C2410_NFDATA;
501 chip->hwcontrol = s3c2410_nand_hwcontrol; 477 chip->cmd_ctrl = s3c2410_nand_hwcontrol;
502 chip->dev_ready = s3c2410_nand_devready; 478 chip->dev_ready = s3c2410_nand_devready;
503 chip->write_buf = s3c2410_nand_write_buf; 479 chip->write_buf = s3c2410_nand_write_buf;
504 chip->read_buf = s3c2410_nand_read_buf; 480 chip->read_buf = s3c2410_nand_read_buf;
@@ -511,7 +487,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
511 if (info->is_s3c2440) { 487 if (info->is_s3c2440) {
512 chip->IO_ADDR_R = info->regs + S3C2440_NFDATA; 488 chip->IO_ADDR_R = info->regs + S3C2440_NFDATA;
513 chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; 489 chip->IO_ADDR_W = info->regs + S3C2440_NFDATA;
514 chip->hwcontrol = s3c2440_nand_hwcontrol; 490 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
515 } 491 }
516 492
517 nmtd->info = info; 493 nmtd->info = info;