mtd: pxa3xx_nand: condense the flash definition

Adding a new flash definition would need less code. Keep the platform passing flash definition method. If one flash is both defined in platform data and builtin table, driver would select the one from platform data first. By this way, platform could select the timing most suit for itself, not need to follow the common settings. Signed-off-by: Lei Wen <leiwen@marvell.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Acked-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
author: Lei Wen <leiwen@marvell.com> 2010-08-17 01:50:23 -0400
committer: David Woodhouse <David.Woodhouse@intel.com> 2010-10-24 18:38:47 -0400
commit: c1f82478c535f1de9fecf3cafa82014f312d5d4e (patch)
tree: d3713c7b47f472bfea939305b2a67ec5198f2768 /drivers/mtd/nand/pxa3xx_nand.c
parent: 13ed7aed45e370f30a746e49e674144297a92e16 (diff)
1 files changed, 16 insertions, 156 deletions
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 4d01cda68844..4e40de45f4be 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -176,21 +176,7 @@ MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
 */
 static struct pxa3xx_nand_timing default_timing;
 static struct pxa3xx_nand_flash default_flash;
+static struct pxa3xx_nand_cmdset default_cmdset = {
-static struct pxa3xx_nand_cmdset smallpage_cmdset = {
-        .read1          = 0x0000,
-        .read2          = 0x0050,
-        .program        = 0x1080,
-        .read_status    = 0x0070,
-        .read_id        = 0x0090,
-        .erase          = 0xD060,
-        .reset          = 0x00FF,
-        .lock           = 0x002A,
-        .unlock         = 0x2423,
-        .lock_status    = 0x007A,
-};
-static struct pxa3xx_nand_cmdset largepage_cmdset = {
        .read1          = 0x3000,
        .read2          = 0x0050,
        .program        = 0x1080,
@@ -203,143 +189,23 @@ static struct pxa3xx_nand_cmdset largepage_cmdset = {
        .lock_status    = 0x007A,
 };
-#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
+static struct pxa3xx_nand_timing timing[] = {
-static struct pxa3xx_nand_timing samsung512MbX16_timing = {
+        { 10,  0, 20, 40, 30, 40, 11123, 110, 10, },
-        .tCH    = 10,
+        { 10, 25, 15, 25, 15, 30, 25000,  60, 10, },
-        .tCS    = 0,
+        { 10, 35, 15, 25, 15, 25, 25000,  60, 10, },
-        .tWH    = 20,
-        .tWP    = 40,
-        .tRH    = 30,
-        .tRP    = 40,
-        .tR     = 11123,
-        .tWHR   = 110,
-        .tAR    = 10,
-};
-static struct pxa3xx_nand_flash samsung512MbX16 = {
-        .timing         = &samsung512MbX16_timing,
-        .cmdset         = &smallpage_cmdset,
-        .page_per_block = 32,
-        .page_size      = 512,
-        .flash_width    = 16,
-        .dfc_width      = 16,
-        .num_blocks     = 4096,
-        .chip_id        = 0x46ec,
-};
-static struct pxa3xx_nand_flash samsung2GbX8 = {
-        .timing         = &samsung512MbX16_timing,
-        .cmdset         = &smallpage_cmdset,
-        .page_per_block = 64,
-        .page_size      = 2048,
-        .flash_width    = 8,
-        .dfc_width      = 8,
-        .num_blocks     = 2048,
-        .chip_id        = 0xdaec,
-};
-static struct pxa3xx_nand_flash samsung32GbX8 = {
-        .timing         = &samsung512MbX16_timing,
-        .cmdset         = &smallpage_cmdset,
-        .page_per_block = 128,
-        .page_size      = 4096,
-        .flash_width    = 8,
-        .dfc_width      = 8,
-        .num_blocks     = 8192,
-        .chip_id        = 0xd7ec,
 };
-static struct pxa3xx_nand_timing micron_timing = {
+static struct pxa3xx_nand_flash builtin_flash_types[] = {
-        .tCH    = 10,
+        { 0x46ec,  32,  512, 16, 16, 4096, &default_cmdset, &timing[0] },
-        .tCS    = 25,
+        { 0xdaec,  64, 2048,  8,  8, 2048, &default_cmdset, &timing[0] },
-        .tWH    = 15,
+        { 0xd7ec, 128, 4096,  8,  8, 8192, &default_cmdset, &timing[0] },
-        .tWP    = 25,
+        { 0xa12c,  64, 2048,  8,  8, 1024, &default_cmdset, &timing[1] },
-        .tRH    = 15,
+        { 0xb12c,  64, 2048, 16, 16, 1024, &default_cmdset, &timing[1] },
-        .tRP    = 30,
+        { 0xdc2c,  64, 2048,  8,  8, 4096, &default_cmdset, &timing[1] },
-        .tR     = 25000,
+        { 0xcc2c,  64, 2048, 16, 16, 4096, &default_cmdset, &timing[1] },
-        .tWHR   = 60,
+        { 0xba20,  64, 2048, 16, 16, 2048, &default_cmdset, &timing[2] },
-        .tAR    = 10,
 };
-static struct pxa3xx_nand_flash micron1GbX8 = {
-        .timing         = &micron_timing,
-        .cmdset         = &largepage_cmdset,
-        .page_per_block = 64,
-        .page_size      = 2048,
-        .flash_width    = 8,
-        .dfc_width      = 8,
-        .num_blocks     = 1024,
-        .chip_id        = 0xa12c,
-};
-static struct pxa3xx_nand_flash micron1GbX16 = {
-        .timing         = &micron_timing,
-        .cmdset         = &largepage_cmdset,
-        .page_per_block = 64,
-        .page_size      = 2048,
-        .flash_width    = 16,
-        .dfc_width      = 16,
-        .num_blocks     = 1024,
-        .chip_id        = 0xb12c,
-};
-static struct pxa3xx_nand_flash micron4GbX8 = {
-        .timing         = &micron_timing,
-        .cmdset         = &largepage_cmdset,
-        .page_per_block = 64,
-        .page_size      = 2048,
-        .flash_width    = 8,
-        .dfc_width      = 8,
-        .num_blocks     = 4096,
-        .chip_id        = 0xdc2c,
-};
-static struct pxa3xx_nand_flash micron4GbX16 = {
-        .timing         = &micron_timing,
-        .cmdset         = &largepage_cmdset,
-        .page_per_block = 64,
-        .page_size      = 2048,
-        .flash_width    = 16,
-        .dfc_width      = 16,
-        .num_blocks     = 4096,
-        .chip_id        = 0xcc2c,
-};
-static struct pxa3xx_nand_timing stm2GbX16_timing = {
-        .tCH = 10,
-        .tCS = 35,
-        .tWH = 15,
-        .tWP = 25,
-        .tRH = 15,
-        .tRP = 25,
-        .tR = 25000,
-        .tWHR = 60,
-        .tAR = 10,
-};
-static struct pxa3xx_nand_flash stm2GbX16 = {
-        .timing = &stm2GbX16_timing,
-        .cmdset = &largepage_cmdset,
-        .page_per_block = 64,
-        .page_size = 2048,
-        .flash_width = 16,
-        .dfc_width = 16,
-        .num_blocks = 2048,
-        .chip_id = 0xba20,
-};
-static struct pxa3xx_nand_flash *builtin_flash_types[] = {
-        &samsung512MbX16,
-        &samsung2GbX8,
-        &samsung32GbX8,
-        &micron1GbX8,
-        &micron1GbX16,
-        &micron4GbX8,
-        &micron4GbX16,
-        &stm2GbX16,
-};
-#endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
 #define NDTR0_tCH(c)    (min((c), 7) << 19)
 #define NDTR0_tCS(c)    (min((c), 7) << 16)
 #define NDTR0_tWH(c)    (min((c), 7) << 11)
@@ -1027,11 +893,6 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
        default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;
        default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;
-        if (default_flash.page_size == 2048)
-                default_flash.cmdset = &largepage_cmdset;
-        else
-                default_flash.cmdset = &smallpage_cmdset;
        /* set info fields needed to __readid */
        info->flash_info = &default_flash;
        info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
@@ -1068,6 +929,7 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
        pxa3xx_nand_detect_timing(info, &default_timing);
        default_flash.timing = &default_timing;
+        default_flash.cmdset = &default_cmdset;
        return 0;
 }
@@ -1096,10 +958,9 @@ static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
                        return 0;
        }
-#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
        for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
-                f = builtin_flash_types[i];
+                f = &builtin_flash_types[i];
                if (pxa3xx_nand_config_flash(info, f))
                        continue;
@@ -1110,7 +971,6 @@ static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
                if (id == f->chip_id)
                        return 0;
        }
-#endif
        dev_warn(&info->pdev->dev,
                 "failed to detect configured nand flash; found %04x instead of\n",
author	Lei Wen <leiwen@marvell.com>	2010-08-17 01:50:23 -0400
committer	David Woodhouse <David.Woodhouse@intel.com>	2010-10-24 18:38:47 -0400
commit	c1f82478c535f1de9fecf3cafa82014f312d5d4e (patch)
tree	d3713c7b47f472bfea939305b2a67ec5198f2768 /drivers/mtd/nand/pxa3xx_nand.c
parent	13ed7aed45e370f30a746e49e674144297a92e16 (diff)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 4d01cda68844..4e40de45f4be 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -176,21 +176,7 @@ MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
176	*/	176	*/
177	static struct pxa3xx_nand_timing default_timing;	177	static struct pxa3xx_nand_timing default_timing;
178	static struct pxa3xx_nand_flash default_flash;	178	static struct pxa3xx_nand_flash default_flash;
179		179	static struct pxa3xx_nand_cmdset default_cmdset = {
180	static struct pxa3xx_nand_cmdset smallpage_cmdset = {
181	.read1 = 0x0000,
182	.read2 = 0x0050,
183	.program = 0x1080,
184	.read_status = 0x0070,
185	.read_id = 0x0090,
186	.erase = 0xD060,
187	.reset = 0x00FF,
188	.lock = 0x002A,
189	.unlock = 0x2423,
190	.lock_status = 0x007A,
191	};
192
193	static struct pxa3xx_nand_cmdset largepage_cmdset = {
194	.read1 = 0x3000,	180	.read1 = 0x3000,
195	.read2 = 0x0050,	181	.read2 = 0x0050,
196	.program = 0x1080,	182	.program = 0x1080,
@@ -203,143 +189,23 @@ static struct pxa3xx_nand_cmdset largepage_cmdset = {
203	.lock_status = 0x007A,	189	.lock_status = 0x007A,
204	};	190	};
205		191
206	#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN	192	static struct pxa3xx_nand_timing timing[] = {
207	static struct pxa3xx_nand_timing samsung512MbX16_timing = {	193	{ 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
208	.tCH = 10,	194	{ 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
209	.tCS = 0,	195	{ 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
210	.tWH = 20,
211	.tWP = 40,
212	.tRH = 30,
213	.tRP = 40,
214	.tR = 11123,
215	.tWHR = 110,
216	.tAR = 10,
217	};
218
219	static struct pxa3xx_nand_flash samsung512MbX16 = {
220	.timing = &samsung512MbX16_timing,
221	.cmdset = &smallpage_cmdset,
222	.page_per_block = 32,
223	.page_size = 512,
224	.flash_width = 16,
225	.dfc_width = 16,
226	.num_blocks = 4096,
227	.chip_id = 0x46ec,
228	};
229
230	static struct pxa3xx_nand_flash samsung2GbX8 = {
231	.timing = &samsung512MbX16_timing,
232	.cmdset = &smallpage_cmdset,
233	.page_per_block = 64,
234	.page_size = 2048,
235	.flash_width = 8,
236	.dfc_width = 8,
237	.num_blocks = 2048,
238	.chip_id = 0xdaec,
239	};
240
241	static struct pxa3xx_nand_flash samsung32GbX8 = {
242	.timing = &samsung512MbX16_timing,
243	.cmdset = &smallpage_cmdset,
244	.page_per_block = 128,
245	.page_size = 4096,
246	.flash_width = 8,
247	.dfc_width = 8,
248	.num_blocks = 8192,
249	.chip_id = 0xd7ec,
250	};	196	};
251		197
252	static struct pxa3xx_nand_timing micron_timing = {	198	static struct pxa3xx_nand_flash builtin_flash_types[] = {
253	.tCH = 10,	199	{ 0x46ec, 32, 512, 16, 16, 4096, &default_cmdset, &timing[0] },
254	.tCS = 25,	200	{ 0xdaec, 64, 2048, 8, 8, 2048, &default_cmdset, &timing[0] },
255	.tWH = 15,	201	{ 0xd7ec, 128, 4096, 8, 8, 8192, &default_cmdset, &timing[0] },
256	.tWP = 25,	202	{ 0xa12c, 64, 2048, 8, 8, 1024, &default_cmdset, &timing[1] },
257	.tRH = 15,	203	{ 0xb12c, 64, 2048, 16, 16, 1024, &default_cmdset, &timing[1] },
258	.tRP = 30,	204	{ 0xdc2c, 64, 2048, 8, 8, 4096, &default_cmdset, &timing[1] },
259	.tR = 25000,	205	{ 0xcc2c, 64, 2048, 16, 16, 4096, &default_cmdset, &timing[1] },
260	.tWHR = 60,	206	{ 0xba20, 64, 2048, 16, 16, 2048, &default_cmdset, &timing[2] },
261	.tAR = 10,
262	};	207	};
263		208
264	static struct pxa3xx_nand_flash micron1GbX8 = {
265	.timing = &micron_timing,
266	.cmdset = &largepage_cmdset,
267	.page_per_block = 64,
268	.page_size = 2048,
269	.flash_width = 8,
270	.dfc_width = 8,
271	.num_blocks = 1024,
272	.chip_id = 0xa12c,
273	};
274
275	static struct pxa3xx_nand_flash micron1GbX16 = {
276	.timing = &micron_timing,
277	.cmdset = &largepage_cmdset,
278	.page_per_block = 64,
279	.page_size = 2048,
280	.flash_width = 16,
281	.dfc_width = 16,
282	.num_blocks = 1024,
283	.chip_id = 0xb12c,
284	};
285
286	static struct pxa3xx_nand_flash micron4GbX8 = {
287	.timing = &micron_timing,
288	.cmdset = &largepage_cmdset,
289	.page_per_block = 64,
290	.page_size = 2048,
291	.flash_width = 8,
292	.dfc_width = 8,
293	.num_blocks = 4096,
294	.chip_id = 0xdc2c,
295	};
296
297	static struct pxa3xx_nand_flash micron4GbX16 = {
298	.timing = &micron_timing,
299	.cmdset = &largepage_cmdset,
300	.page_per_block = 64,
301	.page_size = 2048,
302	.flash_width = 16,
303	.dfc_width = 16,
304	.num_blocks = 4096,
305	.chip_id = 0xcc2c,
306	};
307
308	static struct pxa3xx_nand_timing stm2GbX16_timing = {
309	.tCH = 10,
310	.tCS = 35,
311	.tWH = 15,
312	.tWP = 25,
313	.tRH = 15,
314	.tRP = 25,
315	.tR = 25000,
316	.tWHR = 60,
317	.tAR = 10,
318	};
319
320	static struct pxa3xx_nand_flash stm2GbX16 = {
321	.timing = &stm2GbX16_timing,
322	.cmdset = &largepage_cmdset,
323	.page_per_block = 64,
324	.page_size = 2048,
325	.flash_width = 16,
326	.dfc_width = 16,
327	.num_blocks = 2048,
328	.chip_id = 0xba20,
329	};
330
331	static struct pxa3xx_nand_flash *builtin_flash_types[] = {
332	&samsung512MbX16,
333	&samsung2GbX8,
334	&samsung32GbX8,
335	&micron1GbX8,
336	&micron1GbX16,
337	&micron4GbX8,
338	&micron4GbX16,
339	&stm2GbX16,
340	};
341	#endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
342
343	#define NDTR0_tCH(c) (min((c), 7) << 19)	209	#define NDTR0_tCH(c) (min((c), 7) << 19)
344	#define NDTR0_tCS(c) (min((c), 7) << 16)	210	#define NDTR0_tCS(c) (min((c), 7) << 16)
345	#define NDTR0_tWH(c) (min((c), 7) << 11)	211	#define NDTR0_tWH(c) (min((c), 7) << 11)
@@ -1027,11 +893,6 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
1027	default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;	893	default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;
1028	default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;	894	default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;
1029		895
1030	if (default_flash.page_size == 2048)
1031	default_flash.cmdset = &largepage_cmdset;
1032	else
1033	default_flash.cmdset = &smallpage_cmdset;
1034
1035	/* set info fields needed to __readid */	896	/* set info fields needed to __readid */
1036	info->flash_info = &default_flash;	897	info->flash_info = &default_flash;
1037	info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;	898	info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
@@ -1068,6 +929,7 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
1068		929
1069	pxa3xx_nand_detect_timing(info, &default_timing);	930	pxa3xx_nand_detect_timing(info, &default_timing);
1070	default_flash.timing = &default_timing;	931	default_flash.timing = &default_timing;
		932	default_flash.cmdset = &default_cmdset;
1071		933
1072	return 0;	934	return 0;
1073	}	935	}
@@ -1096,10 +958,9 @@ static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
1096	return 0;	958	return 0;
1097	}	959	}
1098		960
1099	#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
1100	for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {	961	for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
1101		962
1102	f = builtin_flash_types[i];	963	f = &builtin_flash_types[i];
1103		964
1104	if (pxa3xx_nand_config_flash(info, f))	965	if (pxa3xx_nand_config_flash(info, f))
1105	continue;	966	continue;
@@ -1110,7 +971,6 @@ static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
1110	if (id == f->chip_id)	971	if (id == f->chip_id)
1111	return 0;	972	return 0;
1112	}	973	}
1113	#endif
1114		974
1115	dev_warn(&info->pdev->dev,	975	dev_warn(&info->pdev->dev,
1116	"failed to detect configured nand flash; found %04x instead of\n",	976	"failed to detect configured nand flash; found %04x instead of\n",