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authorLinus Torvalds <torvalds@linux-foundation.org>2010-03-02 13:34:25 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2010-03-02 13:34:25 -0500
commit5057bfaff82e12f01a2ffd58f55535cbd7c5c3a2 (patch)
tree0397253173308317480ed82f0b75af46cd3f6cb1 /drivers/mtd/nand/omap2.c
parent6c0ad5dfd3d5ad6def89b485ee52834547da239b (diff)
parentd702d12167a2c05a346f49aac7a311d597762495 (diff)
Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (214 commits) omap2: Initialize Menelaus and MMC for N8X0 AM3517 EVM: correct typo - tca6416 mispelt as tca6516 AM3517 EVM: Enable I2C support AM35x: Enable OMAP_MUX in defconfig AM35x: Add missing GPIO mux config for EHCI port Zoom3: Defconfig update omap: i2c: Fix muxing for command line enabled bus OMAP4: clock: Remove clock hacks from timer-gp.c OMAP4: clock: Add dummy clock nodes for interface clocks OMAP4: clock: Rename leaf clock nodes to end with a _ick or _fck OMAP2+ clock: revise omap2_clk_{disable,enable}() OMAP2/3 clock: combine OMAP2 & 3 boot-time MPU rate change code OMAP clockdomain: if no autodeps exist, don't try to add or remove them OMAP hwmod: add hwmod class support OMAP hwmod: convert header files with static allocations into C files OMAP hwmod: convert hwmod to use hardware clock names rather than clkdev dev+con OMAP clock: add omap_clk_get_by_name() for use by OMAP hwmod core code OMAP3: clock: add capability to change rate of dpll4_m5_ck_3630 OMAP4 clock: drop the ALWAYS_ENABLED clock flag OMAP clock: drop RATE_FIXED clock flag ...
Diffstat (limited to 'drivers/mtd/nand/omap2.c')
-rw-r--r--drivers/mtd/nand/omap2.c35
1 files changed, 4 insertions, 31 deletions
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 1bb799f0125c..26aec0080184 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -30,12 +30,8 @@
30 30
31#define DRIVER_NAME "omap2-nand" 31#define DRIVER_NAME "omap2-nand"
32 32
33/* size (4 KiB) for IO mapping */
34#define NAND_IO_SIZE SZ_4K
35
36#define NAND_WP_OFF 0 33#define NAND_WP_OFF 0
37#define NAND_WP_BIT 0x00000010 34#define NAND_WP_BIT 0x00000010
38#define WR_RD_PIN_MONITORING 0x00600000
39 35
40#define GPMC_BUF_FULL 0x00000001 36#define GPMC_BUF_FULL 0x00000001
41#define GPMC_BUF_EMPTY 0x00000000 37#define GPMC_BUF_EMPTY 0x00000000
@@ -882,8 +878,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
882 struct omap_nand_info *info; 878 struct omap_nand_info *info;
883 struct omap_nand_platform_data *pdata; 879 struct omap_nand_platform_data *pdata;
884 int err; 880 int err;
885 unsigned long val;
886
887 881
888 pdata = pdev->dev.platform_data; 882 pdata = pdev->dev.platform_data;
889 if (pdata == NULL) { 883 if (pdata == NULL) {
@@ -905,28 +899,14 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
905 info->gpmc_cs = pdata->cs; 899 info->gpmc_cs = pdata->cs;
906 info->gpmc_baseaddr = pdata->gpmc_baseaddr; 900 info->gpmc_baseaddr = pdata->gpmc_baseaddr;
907 info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr; 901 info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr;
902 info->phys_base = pdata->phys_base;
908 903
909 info->mtd.priv = &info->nand; 904 info->mtd.priv = &info->nand;
910 info->mtd.name = dev_name(&pdev->dev); 905 info->mtd.name = dev_name(&pdev->dev);
911 info->mtd.owner = THIS_MODULE; 906 info->mtd.owner = THIS_MODULE;
912 907
913 err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base); 908 info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0;
914 if (err < 0) { 909 info->nand.options |= NAND_SKIP_BBTSCAN;
915 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
916 goto out_free_info;
917 }
918
919 /* Enable RD PIN Monitoring Reg */
920 if (pdata->dev_ready) {
921 val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
922 val |= WR_RD_PIN_MONITORING;
923 gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
924 }
925
926 val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7);
927 val &= ~(0xf << 8);
928 val |= (0xc & 0xf) << 8;
929 gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val);
930 910
931 /* NAND write protect off */ 911 /* NAND write protect off */
932 omap_nand_wp(&info->mtd, NAND_WP_OFF); 912 omap_nand_wp(&info->mtd, NAND_WP_OFF);
@@ -934,7 +914,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
934 if (!request_mem_region(info->phys_base, NAND_IO_SIZE, 914 if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
935 pdev->dev.driver->name)) { 915 pdev->dev.driver->name)) {
936 err = -EBUSY; 916 err = -EBUSY;
937 goto out_free_cs; 917 goto out_free_info;
938 } 918 }
939 919
940 info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE); 920 info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
@@ -963,11 +943,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
963 info->nand.chip_delay = 50; 943 info->nand.chip_delay = 50;
964 } 944 }
965 945
966 info->nand.options |= NAND_SKIP_BBTSCAN;
967 if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000)
968 == 0x1000)
969 info->nand.options |= NAND_BUSWIDTH_16;
970
971 if (use_prefetch) { 946 if (use_prefetch) {
972 /* copy the virtual address of nand base for fifo access */ 947 /* copy the virtual address of nand base for fifo access */
973 info->nand_pref_fifo_add = info->nand.IO_ADDR_R; 948 info->nand_pref_fifo_add = info->nand.IO_ADDR_R;
@@ -1043,8 +1018,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
1043 1018
1044out_release_mem_region: 1019out_release_mem_region:
1045 release_mem_region(info->phys_base, NAND_IO_SIZE); 1020 release_mem_region(info->phys_base, NAND_IO_SIZE);
1046out_free_cs:
1047 gpmc_cs_free(info->gpmc_cs);
1048out_free_info: 1021out_free_info:
1049 kfree(info); 1022 kfree(info);
1050 1023