diff options
| author | Thomas Gleixner <tglx@cruncher.tec.linutronix.de> | 2006-05-24 16:57:09 -0400 |
|---|---|---|
| committer | David Woodhouse <dwmw2@infradead.org> | 2006-05-24 18:45:24 -0400 |
| commit | 12efdde3139c568a59561b69865fd14f37c75603 (patch) | |
| tree | ef5b0b445dd6da3ab61120bee09b3c93fae953a8 /drivers/mtd/nand/nand_base.c | |
| parent | ace4dfee56fff184e07d7248a759b574321afa8b (diff) | |
[MTD] NAND fix cmd_ctrl breakage
The cmd_ctrl rework lacks some state transition flags.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/mtd/nand/nand_base.c')
| -rw-r--r-- | drivers/mtd/nand/nand_base.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 6036d322bf68..5690de223c11 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c | |||
| @@ -538,7 +538,8 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, | |||
| 538 | udelay(chip->chip_delay); | 538 | udelay(chip->chip_delay); |
| 539 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | 539 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
| 540 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); | 540 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
| 541 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE); | 541 | chip->cmd_ctrl(mtd, |
| 542 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | ||
| 542 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; | 543 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
| 543 | return; | 544 | return; |
| 544 | 545 | ||
| @@ -641,14 +642,18 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, | |||
| 641 | if (chip->dev_ready) | 642 | if (chip->dev_ready) |
| 642 | break; | 643 | break; |
| 643 | udelay(chip->chip_delay); | 644 | udelay(chip->chip_delay); |
| 644 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, NAND_NCE | NAND_CLE); | 645 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
| 645 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE); | 646 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
| 647 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | ||
| 648 | NAND_NCE | NAND_CTRL_CHANGE); | ||
| 646 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; | 649 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
| 647 | return; | 650 | return; |
| 648 | 651 | ||
| 649 | case NAND_CMD_READ0: | 652 | case NAND_CMD_READ0: |
| 650 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_NCE | NAND_CLE); | 653 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
| 651 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE); | 654 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
| 655 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | ||
| 656 | NAND_NCE | NAND_CTRL_CHANGE); | ||
| 652 | 657 | ||
| 653 | /* This applies to read commands */ | 658 | /* This applies to read commands */ |
| 654 | default: | 659 | default: |