diff options
| author | Jamie Iles <jamie@jamieiles.com> | 2011-05-06 10:28:56 -0400 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2011-05-24 21:02:01 -0400 |
| commit | 9589bf5bed2936a159fc96c96339f15a512fdfa9 (patch) | |
| tree | ca0547147e34fc91ba7112c00315fd518dbfa16a /drivers/mtd/nand/denali.h | |
| parent | 84457949e4921f15548a9d317a4a4318b3c3af75 (diff) | |
mtd: denali: remove nearly-duplicated register definitions
The controller has interrupt enable/status register pairs for each bank
(along with ECC and status registers) that differ only in address offset.
Rather than providing definitions for each register, make the address a
macro so that it scales for devices with different numbers of banks.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/nand/denali.h')
| -rw-r--r-- | drivers/mtd/nand/denali.h | 371 |
1 files changed, 57 insertions, 314 deletions
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 9b875fd23687..638668c4b41f 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h | |||
| @@ -211,185 +211,46 @@ | |||
| 211 | #define TRANSFER_MODE 0x400 | 211 | #define TRANSFER_MODE 0x400 |
| 212 | #define TRANSFER_MODE__VALUE 0x0003 | 212 | #define TRANSFER_MODE__VALUE 0x0003 |
| 213 | 213 | ||
| 214 | #define INTR_STATUS0 0x410 | 214 | #define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50)) |
| 215 | #define INTR_STATUS0__ECC_TRANSACTION_DONE 0x0001 | 215 | #define INTR_EN(__bank) (0x420 + ((__bank) * 0x50)) |
| 216 | #define INTR_STATUS0__ECC_ERR 0x0002 | 216 | |
| 217 | #define INTR_STATUS0__DMA_CMD_COMP 0x0004 | 217 | #define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001 |
| 218 | #define INTR_STATUS0__TIME_OUT 0x0008 | 218 | #define INTR_STATUS__ECC_ERR 0x0002 |
| 219 | #define INTR_STATUS0__PROGRAM_FAIL 0x0010 | 219 | #define INTR_STATUS__DMA_CMD_COMP 0x0004 |
| 220 | #define INTR_STATUS0__ERASE_FAIL 0x0020 | 220 | #define INTR_STATUS__TIME_OUT 0x0008 |
| 221 | #define INTR_STATUS0__LOAD_COMP 0x0040 | 221 | #define INTR_STATUS__PROGRAM_FAIL 0x0010 |
| 222 | #define INTR_STATUS0__PROGRAM_COMP 0x0080 | 222 | #define INTR_STATUS__ERASE_FAIL 0x0020 |
| 223 | #define INTR_STATUS0__ERASE_COMP 0x0100 | 223 | #define INTR_STATUS__LOAD_COMP 0x0040 |
| 224 | #define INTR_STATUS0__PIPE_CPYBCK_CMD_COMP 0x0200 | 224 | #define INTR_STATUS__PROGRAM_COMP 0x0080 |
| 225 | #define INTR_STATUS0__LOCKED_BLK 0x0400 | 225 | #define INTR_STATUS__ERASE_COMP 0x0100 |
| 226 | #define INTR_STATUS0__UNSUP_CMD 0x0800 | 226 | #define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200 |
| 227 | #define INTR_STATUS0__INT_ACT 0x1000 | 227 | #define INTR_STATUS__LOCKED_BLK 0x0400 |
| 228 | #define INTR_STATUS0__RST_COMP 0x2000 | 228 | #define INTR_STATUS__UNSUP_CMD 0x0800 |
| 229 | #define INTR_STATUS0__PIPE_CMD_ERR 0x4000 | 229 | #define INTR_STATUS__INT_ACT 0x1000 |
| 230 | #define INTR_STATUS0__PAGE_XFER_INC 0x8000 | 230 | #define INTR_STATUS__RST_COMP 0x2000 |
| 231 | 231 | #define INTR_STATUS__PIPE_CMD_ERR 0x4000 | |
| 232 | #define INTR_EN0 0x420 | 232 | #define INTR_STATUS__PAGE_XFER_INC 0x8000 |
| 233 | #define INTR_EN0__ECC_TRANSACTION_DONE 0x0001 | 233 | |
| 234 | #define INTR_EN0__ECC_ERR 0x0002 | 234 | #define INTR_EN__ECC_TRANSACTION_DONE 0x0001 |
| 235 | #define INTR_EN0__DMA_CMD_COMP 0x0004 | 235 | #define INTR_EN__ECC_ERR 0x0002 |
| 236 | #define INTR_EN0__TIME_OUT 0x0008 | 236 | #define INTR_EN__DMA_CMD_COMP 0x0004 |
| 237 | #define INTR_EN0__PROGRAM_FAIL 0x0010 | 237 | #define INTR_EN__TIME_OUT 0x0008 |
| 238 | #define INTR_EN0__ERASE_FAIL 0x0020 | 238 | #define INTR_EN__PROGRAM_FAIL 0x0010 |
| 239 | #define INTR_EN0__LOAD_COMP 0x0040 | 239 | #define INTR_EN__ERASE_FAIL 0x0020 |
| 240 | #define INTR_EN0__PROGRAM_COMP 0x0080 | 240 | #define INTR_EN__LOAD_COMP 0x0040 |
| 241 | #define INTR_EN0__ERASE_COMP 0x0100 | 241 | #define INTR_EN__PROGRAM_COMP 0x0080 |
| 242 | #define INTR_EN0__PIPE_CPYBCK_CMD_COMP 0x0200 | 242 | #define INTR_EN__ERASE_COMP 0x0100 |
| 243 | #define INTR_EN0__LOCKED_BLK 0x0400 | 243 | #define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200 |
| 244 | #define INTR_EN0__UNSUP_CMD 0x0800 | 244 | #define INTR_EN__LOCKED_BLK 0x0400 |
| 245 | #define INTR_EN0__INT_ACT 0x1000 | 245 | #define INTR_EN__UNSUP_CMD 0x0800 |
| 246 | #define INTR_EN0__RST_COMP 0x2000 | 246 | #define INTR_EN__INT_ACT 0x1000 |
| 247 | #define INTR_EN0__PIPE_CMD_ERR 0x4000 | 247 | #define INTR_EN__RST_COMP 0x2000 |
| 248 | #define INTR_EN0__PAGE_XFER_INC 0x8000 | 248 | #define INTR_EN__PIPE_CMD_ERR 0x4000 |
| 249 | 249 | #define INTR_EN__PAGE_XFER_INC 0x8000 | |
| 250 | #define PAGE_CNT0 0x430 | 250 | |
| 251 | #define PAGE_CNT0__VALUE 0x00ff | 251 | #define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50)) |
| 252 | 252 | #define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50)) | |
| 253 | #define ERR_PAGE_ADDR0 0x440 | 253 | #define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50)) |
| 254 | #define ERR_PAGE_ADDR0__VALUE 0xffff | ||
| 255 | |||
| 256 | #define ERR_BLOCK_ADDR0 0x450 | ||
| 257 | #define ERR_BLOCK_ADDR0__VALUE 0xffff | ||
| 258 | |||
| 259 | #define INTR_STATUS1 0x460 | ||
| 260 | #define INTR_STATUS1__ECC_TRANSACTION_DONE 0x0001 | ||
| 261 | #define INTR_STATUS1__ECC_ERR 0x0002 | ||
| 262 | #define INTR_STATUS1__DMA_CMD_COMP 0x0004 | ||
| 263 | #define INTR_STATUS1__TIME_OUT 0x0008 | ||
| 264 | #define INTR_STATUS1__PROGRAM_FAIL 0x0010 | ||
| 265 | #define INTR_STATUS1__ERASE_FAIL 0x0020 | ||
| 266 | #define INTR_STATUS1__LOAD_COMP 0x0040 | ||
| 267 | #define INTR_STATUS1__PROGRAM_COMP 0x0080 | ||
| 268 | #define INTR_STATUS1__ERASE_COMP 0x0100 | ||
| 269 | #define INTR_STATUS1__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
| 270 | #define INTR_STATUS1__LOCKED_BLK 0x0400 | ||
| 271 | #define INTR_STATUS1__UNSUP_CMD 0x0800 | ||
| 272 | #define INTR_STATUS1__INT_ACT 0x1000 | ||
| 273 | #define INTR_STATUS1__RST_COMP 0x2000 | ||
| 274 | #define INTR_STATUS1__PIPE_CMD_ERR 0x4000 | ||
| 275 | #define INTR_STATUS1__PAGE_XFER_INC 0x8000 | ||
| 276 | |||
| 277 | #define INTR_EN1 0x470 | ||
| 278 | #define INTR_EN1__ECC_TRANSACTION_DONE 0x0001 | ||
| 279 | #define INTR_EN1__ECC_ERR 0x0002 | ||
| 280 | #define INTR_EN1__DMA_CMD_COMP 0x0004 | ||
| 281 | #define INTR_EN1__TIME_OUT 0x0008 | ||
| 282 | #define INTR_EN1__PROGRAM_FAIL 0x0010 | ||
| 283 | #define INTR_EN1__ERASE_FAIL 0x0020 | ||
| 284 | #define INTR_EN1__LOAD_COMP 0x0040 | ||
| 285 | #define INTR_EN1__PROGRAM_COMP 0x0080 | ||
| 286 | #define INTR_EN1__ERASE_COMP 0x0100 | ||
| 287 | #define INTR_EN1__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
| 288 | #define INTR_EN1__LOCKED_BLK 0x0400 | ||
| 289 | #define INTR_EN1__UNSUP_CMD 0x0800 | ||
| 290 | #define INTR_EN1__INT_ACT 0x1000 | ||
| 291 | #define INTR_EN1__RST_COMP 0x2000 | ||
| 292 | #define INTR_EN1__PIPE_CMD_ERR 0x4000 | ||
| 293 | #define INTR_EN1__PAGE_XFER_INC 0x8000 | ||
| 294 | |||
| 295 | #define PAGE_CNT1 0x480 | ||
| 296 | #define PAGE_CNT1__VALUE 0x00ff | ||
| 297 | |||
| 298 | #define ERR_PAGE_ADDR1 0x490 | ||
| 299 | #define ERR_PAGE_ADDR1__VALUE 0xffff | ||
| 300 | |||
| 301 | #define ERR_BLOCK_ADDR1 0x4a0 | ||
| 302 | #define ERR_BLOCK_ADDR1__VALUE 0xffff | ||
| 303 | |||
| 304 | #define INTR_STATUS2 0x4b0 | ||
| 305 | #define INTR_STATUS2__ECC_TRANSACTION_DONE 0x0001 | ||
| 306 | #define INTR_STATUS2__ECC_ERR 0x0002 | ||
| 307 | #define INTR_STATUS2__DMA_CMD_COMP 0x0004 | ||
| 308 | #define INTR_STATUS2__TIME_OUT 0x0008 | ||
| 309 | #define INTR_STATUS2__PROGRAM_FAIL 0x0010 | ||
| 310 | #define INTR_STATUS2__ERASE_FAIL 0x0020 | ||
| 311 | #define INTR_STATUS2__LOAD_COMP 0x0040 | ||
| 312 | #define INTR_STATUS2__PROGRAM_COMP 0x0080 | ||
| 313 | #define INTR_STATUS2__ERASE_COMP 0x0100 | ||
| 314 | #define INTR_STATUS2__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
| 315 | #define INTR_STATUS2__LOCKED_BLK 0x0400 | ||
| 316 | #define INTR_STATUS2__UNSUP_CMD 0x0800 | ||
| 317 | #define INTR_STATUS2__INT_ACT 0x1000 | ||
| 318 | #define INTR_STATUS2__RST_COMP 0x2000 | ||
| 319 | #define INTR_STATUS2__PIPE_CMD_ERR 0x4000 | ||
| 320 | #define INTR_STATUS2__PAGE_XFER_INC 0x8000 | ||
| 321 | |||
| 322 | #define INTR_EN2 0x4c0 | ||
| 323 | #define INTR_EN2__ECC_TRANSACTION_DONE 0x0001 | ||
| 324 | #define INTR_EN2__ECC_ERR 0x0002 | ||
| 325 | #define INTR_EN2__DMA_CMD_COMP 0x0004 | ||
| 326 | #define INTR_EN2__TIME_OUT 0x0008 | ||
| 327 | #define INTR_EN2__PROGRAM_FAIL 0x0010 | ||
| 328 | #define INTR_EN2__ERASE_FAIL 0x0020 | ||
| 329 | #define INTR_EN2__LOAD_COMP 0x0040 | ||
| 330 | #define INTR_EN2__PROGRAM_COMP 0x0080 | ||
| 331 | #define INTR_EN2__ERASE_COMP 0x0100 | ||
| 332 | #define INTR_EN2__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
| 333 | #define INTR_EN2__LOCKED_BLK 0x0400 | ||
| 334 | #define INTR_EN2__UNSUP_CMD 0x0800 | ||
| 335 | #define INTR_EN2__INT_ACT 0x1000 | ||
| 336 | #define INTR_EN2__RST_COMP 0x2000 | ||
| 337 | #define INTR_EN2__PIPE_CMD_ERR 0x4000 | ||
| 338 | #define INTR_EN2__PAGE_XFER_INC 0x8000 | ||
| 339 | |||
| 340 | #define PAGE_CNT2 0x4d0 | ||
| 341 | #define PAGE_CNT2__VALUE 0x00ff | ||
| 342 | |||
| 343 | #define ERR_PAGE_ADDR2 0x4e0 | ||
| 344 | #define ERR_PAGE_ADDR2__VALUE 0xffff | ||
| 345 | |||
| 346 | #define ERR_BLOCK_ADDR2 0x4f0 | ||
| 347 | #define ERR_BLOCK_ADDR2__VALUE 0xffff | ||
| 348 | |||
| 349 | #define INTR_STATUS3 0x500 | ||
| 350 | #define INTR_STATUS3__ECC_TRANSACTION_DONE 0x0001 | ||
| 351 | #define INTR_STATUS3__ECC_ERR 0x0002 | ||
| 352 | #define INTR_STATUS3__DMA_CMD_COMP 0x0004 | ||
| 353 | #define INTR_STATUS3__TIME_OUT 0x0008 | ||
| 354 | #define INTR_STATUS3__PROGRAM_FAIL 0x0010 | ||
| 355 | #define INTR_STATUS3__ERASE_FAIL 0x0020 | ||
| 356 | #define INTR_STATUS3__LOAD_COMP 0x0040 | ||
| 357 | #define INTR_STATUS3__PROGRAM_COMP 0x0080 | ||
| 358 | #define INTR_STATUS3__ERASE_COMP 0x0100 | ||
| 359 | #define INTR_STATUS3__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
| 360 | #define INTR_STATUS3__LOCKED_BLK 0x0400 | ||
| 361 | #define INTR_STATUS3__UNSUP_CMD 0x0800 | ||
| 362 | #define INTR_STATUS3__INT_ACT 0x1000 | ||
| 363 | #define INTR_STATUS3__RST_COMP 0x2000 | ||
| 364 | #define INTR_STATUS3__PIPE_CMD_ERR 0x4000 | ||
| 365 | #define INTR_STATUS3__PAGE_XFER_INC 0x8000 | ||
| 366 | |||
| 367 | #define INTR_EN3 0x510 | ||
| 368 | #define INTR_EN3__ECC_TRANSACTION_DONE 0x0001 | ||
| 369 | #define INTR_EN3__ECC_ERR 0x0002 | ||
| 370 | #define INTR_EN3__DMA_CMD_COMP 0x0004 | ||
| 371 | #define INTR_EN3__TIME_OUT 0x0008 | ||
| 372 | #define INTR_EN3__PROGRAM_FAIL 0x0010 | ||
| 373 | #define INTR_EN3__ERASE_FAIL 0x0020 | ||
| 374 | #define INTR_EN3__LOAD_COMP 0x0040 | ||
| 375 | #define INTR_EN3__PROGRAM_COMP 0x0080 | ||
| 376 | #define INTR_EN3__ERASE_COMP 0x0100 | ||
| 377 | #define INTR_EN3__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
| 378 | #define INTR_EN3__LOCKED_BLK 0x0400 | ||
| 379 | #define INTR_EN3__UNSUP_CMD 0x0800 | ||
| 380 | #define INTR_EN3__INT_ACT 0x1000 | ||
| 381 | #define INTR_EN3__RST_COMP 0x2000 | ||
| 382 | #define INTR_EN3__PIPE_CMD_ERR 0x4000 | ||
| 383 | #define INTR_EN3__PAGE_XFER_INC 0x8000 | ||
| 384 | |||
| 385 | #define PAGE_CNT3 0x520 | ||
| 386 | #define PAGE_CNT3__VALUE 0x00ff | ||
| 387 | |||
| 388 | #define ERR_PAGE_ADDR3 0x530 | ||
| 389 | #define ERR_PAGE_ADDR3__VALUE 0xffff | ||
| 390 | |||
| 391 | #define ERR_BLOCK_ADDR3 0x540 | ||
| 392 | #define ERR_BLOCK_ADDR3__VALUE 0xffff | ||
| 393 | 254 | ||
| 394 | #define DATA_INTR 0x550 | 255 | #define DATA_INTR 0x550 |
| 395 | #define DATA_INTR__WRITE_SPACE_AV 0x0001 | 256 | #define DATA_INTR__WRITE_SPACE_AV 0x0001 |
| @@ -484,141 +345,23 @@ | |||
| 484 | #define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 | 345 | #define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 |
| 485 | #define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 | 346 | #define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 |
| 486 | 347 | ||
| 487 | #define PERM_SRC_ID_0 0x830 | 348 | #define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40)) |
| 488 | #define PERM_SRC_ID_0__SRCID 0x00ff | 349 | #define PERM_SRC_ID__SRCID 0x00ff |
| 489 | #define PERM_SRC_ID_0__DIRECT_ACCESS_ACTIVE 0x0800 | 350 | #define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800 |
| 490 | #define PERM_SRC_ID_0__WRITE_ACTIVE 0x2000 | 351 | #define PERM_SRC_ID__WRITE_ACTIVE 0x2000 |
| 491 | #define PERM_SRC_ID_0__READ_ACTIVE 0x4000 | 352 | #define PERM_SRC_ID__READ_ACTIVE 0x4000 |
| 492 | #define PERM_SRC_ID_0__PARTITION_VALID 0x8000 | 353 | #define PERM_SRC_ID__PARTITION_VALID 0x8000 |
| 493 | 354 | ||
| 494 | #define MIN_BLK_ADDR_0 0x840 | 355 | #define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40)) |
| 495 | #define MIN_BLK_ADDR_0__VALUE 0xffff | 356 | #define MIN_BLK_ADDR__VALUE 0xffff |
| 496 | 357 | ||
| 497 | #define MAX_BLK_ADDR_0 0x850 | 358 | #define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40)) |
| 498 | #define MAX_BLK_ADDR_0__VALUE 0xffff | 359 | #define MAX_BLK_ADDR__VALUE 0xffff |
| 499 | 360 | ||
| 500 | #define MIN_MAX_BANK_0 0x860 | 361 | #define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40)) |
| 501 | #define MIN_MAX_BANK_0__MIN_VALUE 0x0003 | 362 | #define MIN_MAX_BANK__MIN_VALUE 0x0003 |
| 502 | #define MIN_MAX_BANK_0__MAX_VALUE 0x000c | 363 | #define MIN_MAX_BANK__MAX_VALUE 0x000c |
| 503 | 364 | ||
| 504 | #define PERM_SRC_ID_1 0x870 | ||
| 505 | #define PERM_SRC_ID_1__SRCID 0x00ff | ||
| 506 | #define PERM_SRC_ID_1__DIRECT_ACCESS_ACTIVE 0x0800 | ||
| 507 | #define PERM_SRC_ID_1__WRITE_ACTIVE 0x2000 | ||
| 508 | #define PERM_SRC_ID_1__READ_ACTIVE 0x4000 | ||
| 509 | #define PERM_SRC_ID_1__PARTITION_VALID 0x8000 | ||
| 510 | |||
| 511 | #define MIN_BLK_ADDR_1 0x880 | ||
| 512 | #define MIN_BLK_ADDR_1__VALUE 0xffff | ||
| 513 | |||
| 514 | #define MAX_BLK_ADDR_1 0x890 | ||
| 515 | #define MAX_BLK_ADDR_1__VALUE 0xffff | ||
| 516 | |||
| 517 | #define MIN_MAX_BANK_1 0x8a0 | ||
| 518 | #define MIN_MAX_BANK_1__MIN_VALUE 0x0003 | ||
| 519 | #define MIN_MAX_BANK_1__MAX_VALUE 0x000c | ||
| 520 | |||
| 521 | #define PERM_SRC_ID_2 0x8b0 | ||
| 522 | #define PERM_SRC_ID_2__SRCID 0x00ff | ||
| 523 | #define PERM_SRC_ID_2__DIRECT_ACCESS_ACTIVE 0x0800 | ||
| 524 | #define PERM_SRC_ID_2__WRITE_ACTIVE 0x2000 | ||
| 525 | #define PERM_SRC_ID_2__READ_ACTIVE 0x4000 | ||
| 526 | #define PERM_SRC_ID_2__PARTITION_VALID 0x8000 | ||
| 527 | |||
| 528 | #define MIN_BLK_ADDR_2 0x8c0 | ||
| 529 | #define MIN_BLK_ADDR_2__VALUE 0xffff | ||
| 530 | |||
| 531 | #define MAX_BLK_ADDR_2 0x8d0 | ||
| 532 | #define MAX_BLK_ADDR_2__VALUE 0xffff | ||
| 533 | |||
| 534 | #define MIN_MAX_BANK_2 0x8e0 | ||
| 535 | #define MIN_MAX_BANK_2__MIN_VALUE 0x0003 | ||
| 536 | #define MIN_MAX_BANK_2__MAX_VALUE 0x000c | ||
| 537 | |||
| 538 | #define PERM_SRC_ID_3 0x8f0 | ||
| 539 | #define PERM_SRC_ID_3__SRCID 0x00ff | ||
| 540 | #define PERM_SRC_ID_3__DIRECT_ACCESS_ACTIVE 0x0800 | ||
| 541 | #define PERM_SRC_ID_3__WRITE_ACTIVE 0x2000 | ||
| 542 | #define PERM_SRC_ID_3__READ_ACTIVE 0x4000 | ||
| 543 | #define PERM_SRC_ID_3__PARTITION_VALID 0x8000 | ||
| 544 | |||
| 545 | #define MIN_BLK_ADDR_3 0x900 | ||
| 546 | #define MIN_BLK_ADDR_3__VALUE 0xffff | ||
| 547 | |||
| 548 | #define MAX_BLK_ADDR_3 0x910 | ||
| 549 | #define MAX_BLK_ADDR_3__VALUE 0xffff | ||
| 550 | |||
| 551 | #define MIN_MAX_BANK_3 0x920 | ||
| 552 | #define MIN_MAX_BANK_3__MIN_VALUE 0x0003 | ||
| 553 | #define MIN_MAX_BANK_3__MAX_VALUE 0x000c | ||
| 554 | |||
| 555 | #define PERM_SRC_ID_4 0x930 | ||
| 556 | #define PERM_SRC_ID_4__SRCID 0x00ff | ||
| 557 | #define PERM_SRC_ID_4__DIRECT_ACCESS_ACTIVE 0x0800 | ||
| 558 | #define PERM_SRC_ID_4__WRITE_ACTIVE 0x2000 | ||
| 559 | #define PERM_SRC_ID_4__READ_ACTIVE 0x4000 | ||
| 560 | #define PERM_SRC_ID_4__PARTITION_VALID 0x8000 | ||
| 561 | |||
| 562 | #define MIN_BLK_ADDR_4 0x940 | ||
| 563 | #define MIN_BLK_ADDR_4__VALUE 0xffff | ||
| 564 | |||
| 565 | #define MAX_BLK_ADDR_4 0x950 | ||
| 566 | #define MAX_BLK_ADDR_4__VALUE 0xffff | ||
| 567 | |||
| 568 | #define MIN_MAX_BANK_4 0x960 | ||
| 569 | #define MIN_MAX_BANK_4__MIN_VALUE 0x0003 | ||
| 570 | #define MIN_MAX_BANK_4__MAX_VALUE 0x000c | ||
| 571 | |||
| 572 | #define PERM_SRC_ID_5 0x970 | ||
| 573 | #define PERM_SRC_ID_5__SRCID 0x00ff | ||
| 574 | #define PERM_SRC_ID_5__DIRECT_ACCESS_ACTIVE 0x0800 | ||
| 575 | #define PERM_SRC_ID_5__WRITE_ACTIVE 0x2000 | ||
| 576 | #define PERM_SRC_ID_5__READ_ACTIVE 0x4000 | ||
| 577 | #define PERM_SRC_ID_5__PARTITION_VALID 0x8000 | ||
| 578 | |||
| 579 | #define MIN_BLK_ADDR_5 0x980 | ||
| 580 | #define MIN_BLK_ADDR_5__VALUE 0xffff | ||
| 581 | |||
| 582 | #define MAX_BLK_ADDR_5 0x990 | ||
| 583 | #define MAX_BLK_ADDR_5__VALUE 0xffff | ||
| 584 | |||
| 585 | #define MIN_MAX_BANK_5 0x9a0 | ||
| 586 | #define MIN_MAX_BANK_5__MIN_VALUE 0x0003 | ||
| 587 | #define MIN_MAX_BANK_5__MAX_VALUE 0x000c | ||
| 588 | |||
| 589 | #define PERM_SRC_ID_6 0x9b0 | ||
| 590 | #define PERM_SRC_ID_6__SRCID 0x00ff | ||
| 591 | #define PERM_SRC_ID_6__DIRECT_ACCESS_ACTIVE 0x0800 | ||
| 592 | #define PERM_SRC_ID_6__WRITE_ACTIVE 0x2000 | ||
| 593 | #define PERM_SRC_ID_6__READ_ACTIVE 0x4000 | ||
| 594 | #define PERM_SRC_ID_6__PARTITION_VALID 0x8000 | ||
| 595 | |||
| 596 | #define MIN_BLK_ADDR_6 0x9c0 | ||
| 597 | #define MIN_BLK_ADDR_6__VALUE 0xffff | ||
| 598 | |||
| 599 | #define MAX_BLK_ADDR_6 0x9d0 | ||
| 600 | #define MAX_BLK_ADDR_6__VALUE 0xffff | ||
| 601 | |||
| 602 | #define MIN_MAX_BANK_6 0x9e0 | ||
| 603 | #define MIN_MAX_BANK_6__MIN_VALUE 0x0003 | ||
| 604 | #define MIN_MAX_BANK_6__MAX_VALUE 0x000c | ||
| 605 | |||
| 606 | #define PERM_SRC_ID_7 0x9f0 | ||
| 607 | #define PERM_SRC_ID_7__SRCID 0x00ff | ||
| 608 | #define PERM_SRC_ID_7__DIRECT_ACCESS_ACTIVE 0x0800 | ||
| 609 | #define PERM_SRC_ID_7__WRITE_ACTIVE 0x2000 | ||
| 610 | #define PERM_SRC_ID_7__READ_ACTIVE 0x4000 | ||
| 611 | #define PERM_SRC_ID_7__PARTITION_VALID 0x8000 | ||
| 612 | |||
| 613 | #define MIN_BLK_ADDR_7 0xa00 | ||
| 614 | #define MIN_BLK_ADDR_7__VALUE 0xffff | ||
| 615 | |||
| 616 | #define MAX_BLK_ADDR_7 0xa10 | ||
| 617 | #define MAX_BLK_ADDR_7__VALUE 0xffff | ||
| 618 | |||
| 619 | #define MIN_MAX_BANK_7 0xa20 | ||
| 620 | #define MIN_MAX_BANK_7__MIN_VALUE 0x0003 | ||
| 621 | #define MIN_MAX_BANK_7__MAX_VALUE 0x000c | ||
| 622 | 365 | ||
| 623 | /* ffsdefs.h */ | 366 | /* ffsdefs.h */ |
| 624 | #define CLEAR 0 /*use this to clear a field instead of "fail"*/ | 367 | #define CLEAR 0 /*use this to clear a field instead of "fail"*/ |