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authorChuanxiao <chuanxiao.dong@gmail.com>2010-08-05 11:06:04 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2010-08-05 11:31:51 -0400
commit5bac3acfb82aa22c5e917063973db5482f7ff6ab (patch)
treec417a3a40f472b7b9a31adb0a692c32bdf492a32 /drivers/mtd/nand/denali.c
parentd2350c2ab51df7088d3db73a4c85ad73ded37a01 (diff)
nand/denali Clean up all white spaces in code indent
Hi, I have changed the outlook mail cliet to be linux mutt client and use my personal gmail to submit patches. Here are 5 new patches to fix nand/denali check patch errors. The other 4 patches will be sent out after this mail. Thanks for your review. >From d125ad3f57bbf517131dccad6b5933edf8c2632a Mon Sep 17 00:00:00 2001 From: Chuanxiao Dong <chuanxiao.dong@intel.com> Date: Tue, 3 Aug 2010 15:54:48 +0800 Subject: [PATCH 1/5] mtd: denali.c: clean up all whitespaces in code indent Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/nand/denali.c')
-rw-r--r--drivers/mtd/nand/denali.c337
1 files changed, 168 insertions, 169 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index ca03428b59cc..ca02838a420e 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -29,7 +29,7 @@
29 29
30MODULE_LICENSE("GPL"); 30MODULE_LICENSE("GPL");
31 31
32/* We define a module parameter that allows the user to override 32/* We define a module parameter that allows the user to override
33 * the hardware and decide what timing mode should be used. 33 * the hardware and decide what timing mode should be used.
34 */ 34 */
35#define NAND_DEFAULT_TIMINGS -1 35#define NAND_DEFAULT_TIMINGS -1
@@ -54,13 +54,13 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting. -1 indicates
54 INTR_STATUS0__RST_COMP | \ 54 INTR_STATUS0__RST_COMP | \
55 INTR_STATUS0__ERASE_COMP) 55 INTR_STATUS0__ERASE_COMP)
56 56
57/* indicates whether or not the internal value for the flash bank is 57/* indicates whether or not the internal value for the flash bank is
58 valid or not */ 58 valid or not */
59#define CHIP_SELECT_INVALID -1 59#define CHIP_SELECT_INVALID -1
60 60
61#define SUPPORT_8BITECC 1 61#define SUPPORT_8BITECC 1
62 62
63/* This macro divides two integers and rounds fractional values up 63/* This macro divides two integers and rounds fractional values up
64 * to the nearest integer value. */ 64 * to the nearest integer value. */
65#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) 65#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
66 66
@@ -83,7 +83,7 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting. -1 indicates
83#define ADDR_CYCLE 1 83#define ADDR_CYCLE 1
84#define STATUS_CYCLE 2 84#define STATUS_CYCLE 2
85 85
86/* this is a helper macro that allows us to 86/* this is a helper macro that allows us to
87 * format the bank into the proper bits for the controller */ 87 * format the bank into the proper bits for the controller */
88#define BANK(x) ((x) << 24) 88#define BANK(x) ((x) << 24)
89 89
@@ -95,28 +95,28 @@ static const struct pci_device_id denali_pci_ids[] = {
95}; 95};
96 96
97 97
98/* these are static lookup tables that give us easy access to 98/* these are static lookup tables that give us easy access to
99 registers in the NAND controller. 99 registers in the NAND controller.
100 */ 100 */
101static const uint32_t intr_status_addresses[4] = {INTR_STATUS0, 101static const uint32_t intr_status_addresses[4] = {INTR_STATUS0,
102 INTR_STATUS1, 102 INTR_STATUS1,
103 INTR_STATUS2, 103 INTR_STATUS2,
104 INTR_STATUS3}; 104 INTR_STATUS3};
105 105
106static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0, 106static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0,
107 DEVICE_RESET__BANK1, 107 DEVICE_RESET__BANK1,
108 DEVICE_RESET__BANK2, 108 DEVICE_RESET__BANK2,
109 DEVICE_RESET__BANK3}; 109 DEVICE_RESET__BANK3};
110 110
111static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT, 111static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT,
112 INTR_STATUS1__TIME_OUT, 112 INTR_STATUS1__TIME_OUT,
113 INTR_STATUS2__TIME_OUT, 113 INTR_STATUS2__TIME_OUT,
114 INTR_STATUS3__TIME_OUT}; 114 INTR_STATUS3__TIME_OUT};
115 115
116static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP, 116static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP,
117 INTR_STATUS1__RST_COMP, 117 INTR_STATUS1__RST_COMP,
118 INTR_STATUS2__RST_COMP, 118 INTR_STATUS2__RST_COMP,
119 INTR_STATUS3__RST_COMP}; 119 INTR_STATUS3__RST_COMP};
120 120
121/* specifies the debug level of the driver */ 121/* specifies the debug level of the driver */
122static int nand_debug_level = 0; 122static int nand_debug_level = 0;
@@ -131,21 +131,21 @@ static uint32_t read_interrupt_status(struct denali_nand_info *denali);
131 131
132/* This is a wrapper for writing to the denali registers. 132/* This is a wrapper for writing to the denali registers.
133 * this allows us to create debug information so we can 133 * this allows us to create debug information so we can
134 * observe how the driver is programming the device. 134 * observe how the driver is programming the device.
135 * it uses standard linux convention for (val, addr) */ 135 * it uses standard linux convention for (val, addr) */
136static void denali_write32(uint32_t value, void *addr) 136static void denali_write32(uint32_t value, void *addr)
137{ 137{
138 iowrite32(value, addr); 138 iowrite32(value, addr);
139 139
140#if DEBUG_DENALI 140#if DEBUG_DENALI
141 printk(KERN_ERR "wrote: 0x%x -> 0x%x\n", value, (uint32_t)((uint32_t)addr & 0x1fff)); 141 printk(KERN_ERR "wrote: 0x%x -> 0x%x\n", value, (uint32_t)((uint32_t)addr & 0x1fff));
142#endif 142#endif
143} 143}
144 144
145/* Certain operations for the denali NAND controller use an indexed mode to read/write 145/* Certain operations for the denali NAND controller use an indexed mode to read/write
146 data. The operation is performed by writing the address value of the command to 146 data. The operation is performed by writing the address value of the command to
147 the device memory followed by the data. This function abstracts this common 147 the device memory followed by the data. This function abstracts this common
148 operation. 148 operation.
149*/ 149*/
150static void index_addr(struct denali_nand_info *denali, uint32_t address, uint32_t data) 150static void index_addr(struct denali_nand_info *denali, uint32_t address, uint32_t data)
151{ 151{
@@ -161,7 +161,7 @@ static void index_addr_read_data(struct denali_nand_info *denali,
161 *pdata = ioread32(denali->flash_mem + 0x10); 161 *pdata = ioread32(denali->flash_mem + 0x10);
162} 162}
163 163
164/* We need to buffer some data for some of the NAND core routines. 164/* We need to buffer some data for some of the NAND core routines.
165 * The operations manage buffering that data. */ 165 * The operations manage buffering that data. */
166static void reset_buf(struct denali_nand_info *denali) 166static void reset_buf(struct denali_nand_info *denali)
167{ 167{
@@ -183,7 +183,7 @@ static void read_status(struct denali_nand_info *denali)
183 reset_buf(denali); 183 reset_buf(denali);
184 184
185 /* initiate a device status read */ 185 /* initiate a device status read */
186 cmd = MODE_11 | BANK(denali->flash_bank); 186 cmd = MODE_11 | BANK(denali->flash_bank);
187 index_addr(denali, cmd | COMMAND_CYCLE, 0x70); 187 index_addr(denali, cmd | COMMAND_CYCLE, 0x70);
188 denali_write32(cmd | STATUS_CYCLE, denali->flash_mem); 188 denali_write32(cmd | STATUS_CYCLE, denali->flash_mem);
189 189
@@ -199,7 +199,7 @@ static void read_status(struct denali_nand_info *denali)
199static void reset_bank(struct denali_nand_info *denali) 199static void reset_bank(struct denali_nand_info *denali)
200{ 200{
201 uint32_t irq_status = 0; 201 uint32_t irq_status = 0;
202 uint32_t irq_mask = reset_complete[denali->flash_bank] | 202 uint32_t irq_mask = reset_complete[denali->flash_bank] |
203 operation_timeout[denali->flash_bank]; 203 operation_timeout[denali->flash_bank];
204 int bank = 0; 204 int bank = 0;
205 205
@@ -209,7 +209,7 @@ static void reset_bank(struct denali_nand_info *denali)
209 denali_write32(bank, denali->flash_reg + DEVICE_RESET); 209 denali_write32(bank, denali->flash_reg + DEVICE_RESET);
210 210
211 irq_status = wait_for_irq(denali, irq_mask); 211 irq_status = wait_for_irq(denali, irq_mask);
212 212
213 if (irq_status & operation_timeout[denali->flash_bank]) 213 if (irq_status & operation_timeout[denali->flash_bank])
214 { 214 {
215 printk(KERN_ERR "reset bank failed.\n"); 215 printk(KERN_ERR "reset bank failed.\n");
@@ -610,7 +610,7 @@ static void get_hynix_nand_para(struct denali_nand_info *denali)
610} 610}
611 611
612/* determines how many NAND chips are connected to the controller. Note for 612/* determines how many NAND chips are connected to the controller. Note for
613 Intel CE4100 devices we don't support more than one device. 613 Intel CE4100 devices we don't support more than one device.
614 */ 614 */
615static void find_valid_banks(struct denali_nand_info *denali) 615static void find_valid_banks(struct denali_nand_info *denali)
616{ 616{
@@ -641,8 +641,8 @@ static void find_valid_banks(struct denali_nand_info *denali)
641 { 641 {
642 /* Platform limitations of the CE4100 device limit 642 /* Platform limitations of the CE4100 device limit
643 * users to a single chip solution for NAND. 643 * users to a single chip solution for NAND.
644 * Multichip support is not enabled. 644 * Multichip support is not enabled.
645 */ 645 */
646 if (denali->total_used_banks != 1) 646 if (denali->total_used_banks != 1)
647 { 647 {
648 printk(KERN_ERR "Sorry, Intel CE4100 only supports " 648 printk(KERN_ERR "Sorry, Intel CE4100 only supports "
@@ -885,7 +885,7 @@ static uint16_t NAND_Read_Device_ID(struct denali_nand_info *denali)
885 dump_device_info(denali); 885 dump_device_info(denali);
886 886
887 /* If the user specified to override the default timings 887 /* If the user specified to override the default timings
888 * with a specific ONFI mode, we apply those changes here. 888 * with a specific ONFI mode, we apply those changes here.
889 */ 889 */
890 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) 890 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
891 { 891 {
@@ -912,7 +912,7 @@ static void NAND_LLD_Enable_Disable_Interrupts(struct denali_nand_info *denali,
912 */ 912 */
913static inline bool is_flash_bank_valid(int flash_bank) 913static inline bool is_flash_bank_valid(int flash_bank)
914{ 914{
915 return (flash_bank >= 0 && flash_bank < 4); 915 return (flash_bank >= 0 && flash_bank < 4);
916} 916}
917 917
918static void denali_irq_init(struct denali_nand_info *denali) 918static void denali_irq_init(struct denali_nand_info *denali)
@@ -948,7 +948,7 @@ static void denali_irq_enable(struct denali_nand_info *denali, uint32_t int_mask
948} 948}
949 949
950/* This function only returns when an interrupt that this driver cares about 950/* This function only returns when an interrupt that this driver cares about
951 * occurs. This is to reduce the overhead of servicing interrupts 951 * occurs. This is to reduce the overhead of servicing interrupts
952 */ 952 */
953static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) 953static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
954{ 954{
@@ -1003,9 +1003,9 @@ static void print_irq_log(struct denali_nand_info *denali)
1003} 1003}
1004#endif 1004#endif
1005 1005
1006/* This is the interrupt service routine. It handles all interrupts 1006/* This is the interrupt service routine. It handles all interrupts
1007 * sent to this device. Note that on CE4100, this is a shared 1007 * sent to this device. Note that on CE4100, this is a shared
1008 * interrupt. 1008 * interrupt.
1009 */ 1009 */
1010static irqreturn_t denali_isr(int irq, void *dev_id) 1010static irqreturn_t denali_isr(int irq, void *dev_id)
1011{ 1011{
@@ -1015,12 +1015,12 @@ static irqreturn_t denali_isr(int irq, void *dev_id)
1015 1015
1016 spin_lock(&denali->irq_lock); 1016 spin_lock(&denali->irq_lock);
1017 1017
1018 /* check to see if a valid NAND chip has 1018 /* check to see if a valid NAND chip has
1019 * been selected. 1019 * been selected.
1020 */ 1020 */
1021 if (is_flash_bank_valid(denali->flash_bank)) 1021 if (is_flash_bank_valid(denali->flash_bank))
1022 { 1022 {
1023 /* check to see if controller generated 1023 /* check to see if controller generated
1024 * the interrupt, since this is a shared interrupt */ 1024 * the interrupt, since this is a shared interrupt */
1025 if ((irq_status = denali_irq_detected(denali)) != 0) 1025 if ((irq_status = denali_irq_detected(denali)) != 0)
1026 { 1026 {
@@ -1078,10 +1078,10 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
1078 /* our interrupt was detected */ 1078 /* our interrupt was detected */
1079 break; 1079 break;
1080 } 1080 }
1081 else 1081 else
1082 { 1082 {
1083 /* these are not the interrupts you are looking for - 1083 /* these are not the interrupts you are looking for -
1084 need to wait again */ 1084 * need to wait again */
1085 spin_unlock_irq(&denali->irq_lock); 1085 spin_unlock_irq(&denali->irq_lock);
1086#if DEBUG_DENALI 1086#if DEBUG_DENALI
1087 print_irq_log(denali); 1087 print_irq_log(denali);
@@ -1095,20 +1095,20 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
1095 if (comp_res == 0) 1095 if (comp_res == 0)
1096 { 1096 {
1097 /* timeout */ 1097 /* timeout */
1098 printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n", 1098 printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n",
1099 intr_status, irq_mask); 1099 intr_status, irq_mask);
1100 1100
1101 intr_status = 0; 1101 intr_status = 0;
1102 } 1102 }
1103 return intr_status; 1103 return intr_status;
1104} 1104}
1105 1105
1106/* This helper function setups the registers for ECC and whether or not 1106/* This helper function setups the registers for ECC and whether or not
1107 the spare area will be transfered. */ 1107 the spare area will be transfered. */
1108static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, 1108static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
1109 bool transfer_spare) 1109 bool transfer_spare)
1110{ 1110{
1111 int ecc_en_flag = 0, transfer_spare_flag = 0; 1111 int ecc_en_flag = 0, transfer_spare_flag = 0;
1112 1112
1113 /* set ECC, transfer spare bits if needed */ 1113 /* set ECC, transfer spare bits if needed */
1114 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; 1114 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
@@ -1119,15 +1119,15 @@ static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
1119 denali_write32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); 1119 denali_write32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
1120} 1120}
1121 1121
1122/* sends a pipeline command operation to the controller. See the Denali NAND 1122/* sends a pipeline command operation to the controller. See the Denali NAND
1123 controller's user guide for more information (section 4.2.3.6). 1123 controller's user guide for more information (section 4.2.3.6).
1124 */ 1124 */
1125static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en, 1125static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en,
1126 bool transfer_spare, int access_type, 1126 bool transfer_spare, int access_type,
1127 int op) 1127 int op)
1128{ 1128{
1129 int status = PASS; 1129 int status = PASS;
1130 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, 1130 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0,
1131 irq_mask = 0; 1131 irq_mask = 0;
1132 1132
1133 if (op == DENALI_READ) irq_mask = INTR_STATUS0__LOAD_COMP; 1133 if (op == DENALI_READ) irq_mask = INTR_STATUS0__LOAD_COMP;
@@ -1145,32 +1145,32 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en
1145 1145
1146 1146
1147 /* clear interrupts */ 1147 /* clear interrupts */
1148 clear_interrupts(denali); 1148 clear_interrupts(denali);
1149 1149
1150 addr = BANK(denali->flash_bank) | denali->page; 1150 addr = BANK(denali->flash_bank) | denali->page;
1151 1151
1152 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) 1152 if (op == DENALI_WRITE && access_type != SPARE_ACCESS)
1153 { 1153 {
1154 cmd = MODE_01 | addr; 1154 cmd = MODE_01 | addr;
1155 denali_write32(cmd, denali->flash_mem); 1155 denali_write32(cmd, denali->flash_mem);
1156 } 1156 }
1157 else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) 1157 else if (op == DENALI_WRITE && access_type == SPARE_ACCESS)
1158 { 1158 {
1159 /* read spare area */ 1159 /* read spare area */
1160 cmd = MODE_10 | addr; 1160 cmd = MODE_10 | addr;
1161 index_addr(denali, (uint32_t)cmd, access_type); 1161 index_addr(denali, (uint32_t)cmd, access_type);
1162 1162
1163 cmd = MODE_01 | addr; 1163 cmd = MODE_01 | addr;
1164 denali_write32(cmd, denali->flash_mem); 1164 denali_write32(cmd, denali->flash_mem);
1165 } 1165 }
1166 else if (op == DENALI_READ) 1166 else if (op == DENALI_READ)
1167 { 1167 {
1168 /* setup page read request for access type */ 1168 /* setup page read request for access type */
1169 cmd = MODE_10 | addr; 1169 cmd = MODE_10 | addr;
1170 index_addr(denali, (uint32_t)cmd, access_type); 1170 index_addr(denali, (uint32_t)cmd, access_type);
1171 1171
1172 /* page 33 of the NAND controller spec indicates we should not 1172 /* page 33 of the NAND controller spec indicates we should not
1173 use the pipeline commands in Spare area only mode. So we 1173 use the pipeline commands in Spare area only mode. So we
1174 don't. 1174 don't.
1175 */ 1175 */
1176 if (access_type == SPARE_ACCESS) 1176 if (access_type == SPARE_ACCESS)
@@ -1181,8 +1181,8 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en
1181 else 1181 else
1182 { 1182 {
1183 index_addr(denali, (uint32_t)cmd, 0x2000 | op | page_count); 1183 index_addr(denali, (uint32_t)cmd, 0x2000 | op | page_count);
1184 1184
1185 /* wait for command to be accepted 1185 /* wait for command to be accepted
1186 * can always use status0 bit as the mask is identical for each 1186 * can always use status0 bit as the mask is identical for each
1187 * bank. */ 1187 * bank. */
1188 irq_status = wait_for_irq(denali, irq_mask); 1188 irq_status = wait_for_irq(denali, irq_mask);
@@ -1204,13 +1204,13 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en
1204} 1204}
1205 1205
1206/* helper function that simply writes a buffer to the flash */ 1206/* helper function that simply writes a buffer to the flash */
1207static int write_data_to_flash_mem(struct denali_nand_info *denali, const uint8_t *buf, 1207static int write_data_to_flash_mem(struct denali_nand_info *denali, const uint8_t *buf,
1208 int len) 1208 int len)
1209{ 1209{
1210 uint32_t i = 0, *buf32; 1210 uint32_t i = 0, *buf32;
1211 1211
1212 /* verify that the len is a multiple of 4. see comment in 1212 /* verify that the len is a multiple of 4. see comment in
1213 * read_data_from_flash_mem() */ 1213 * read_data_from_flash_mem() */
1214 BUG_ON((len % 4) != 0); 1214 BUG_ON((len % 4) != 0);
1215 1215
1216 /* write the data to the flash memory */ 1216 /* write the data to the flash memory */
@@ -1219,21 +1219,20 @@ static int write_data_to_flash_mem(struct denali_nand_info *denali, const uint8_
1219 { 1219 {
1220 denali_write32(*buf32++, denali->flash_mem + 0x10); 1220 denali_write32(*buf32++, denali->flash_mem + 0x10);
1221 } 1221 }
1222 return i*4; /* intent is to return the number of bytes read */ 1222 return i*4; /* intent is to return the number of bytes read */
1223} 1223}
1224 1224
1225/* helper function that simply reads a buffer from the flash */ 1225/* helper function that simply reads a buffer from the flash */
1226static int read_data_from_flash_mem(struct denali_nand_info *denali, uint8_t *buf, 1226static int read_data_from_flash_mem(struct denali_nand_info *denali, uint8_t *buf,
1227 int len) 1227 int len)
1228{ 1228{
1229 uint32_t i = 0, *buf32; 1229 uint32_t i = 0, *buf32;
1230 1230
1231 /* we assume that len will be a multiple of 4, if not 1231 /* we assume that len will be a multiple of 4, if not
1232 * it would be nice to know about it ASAP rather than 1232 * it would be nice to know about it ASAP rather than
1233 * have random failures... 1233 * have random failures...
1234 * 1234 * This assumption is based on the fact that this
1235 * This assumption is based on the fact that this 1235 * function is designed to be used to read flash pages,
1236 * function is designed to be used to read flash pages,
1237 * which are typically multiples of 4... 1236 * which are typically multiples of 4...
1238 */ 1237 */
1239 1238
@@ -1245,7 +1244,7 @@ static int read_data_from_flash_mem(struct denali_nand_info *denali, uint8_t *bu
1245 { 1244 {
1246 *buf32++ = ioread32(denali->flash_mem + 0x10); 1245 *buf32++ = ioread32(denali->flash_mem + 0x10);
1247 } 1246 }
1248 return i*4; /* intent is to return the number of bytes read */ 1247 return i*4; /* intent is to return the number of bytes read */
1249} 1248}
1250 1249
1251/* writes OOB data to the device */ 1250/* writes OOB data to the device */
@@ -1253,14 +1252,14 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1253{ 1252{
1254 struct denali_nand_info *denali = mtd_to_denali(mtd); 1253 struct denali_nand_info *denali = mtd_to_denali(mtd);
1255 uint32_t irq_status = 0; 1254 uint32_t irq_status = 0;
1256 uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP | 1255 uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP |
1257 INTR_STATUS0__PROGRAM_FAIL; 1256 INTR_STATUS0__PROGRAM_FAIL;
1258 int status = 0; 1257 int status = 0;
1259 1258
1260 denali->page = page; 1259 denali->page = page;
1261 1260
1262 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, 1261 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
1263 DENALI_WRITE) == PASS) 1262 DENALI_WRITE) == PASS)
1264 { 1263 {
1265 write_data_to_flash_mem(denali, buf, mtd->oobsize); 1264 write_data_to_flash_mem(denali, buf, mtd->oobsize);
1266 1265
@@ -1271,7 +1270,7 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1271 spin_unlock_irq(&denali->irq_lock); 1270 spin_unlock_irq(&denali->irq_lock);
1272#endif 1271#endif
1273 1272
1274 1273
1275 /* wait for operation to complete */ 1274 /* wait for operation to complete */
1276 irq_status = wait_for_irq(denali, irq_mask); 1275 irq_status = wait_for_irq(denali, irq_mask);
1277 1276
@@ -1281,10 +1280,10 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1281 status = -EIO; 1280 status = -EIO;
1282 } 1281 }
1283 } 1282 }
1284 else 1283 else
1285 { 1284 {
1286 printk(KERN_ERR "unable to send pipeline command\n"); 1285 printk(KERN_ERR "unable to send pipeline command\n");
1287 status = -EIO; 1286 status = -EIO;
1288 } 1287 }
1289 return status; 1288 return status;
1290} 1289}
@@ -1300,12 +1299,12 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1300#if DEBUG_DENALI 1299#if DEBUG_DENALI
1301 printk("read_oob %d\n", page); 1300 printk("read_oob %d\n", page);
1302#endif 1301#endif
1303 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, 1302 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
1304 DENALI_READ) == PASS) 1303 DENALI_READ) == PASS)
1305 { 1304 {
1306 read_data_from_flash_mem(denali, buf, mtd->oobsize); 1305 read_data_from_flash_mem(denali, buf, mtd->oobsize);
1307 1306
1308 /* wait for command to be accepted 1307 /* wait for command to be accepted
1309 * can always use status0 bit as the mask is identical for each 1308 * can always use status0 bit as the mask is identical for each
1310 * bank. */ 1309 * bank. */
1311 irq_status = wait_for_irq(denali, irq_mask); 1310 irq_status = wait_for_irq(denali, irq_mask);
@@ -1319,10 +1318,10 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1319 * instability with the controller if you do a block erase 1318 * instability with the controller if you do a block erase
1320 * and the last transaction was a SPARE_ACCESS. Block erase 1319 * and the last transaction was a SPARE_ACCESS. Block erase
1321 * is reliable (according to the MTD test infrastructure) 1320 * is reliable (according to the MTD test infrastructure)
1322 * if you are in MAIN_ACCESS. 1321 * if you are in MAIN_ACCESS.
1323 */ 1322 */
1324 addr = BANK(denali->flash_bank) | denali->page; 1323 addr = BANK(denali->flash_bank) | denali->page;
1325 cmd = MODE_10 | addr; 1324 cmd = MODE_10 | addr;
1326 index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); 1325 index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
1327 1326
1328#if DEBUG_DENALI 1327#if DEBUG_DENALI
@@ -1334,14 +1333,14 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1334 } 1333 }
1335} 1334}
1336 1335
1337/* this function examines buffers to see if they contain data that 1336/* this function examines buffers to see if they contain data that
1338 * indicate that the buffer is part of an erased region of flash. 1337 * indicate that the buffer is part of an erased region of flash.
1339 */ 1338 */
1340bool is_erased(uint8_t *buf, int len) 1339bool is_erased(uint8_t *buf, int len)
1341{ 1340{
1342 int i = 0; 1341 int i = 0;
1343 for (i = 0; i < len; i++) 1342 for (i = 0; i < len; i++)
1344 { 1343 {
1345 if (buf[i] != 0xFF) 1344 if (buf[i] != 0xFF)
1346 { 1345 {
1347 return false; 1346 return false;
@@ -1358,7 +1357,7 @@ bool is_erased(uint8_t *buf, int len)
1358#define ECC_ERR_DEVICE(x) ((x) & ERR_CORRECTION_INFO__DEVICE_NR >> 8) 1357#define ECC_ERR_DEVICE(x) ((x) & ERR_CORRECTION_INFO__DEVICE_NR >> 8)
1359#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) 1358#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
1360 1359
1361static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, 1360static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
1362 uint8_t *oobbuf, uint32_t irq_status) 1361 uint8_t *oobbuf, uint32_t irq_status)
1363{ 1362{
1364 bool check_erased_page = false; 1363 bool check_erased_page = false;
@@ -1370,27 +1369,27 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
1370 uint32_t err_byte = 0, err_sector = 0, err_device = 0; 1369 uint32_t err_byte = 0, err_sector = 0, err_device = 0;
1371 uint32_t err_correction_value = 0; 1370 uint32_t err_correction_value = 0;
1372 1371
1373 do 1372 do
1374 { 1373 {
1375 err_address = ioread32(denali->flash_reg + 1374 err_address = ioread32(denali->flash_reg +
1376 ECC_ERROR_ADDRESS); 1375 ECC_ERROR_ADDRESS);
1377 err_sector = ECC_SECTOR(err_address); 1376 err_sector = ECC_SECTOR(err_address);
1378 err_byte = ECC_BYTE(err_address); 1377 err_byte = ECC_BYTE(err_address);
1379 1378
1380 1379
1381 err_correction_info = ioread32(denali->flash_reg + 1380 err_correction_info = ioread32(denali->flash_reg +
1382 ERR_CORRECTION_INFO); 1381 ERR_CORRECTION_INFO);
1383 err_correction_value = 1382 err_correction_value =
1384 ECC_CORRECTION_VALUE(err_correction_info); 1383 ECC_CORRECTION_VALUE(err_correction_info);
1385 err_device = ECC_ERR_DEVICE(err_correction_info); 1384 err_device = ECC_ERR_DEVICE(err_correction_info);
1386 1385
1387 if (ECC_ERROR_CORRECTABLE(err_correction_info)) 1386 if (ECC_ERROR_CORRECTABLE(err_correction_info))
1388 { 1387 {
1389 /* offset in our buffer is computed as: 1388 /* offset in our buffer is computed as:
1390 sector number * sector size + offset in 1389 sector number * sector size + offset in
1391 sector 1390 sector
1392 */ 1391 */
1393 int offset = err_sector * ECC_SECTOR_SIZE + 1392 int offset = err_sector * ECC_SECTOR_SIZE +
1394 err_byte; 1393 err_byte;
1395 if (offset < denali->mtd.writesize) 1394 if (offset < denali->mtd.writesize)
1396 { 1395 {
@@ -1407,15 +1406,15 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
1407 } 1406 }
1408 else 1407 else
1409 { 1408 {
1410 /* if the error is not correctable, need to 1409 /* if the error is not correctable, need to
1411 * look at the page to see if it is an erased page. 1410 * look at the page to see if it is an erased page.
1412 * if so, then it's not a real ECC error */ 1411 * if so, then it's not a real ECC error */
1413 check_erased_page = true; 1412 check_erased_page = true;
1414 } 1413 }
1415 1414
1416#if DEBUG_DENALI 1415#if DEBUG_DENALI
1417 printk("Detected ECC error in page %d: err_addr = 0x%08x," 1416 printk("Detected ECC error in page %d: err_addr = 0x%08x,"
1418 " info to fix is 0x%08x\n", denali->page, err_address, 1417 " info to fix is 0x%08x\n", denali->page, err_address,
1419 err_correction_info); 1418 err_correction_info);
1420#endif 1419#endif
1421 } while (!ECC_LAST_ERR(err_correction_info)); 1420 } while (!ECC_LAST_ERR(err_correction_info));
@@ -1458,9 +1457,9 @@ static void denali_setup_dma(struct denali_nand_info *denali, int op)
1458 index_addr(denali, mode | 0x14000, 0x2400); 1457 index_addr(denali, mode | 0x14000, 0x2400);
1459} 1458}
1460 1459
1461/* writes a page. user specifies type, and this function handles the 1460/* writes a page. user specifies type, and this function handles the
1462 configuration details. */ 1461 configuration details. */
1463static void write_page(struct mtd_info *mtd, struct nand_chip *chip, 1462static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1464 const uint8_t *buf, bool raw_xfer) 1463 const uint8_t *buf, bool raw_xfer)
1465{ 1464{
1466 struct denali_nand_info *denali = mtd_to_denali(mtd); 1465 struct denali_nand_info *denali = mtd_to_denali(mtd);
@@ -1470,7 +1469,7 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1470 size_t size = denali->mtd.writesize + denali->mtd.oobsize; 1469 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1471 1470
1472 uint32_t irq_status = 0; 1471 uint32_t irq_status = 0;
1473 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP | 1472 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP |
1474 INTR_STATUS0__PROGRAM_FAIL; 1473 INTR_STATUS0__PROGRAM_FAIL;
1475 1474
1476 /* if it is a raw xfer, we want to disable ecc, and send 1475 /* if it is a raw xfer, we want to disable ecc, and send
@@ -1486,15 +1485,15 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1486 if (raw_xfer) 1485 if (raw_xfer)
1487 { 1486 {
1488 /* transfer the data to the spare area */ 1487 /* transfer the data to the spare area */
1489 memcpy(denali->buf.buf + mtd->writesize, 1488 memcpy(denali->buf.buf + mtd->writesize,
1490 chip->oob_poi, 1489 chip->oob_poi,
1491 mtd->oobsize); 1490 mtd->oobsize);
1492 } 1491 }
1493 1492
1494 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE); 1493 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE);
1495 1494
1496 clear_interrupts(denali); 1495 clear_interrupts(denali);
1497 denali_enable_dma(denali, true); 1496 denali_enable_dma(denali, true);
1498 1497
1499 denali_setup_dma(denali, DENALI_WRITE); 1498 denali_setup_dma(denali, DENALI_WRITE);
1500 1499
@@ -1504,53 +1503,53 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1504 if (irq_status == 0) 1503 if (irq_status == 0)
1505 { 1504 {
1506 printk(KERN_ERR "timeout on write_page (type = %d)\n", raw_xfer); 1505 printk(KERN_ERR "timeout on write_page (type = %d)\n", raw_xfer);
1507 denali->status = 1506 denali->status =
1508 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ? NAND_STATUS_FAIL : 1507 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ? NAND_STATUS_FAIL :
1509 PASS; 1508 PASS;
1510 } 1509 }
1511 1510
1512 denali_enable_dma(denali, false); 1511 denali_enable_dma(denali, false);
1513 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE); 1512 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE);
1514} 1513}
1515 1514
1516/* NAND core entry points */ 1515/* NAND core entry points */
1517 1516
1518/* this is the callback that the NAND core calls to write a page. Since 1517/* this is the callback that the NAND core calls to write a page. Since
1519 writing a page with ECC or without is similar, all the work is done 1518 writing a page with ECC or without is similar, all the work is done
1520 by write_page above. */ 1519 by write_page above. */
1521static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, 1520static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1522 const uint8_t *buf) 1521 const uint8_t *buf)
1523{ 1522{
1524 /* for regular page writes, we let HW handle all the ECC 1523 /* for regular page writes, we let HW handle all the ECC
1525 * data written to the device. */ 1524 * data written to the device. */
1526 write_page(mtd, chip, buf, false); 1525 write_page(mtd, chip, buf, false);
1527} 1526}
1528 1527
1529/* This is the callback that the NAND core calls to write a page without ECC. 1528/* This is the callback that the NAND core calls to write a page without ECC.
1530 raw access is similiar to ECC page writes, so all the work is done in the 1529 raw access is similiar to ECC page writes, so all the work is done in the
1531 write_page() function above. 1530 write_page() function above.
1532 */ 1531 */
1533static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1532static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1534 const uint8_t *buf) 1533 const uint8_t *buf)
1535{ 1534{
1536 /* for raw page writes, we want to disable ECC and simply write 1535 /* for raw page writes, we want to disable ECC and simply write
1537 whatever data is in the buffer. */ 1536 whatever data is in the buffer. */
1538 write_page(mtd, chip, buf, true); 1537 write_page(mtd, chip, buf, true);
1539} 1538}
1540 1539
1541static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 1540static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1542 int page) 1541 int page)
1543{ 1542{
1544 return write_oob_data(mtd, chip->oob_poi, page); 1543 return write_oob_data(mtd, chip->oob_poi, page);
1545} 1544}
1546 1545
1547static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 1546static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1548 int page, int sndcmd) 1547 int page, int sndcmd)
1549{ 1548{
1550 read_oob_data(mtd, chip->oob_poi, page); 1549 read_oob_data(mtd, chip->oob_poi, page);
1551 1550
1552 return 0; /* notify NAND core to send command to 1551 return 0; /* notify NAND core to send command to
1553 * NAND device. */ 1552 NAND device. */
1554} 1553}
1555 1554
1556static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, 1555static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
@@ -1563,7 +1562,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1563 size_t size = denali->mtd.writesize + denali->mtd.oobsize; 1562 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1564 1563
1565 uint32_t irq_status = 0; 1564 uint32_t irq_status = 0;
1566 uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE | 1565 uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE |
1567 INTR_STATUS0__ECC_ERR; 1566 INTR_STATUS0__ECC_ERR;
1568 bool check_erased_page = false; 1567 bool check_erased_page = false;
1569 1568
@@ -1581,7 +1580,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1581 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE); 1580 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1582 1581
1583 memcpy(buf, denali->buf.buf, mtd->writesize); 1582 memcpy(buf, denali->buf.buf, mtd->writesize);
1584 1583
1585 check_erased_page = handle_ecc(denali, buf, chip->oob_poi, irq_status); 1584 check_erased_page = handle_ecc(denali, buf, chip->oob_poi, irq_status);
1586 denali_enable_dma(denali, false); 1585 denali_enable_dma(denali, false);
1587 1586
@@ -1600,7 +1599,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1600 { 1599 {
1601 denali->mtd.ecc_stats.failed++; 1600 denali->mtd.ecc_stats.failed++;
1602 } 1601 }
1603 } 1602 }
1604 } 1603 }
1605 return 0; 1604 return 0;
1606} 1605}
@@ -1616,7 +1615,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1616 1615
1617 uint32_t irq_status = 0; 1616 uint32_t irq_status = 0;
1618 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP; 1617 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP;
1619 1618
1620 setup_ecc_for_xfer(denali, false, true); 1619 setup_ecc_for_xfer(denali, false, true);
1621 denali_enable_dma(denali, true); 1620 denali_enable_dma(denali, true);
1622 1621
@@ -1687,21 +1686,21 @@ static void denali_erase(struct mtd_info *mtd, int page)
1687 printk("erase page: %d\n", page); 1686 printk("erase page: %d\n", page);
1688#endif 1687#endif
1689 /* clear interrupts */ 1688 /* clear interrupts */
1690 clear_interrupts(denali); 1689 clear_interrupts(denali);
1691 1690
1692 /* setup page read request for access type */ 1691 /* setup page read request for access type */
1693 cmd = MODE_10 | BANK(denali->flash_bank) | page; 1692 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1694 index_addr(denali, (uint32_t)cmd, 0x1); 1693 index_addr(denali, (uint32_t)cmd, 0x1);
1695 1694
1696 /* wait for erase to complete or failure to occur */ 1695 /* wait for erase to complete or failure to occur */
1697 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP | 1696 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP |
1698 INTR_STATUS0__ERASE_FAIL); 1697 INTR_STATUS0__ERASE_FAIL);
1699 1698
1700 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ? NAND_STATUS_FAIL : 1699 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ? NAND_STATUS_FAIL :
1701 PASS; 1700 PASS;
1702} 1701}
1703 1702
1704static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, 1703static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1705 int page) 1704 int page)
1706{ 1705{
1707 struct denali_nand_info *denali = mtd_to_denali(mtd); 1706 struct denali_nand_info *denali = mtd_to_denali(mtd);
@@ -1710,7 +1709,7 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1710 printk("cmdfunc: 0x%x %d %d\n", cmd, col, page); 1709 printk("cmdfunc: 0x%x %d %d\n", cmd, col, page);
1711#endif 1710#endif
1712 switch (cmd) 1711 switch (cmd)
1713 { 1712 {
1714 case NAND_CMD_PAGEPROG: 1713 case NAND_CMD_PAGEPROG:
1715 break; 1714 break;
1716 case NAND_CMD_STATUS: 1715 case NAND_CMD_STATUS:
@@ -1720,19 +1719,19 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1720 reset_buf(denali); 1719 reset_buf(denali);
1721 if (denali->flash_bank < denali->total_used_banks) 1720 if (denali->flash_bank < denali->total_used_banks)
1722 { 1721 {
1723 /* write manufacturer information into nand 1722 /* write manufacturer information into nand
1724 buffer for NAND subsystem to fetch. 1723 buffer for NAND subsystem to fetch.
1725 */ 1724 */
1726 write_byte_to_buf(denali, denali->dev_info.wDeviceMaker); 1725 write_byte_to_buf(denali, denali->dev_info.wDeviceMaker);
1727 write_byte_to_buf(denali, denali->dev_info.wDeviceID); 1726 write_byte_to_buf(denali, denali->dev_info.wDeviceID);
1728 write_byte_to_buf(denali, denali->dev_info.bDeviceParam0); 1727 write_byte_to_buf(denali, denali->dev_info.bDeviceParam0);
1729 write_byte_to_buf(denali, denali->dev_info.bDeviceParam1); 1728 write_byte_to_buf(denali, denali->dev_info.bDeviceParam1);
1730 write_byte_to_buf(denali, denali->dev_info.bDeviceParam2); 1729 write_byte_to_buf(denali, denali->dev_info.bDeviceParam2);
1731 } 1730 }
1732 else 1731 else
1733 { 1732 {
1734 int i; 1733 int i;
1735 for (i = 0; i < 5; i++) 1734 for (i = 0; i < 5; i++)
1736 write_byte_to_buf(denali, 0xff); 1735 write_byte_to_buf(denali, 0xff);
1737 } 1736 }
1738 break; 1737 break;
@@ -1753,7 +1752,7 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1753} 1752}
1754 1753
1755/* stubs for ECC functions not used by the NAND core */ 1754/* stubs for ECC functions not used by the NAND core */
1756static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, 1755static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1757 uint8_t *ecc_code) 1756 uint8_t *ecc_code)
1758{ 1757{
1759 printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n"); 1758 printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n");
@@ -1761,7 +1760,7 @@ static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1761 return -EIO; 1760 return -EIO;
1762} 1761}
1763 1762
1764static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, 1763static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
1765 uint8_t *read_ecc, uint8_t *calc_ecc) 1764 uint8_t *read_ecc, uint8_t *calc_ecc)
1766{ 1765{
1767 printk(KERN_ERR "denali_ecc_correct called unexpectedly\n"); 1766 printk(KERN_ERR "denali_ecc_correct called unexpectedly\n");
@@ -1797,9 +1796,9 @@ static void denali_hw_init(struct denali_nand_info *denali)
1797static struct nand_ecclayout nand_oob_slc = { 1796static struct nand_ecclayout nand_oob_slc = {
1798 .eccbytes = 4, 1797 .eccbytes = 4,
1799 .eccpos = { 0, 1, 2, 3 }, /* not used */ 1798 .eccpos = { 0, 1, 2, 3 }, /* not used */
1800 .oobfree = {{ 1799 .oobfree = {{
1801 .offset = ECC_BYTES_SLC, 1800 .offset = ECC_BYTES_SLC,
1802 .length = 64 - ECC_BYTES_SLC 1801 .length = 64 - ECC_BYTES_SLC
1803 }} 1802 }}
1804}; 1803};
1805 1804
@@ -1807,9 +1806,9 @@ static struct nand_ecclayout nand_oob_slc = {
1807static struct nand_ecclayout nand_oob_mlc_14bit = { 1806static struct nand_ecclayout nand_oob_mlc_14bit = {
1808 .eccbytes = 14, 1807 .eccbytes = 14,
1809 .eccpos = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13 }, /* not used */ 1808 .eccpos = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13 }, /* not used */
1810 .oobfree = {{ 1809 .oobfree = {{
1811 .offset = ECC_BYTES_MLC, 1810 .offset = ECC_BYTES_MLC,
1812 .length = 64 - ECC_BYTES_MLC 1811 .length = 64 - ECC_BYTES_MLC
1813 }} 1812 }}
1814}; 1813};
1815 1814
@@ -1842,12 +1841,12 @@ void denali_drv_init(struct denali_nand_info *denali)
1842 denali->idx = 0; 1841 denali->idx = 0;
1843 1842
1844 /* setup interrupt handler */ 1843 /* setup interrupt handler */
1845 /* the completion object will be used to notify 1844 /* the completion object will be used to notify
1846 * the callee that the interrupt is done */ 1845 * the callee that the interrupt is done */
1847 init_completion(&denali->complete); 1846 init_completion(&denali->complete);
1848 1847
1849 /* the spinlock will be used to synchronize the ISR 1848 /* the spinlock will be used to synchronize the ISR
1850 * with any element that might be access shared 1849 * with any element that might be access shared
1851 * data (interrupt status) */ 1850 * data (interrupt status) */
1852 spin_lock_init(&denali->irq_lock); 1851 spin_lock_init(&denali->irq_lock);
1853 1852
@@ -1880,9 +1879,9 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1880 } 1879 }
1881 1880
1882 if (id->driver_data == INTEL_CE4100) { 1881 if (id->driver_data == INTEL_CE4100) {
1883 /* Due to a silicon limitation, we can only support 1882 /* Due to a silicon limitation, we can only support
1884 * ONFI timing mode 1 and below. 1883 * ONFI timing mode 1 and below.
1885 */ 1884 */
1886 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) 1885 if (onfi_timing_mode < -1 || onfi_timing_mode > 1)
1887 { 1886 {
1888 printk("Intel CE4100 only supports ONFI timing mode 1 " 1887 printk("Intel CE4100 only supports ONFI timing mode 1 "
@@ -1918,7 +1917,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1918 printk(KERN_ERR "Spectra: no usable DMA configuration\n"); 1917 printk(KERN_ERR "Spectra: no usable DMA configuration\n");
1919 goto failed_enable; 1918 goto failed_enable;
1920 } 1919 }
1921 denali->buf.dma_buf = pci_map_single(dev, denali->buf.buf, DENALI_BUF_SIZE, 1920 denali->buf.dma_buf = pci_map_single(dev, denali->buf.buf, DENALI_BUF_SIZE,
1922 PCI_DMA_BIDIRECTIONAL); 1921 PCI_DMA_BIDIRECTIONAL);
1923 1922
1924 if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) 1923 if (pci_dma_mapping_error(dev, denali->buf.dma_buf))
@@ -1976,8 +1975,8 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1976 1975
1977 NAND_Read_Device_ID(denali); 1976 NAND_Read_Device_ID(denali);
1978 1977
1979 /* MTD supported page sizes vary by kernel. We validate our 1978 /* MTD supported page sizes vary by kernel. We validate our
1980 kernel supports the device here. 1979 * kernel supports the device here.
1981 */ 1980 */
1982 if (denali->dev_info.wPageSize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) 1981 if (denali->dev_info.wPageSize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
1983 { 1982 {
@@ -2009,18 +2008,18 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
2009 denali->nand.read_byte = denali_read_byte; 2008 denali->nand.read_byte = denali_read_byte;
2010 denali->nand.waitfunc = denali_waitfunc; 2009 denali->nand.waitfunc = denali_waitfunc;
2011 2010
2012 /* scan for NAND devices attached to the controller 2011 /* scan for NAND devices attached to the controller
2013 * this is the first stage in a two step process to register 2012 * this is the first stage in a two step process to register
2014 * with the nand subsystem */ 2013 * with the nand subsystem */
2015 if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) 2014 if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL))
2016 { 2015 {
2017 ret = -ENXIO; 2016 ret = -ENXIO;
2018 goto failed_nand; 2017 goto failed_nand;
2019 } 2018 }
2020 2019
2021 /* second stage of the NAND scan 2020 /* second stage of the NAND scan
2022 * this stage requires information regarding ECC and 2021 * this stage requires information regarding ECC and
2023 * bad block management. */ 2022 * bad block management. */
2024 2023
2025 /* Bad block management */ 2024 /* Bad block management */
2026 denali->nand.bbt_td = &bbt_main_descr; 2025 denali->nand.bbt_td = &bbt_main_descr;
@@ -2041,9 +2040,9 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
2041 denali->nand.ecc.bytes = ECC_BYTES_SLC; 2040 denali->nand.ecc.bytes = ECC_BYTES_SLC;
2042 } 2041 }
2043 2042
2044 /* These functions are required by the NAND core framework, otherwise, 2043 /* These functions are required by the NAND core framework, otherwise,
2045 the NAND core will assert. However, we don't need them, so we'll stub 2044 * the NAND core will assert. However, we don't need them, so we'll stub
2046 them out. */ 2045 * them out. */
2047 denali->nand.ecc.calculate = denali_ecc_calculate; 2046 denali->nand.ecc.calculate = denali_ecc_calculate;
2048 denali->nand.ecc.correct = denali_ecc_correct; 2047 denali->nand.ecc.correct = denali_ecc_correct;
2049 denali->nand.ecc.hwctl = denali_ecc_hwctl; 2048 denali->nand.ecc.hwctl = denali_ecc_hwctl;
@@ -2079,7 +2078,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
2079 failed_remap_csr: 2078 failed_remap_csr:
2080 pci_release_regions(dev); 2079 pci_release_regions(dev);
2081 failed_req_csr: 2080 failed_req_csr:
2082 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, 2081 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
2083 PCI_DMA_BIDIRECTIONAL); 2082 PCI_DMA_BIDIRECTIONAL);
2084 failed_enable: 2083 failed_enable:
2085 kfree(denali); 2084 kfree(denali);
@@ -2103,7 +2102,7 @@ static void denali_pci_remove(struct pci_dev *dev)
2103 iounmap(denali->flash_mem); 2102 iounmap(denali->flash_mem);
2104 pci_release_regions(dev); 2103 pci_release_regions(dev);
2105 pci_disable_device(dev); 2104 pci_disable_device(dev);
2106 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, 2105 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
2107 PCI_DMA_BIDIRECTIONAL); 2106 PCI_DMA_BIDIRECTIONAL);
2108 pci_set_drvdata(dev, NULL); 2107 pci_set_drvdata(dev, NULL);
2109 kfree(denali); 2108 kfree(denali);