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authorThomas Gleixner <tglx@cruncher.tec.linutronix.de>2006-05-23 17:25:53 -0400
committerThomas Gleixner <tglx@cruncher.tec.linutronix.de>2006-05-23 17:25:53 -0400
commit7abd3ef9875eb2afcdcd4f450680298a2983a55e (patch)
tree64c19d2e5ecca182938acfcb8a172efb7d907d85 /drivers/mtd/nand/cs553x_nand.c
parent3821720d51b5f304d2c33021a82c8da70f6d6ac9 (diff)
[MTD] Refactor NAND hwcontrol to cmd_ctrl
The hwcontrol function enforced a step by step state machine for any kind of hardware chip access. Let the hardware driver know which control bits are set and inform it about a change of the control lines. Let the hardware driver write out the command and address bytes directly. This gives a peformance advantage for address bus controlled chips and simplifies the quirks in the hardware drivers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/mtd/nand/cs553x_nand.c')
-rw-r--r--drivers/mtd/nand/cs553x_nand.c32
1 files changed, 8 insertions, 24 deletions
diff --git a/drivers/mtd/nand/cs553x_nand.c b/drivers/mtd/nand/cs553x_nand.c
index 064f3feadf53..cd3d7eb132f9 100644
--- a/drivers/mtd/nand/cs553x_nand.c
+++ b/drivers/mtd/nand/cs553x_nand.c
@@ -131,33 +131,17 @@ static void cs553x_write_byte(struct mtd_info *mtd, u_char byte)
131 writeb(byte, this->IO_ADDR_W + 0x801); 131 writeb(byte, this->IO_ADDR_W + 0x801);
132} 132}
133 133
134static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd) 134static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd,
135 unsigned int ctrl)
135{ 136{
136 struct nand_chip *this = mtd->priv; 137 struct nand_chip *this = mtd->priv;
137 void __iomem *mmio_base = this->IO_ADDR_R; 138 void __iomem *mmio_base = this->IO_ADDR_R;
138 unsigned char ctl; 139 if (ctrl & NAND_CTRL_CHANGE) {
139 140 unsigned char ctl = (ctrl & ~NAND_CTRL_CHANGE ) ^ 0x01;
140 switch (cmd) { 141 writeb(ctl, mmio_base + MM_NAND_CTL);
141 case NAND_CTL_SETCLE:
142 ctl = CS_NAND_CTL_CLE;
143 break;
144
145 case NAND_CTL_CLRCLE:
146 case NAND_CTL_CLRALE:
147 case NAND_CTL_SETNCE:
148 ctl = 0;
149 break;
150
151 case NAND_CTL_SETALE:
152 ctl = CS_NAND_CTL_ALE;
153 break;
154
155 default:
156 case NAND_CTL_CLRNCE:
157 ctl = CS_NAND_CTL_CE;
158 break;
159 } 142 }
160 writeb(ctl, mmio_base + MM_NAND_CTL); 143 if (cmd != NAND_CMD_NONE)
144 cs553x_write_byte(mtd, cmd);
161} 145}
162 146
163static int cs553x_device_ready(struct mtd_info *mtd) 147static int cs553x_device_ready(struct mtd_info *mtd)
@@ -233,7 +217,7 @@ static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
233 goto out_mtd; 217 goto out_mtd;
234 } 218 }
235 219
236 this->hwcontrol = cs553x_hwcontrol; 220 this->cmd_ctrl = cs553x_hwcontrol;
237 this->dev_ready = cs553x_device_ready; 221 this->dev_ready = cs553x_device_ready;
238 this->read_byte = cs553x_read_byte; 222 this->read_byte = cs553x_read_byte;
239 this->write_byte = cs553x_write_byte; 223 this->write_byte = cs553x_write_byte;