diff options
author | Thomas Gleixner <tglx@cruncher.tec.linutronix.de> | 2006-05-23 17:25:53 -0400 |
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committer | Thomas Gleixner <tglx@cruncher.tec.linutronix.de> | 2006-05-23 17:25:53 -0400 |
commit | 7abd3ef9875eb2afcdcd4f450680298a2983a55e (patch) | |
tree | 64c19d2e5ecca182938acfcb8a172efb7d907d85 /drivers/mtd/nand/ams-delta.c | |
parent | 3821720d51b5f304d2c33021a82c8da70f6d6ac9 (diff) |
[MTD] Refactor NAND hwcontrol to cmd_ctrl
The hwcontrol function enforced a step by step state machine
for any kind of hardware chip access. Let the hardware driver
know which control bits are set and inform it about a change
of the control lines. Let the hardware driver write out the
command and address bytes directly. This gives a peformance
advantage for address bus controlled chips and simplifies the
quirks in the hardware drivers.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/mtd/nand/ams-delta.c')
-rw-r--r-- | drivers/mtd/nand/ams-delta.c | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c index aeaf2dece095..c0e96860686e 100644 --- a/drivers/mtd/nand/ams-delta.c +++ b/drivers/mtd/nand/ams-delta.c | |||
@@ -34,13 +34,6 @@ static struct mtd_info *ams_delta_mtd = NULL; | |||
34 | 34 | ||
35 | #define NAND_MASK (AMS_DELTA_LATCH2_NAND_NRE | AMS_DELTA_LATCH2_NAND_NWE | AMS_DELTA_LATCH2_NAND_CLE | AMS_DELTA_LATCH2_NAND_ALE | AMS_DELTA_LATCH2_NAND_NCE | AMS_DELTA_LATCH2_NAND_NWP) | 35 | #define NAND_MASK (AMS_DELTA_LATCH2_NAND_NRE | AMS_DELTA_LATCH2_NAND_NWE | AMS_DELTA_LATCH2_NAND_CLE | AMS_DELTA_LATCH2_NAND_ALE | AMS_DELTA_LATCH2_NAND_NCE | AMS_DELTA_LATCH2_NAND_NWP) |
36 | 36 | ||
37 | #define T_NAND_CTL_CLRALE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_ALE, 0) | ||
38 | #define T_NAND_CTL_SETALE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_ALE, AMS_DELTA_LATCH2_NAND_ALE) | ||
39 | #define T_NAND_CTL_CLRCLE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_CLE, 0) | ||
40 | #define T_NAND_CTL_SETCLE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_CLE, AMS_DELTA_LATCH2_NAND_CLE) | ||
41 | #define T_NAND_CTL_SETNCE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NCE, 0) | ||
42 | #define T_NAND_CTL_CLRNCE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NCE, AMS_DELTA_LATCH2_NAND_NCE) | ||
43 | |||
44 | /* | 37 | /* |
45 | * Define partitions for flash devices | 38 | * Define partitions for flash devices |
46 | */ | 39 | */ |
@@ -66,25 +59,6 @@ static struct mtd_partition partition_info[] = { | |||
66 | .size = 3 * SZ_256K }, | 59 | .size = 3 * SZ_256K }, |
67 | }; | 60 | }; |
68 | 61 | ||
69 | /* | ||
70 | * hardware specific access to control-lines | ||
71 | */ | ||
72 | |||
73 | static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd) | ||
74 | { | ||
75 | switch (cmd) { | ||
76 | |||
77 | case NAND_CTL_SETCLE: T_NAND_CTL_SETCLE(cmd); break; | ||
78 | case NAND_CTL_CLRCLE: T_NAND_CTL_CLRCLE(cmd); break; | ||
79 | |||
80 | case NAND_CTL_SETALE: T_NAND_CTL_SETALE(cmd); break; | ||
81 | case NAND_CTL_CLRALE: T_NAND_CTL_CLRALE(cmd); break; | ||
82 | |||
83 | case NAND_CTL_SETNCE: T_NAND_CTL_SETNCE(cmd); break; | ||
84 | case NAND_CTL_CLRNCE: T_NAND_CTL_CLRNCE(cmd); break; | ||
85 | } | ||
86 | } | ||
87 | |||
88 | static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte) | 62 | static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte) |
89 | { | 63 | { |
90 | struct nand_chip *this = mtd->priv; | 64 | struct nand_chip *this = mtd->priv; |
@@ -141,6 +115,32 @@ static int ams_delta_verify_buf(struct mtd_info *mtd, const u_char *buf, | |||
141 | return 0; | 115 | return 0; |
142 | } | 116 | } |
143 | 117 | ||
118 | /* | ||
119 | * Command control function | ||
120 | * | ||
121 | * ctrl: | ||
122 | * NAND_NCE: bit 0 -> bit 2 | ||
123 | * NAND_CLE: bit 1 -> bit 7 | ||
124 | * NAND_ALE: bit 2 -> bit 6 | ||
125 | */ | ||
126 | static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd, | ||
127 | unsigned int ctrl) | ||
128 | { | ||
129 | |||
130 | if (ctrl & NAND_CTRL_CHANGE) { | ||
131 | unsigned long bits; | ||
132 | |||
133 | bits = (~ctrl & NAND_NCE) << 2; | ||
134 | bits |= (ctrl & NAND_CLE) << 7; | ||
135 | bits |= (ctrl & NAND_ALE) << 6; | ||
136 | |||
137 | ams_delta_latch2_write(0xC2, bits); | ||
138 | } | ||
139 | |||
140 | if (cmd != NAND_CMD_NONE) | ||
141 | ams_delta_write_byte(mtd, cmd); | ||
142 | } | ||
143 | |||
144 | static int ams_delta_nand_ready(struct mtd_info *mtd) | 144 | static int ams_delta_nand_ready(struct mtd_info *mtd) |
145 | { | 145 | { |
146 | return omap_get_gpio_datain(AMS_DELTA_GPIO_PIN_NAND_RB); | 146 | return omap_get_gpio_datain(AMS_DELTA_GPIO_PIN_NAND_RB); |
@@ -183,7 +183,7 @@ static int __init ams_delta_init(void) | |||
183 | this->write_buf = ams_delta_write_buf; | 183 | this->write_buf = ams_delta_write_buf; |
184 | this->read_buf = ams_delta_read_buf; | 184 | this->read_buf = ams_delta_read_buf; |
185 | this->verify_buf = ams_delta_verify_buf; | 185 | this->verify_buf = ams_delta_verify_buf; |
186 | this->hwcontrol = ams_delta_hwcontrol; | 186 | this->cmd_ctrl = ams_delta_hwcontrol; |
187 | if (!omap_request_gpio(AMS_DELTA_GPIO_PIN_NAND_RB)) { | 187 | if (!omap_request_gpio(AMS_DELTA_GPIO_PIN_NAND_RB)) { |
188 | this->dev_ready = ams_delta_nand_ready; | 188 | this->dev_ready = ams_delta_nand_ready; |
189 | } else { | 189 | } else { |
@@ -200,7 +200,7 @@ static int __init ams_delta_init(void) | |||
200 | AMS_DELTA_LATCH2_NAND_NCE | | 200 | AMS_DELTA_LATCH2_NAND_NCE | |
201 | AMS_DELTA_LATCH2_NAND_NWP); | 201 | AMS_DELTA_LATCH2_NAND_NWP); |
202 | 202 | ||
203 | /* Scan to find existance of the device */ | 203 | /* Scan to find existance of the device */ |
204 | if (nand_scan(ams_delta_mtd, 1)) { | 204 | if (nand_scan(ams_delta_mtd, 1)) { |
205 | err = -ENXIO; | 205 | err = -ENXIO; |
206 | goto out_mtd; | 206 | goto out_mtd; |