diff options
author | Lew Glendenning <lglendenning@lnxi.com> | 2006-10-20 17:41:04 -0400 |
---|---|---|
committer | David Woodhouse <dwmw2@infradead.org> | 2006-10-21 11:21:04 -0400 |
commit | 29175778b07aa60e7f8030bd95d69f70070cc1f7 (patch) | |
tree | d270a0891202a87f051cce677dbe9f434b5d7a26 /drivers/mtd/maps | |
parent | 89072ef99367cd6fab37b85d6a59a575084c2d2c (diff) |
[MTD] MAPS: Support for BIOS flash chips on Intel ESB2 southbridge
Add MTD map driver for BIOS flash chips connected to the Intel ESB2
southbridge.
[akpm@osdl.org: coding-style fixes, build fix]
Signed-off-by: Ryan Jackson <rjackson@lnxi.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Diffstat (limited to 'drivers/mtd/maps')
-rw-r--r-- | drivers/mtd/maps/Kconfig | 9 | ||||
-rw-r--r-- | drivers/mtd/maps/Makefile | 1 | ||||
-rw-r--r-- | drivers/mtd/maps/esb2rom.c | 449 |
3 files changed, 459 insertions, 0 deletions
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 24747bdc3e19..7514a9bee015 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig | |||
@@ -184,6 +184,15 @@ config MTD_ICHXROM | |||
184 | 184 | ||
185 | BE VERY CAREFUL. | 185 | BE VERY CAREFUL. |
186 | 186 | ||
187 | config MTD_ESB2ROM | ||
188 | tristate "BIOS flash chip on Intel ESB Controller Hub 2" | ||
189 | depends on X86 && MTD_JEDECPROBE | ||
190 | help | ||
191 | Support for treating the BIOS flash chip on ESB2 motherboards | ||
192 | as an MTD device - with this you can reprogram your BIOS. | ||
193 | |||
194 | BE VERY CAREFUL. | ||
195 | |||
187 | config MTD_SCB2_FLASH | 196 | config MTD_SCB2_FLASH |
188 | tristate "BIOS flash chip on Intel SCB2 boards" | 197 | tristate "BIOS flash chip on Intel SCB2 boards" |
189 | depends on X86 && MTD_JEDECPROBE | 198 | depends on X86 && MTD_JEDECPROBE |
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index 191c1928bbec..9061432c5e1a 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile | |||
@@ -17,6 +17,7 @@ obj-$(CONFIG_MTD_DC21285) += dc21285.o | |||
17 | obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o | 17 | obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o |
18 | obj-$(CONFIG_MTD_L440GX) += l440gx.o | 18 | obj-$(CONFIG_MTD_L440GX) += l440gx.o |
19 | obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o | 19 | obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o |
20 | obj-$(CONFIG_MTD_ESB2ROM) += esb2rom.o | ||
20 | obj-$(CONFIG_MTD_ICHXROM) += ichxrom.o | 21 | obj-$(CONFIG_MTD_ICHXROM) += ichxrom.o |
21 | obj-$(CONFIG_MTD_TSUNAMI) += tsunami_flash.o | 22 | obj-$(CONFIG_MTD_TSUNAMI) += tsunami_flash.o |
22 | obj-$(CONFIG_MTD_LUBBOCK) += lubbock-flash.o | 23 | obj-$(CONFIG_MTD_LUBBOCK) += lubbock-flash.o |
diff --git a/drivers/mtd/maps/esb2rom.c b/drivers/mtd/maps/esb2rom.c new file mode 100644 index 000000000000..e1c781482bfa --- /dev/null +++ b/drivers/mtd/maps/esb2rom.c | |||
@@ -0,0 +1,449 @@ | |||
1 | /* | ||
2 | * esb2rom.c | ||
3 | * | ||
4 | * Normal mappings of flash chips in physical memory | ||
5 | * through the Intel ESB2 Southbridge. | ||
6 | * | ||
7 | * This was derived from ichxrom.c in May 2006 by | ||
8 | * Lew Glendenning <lglendenning@lnxi.com> | ||
9 | * | ||
10 | * Eric Biederman, of course, was a major help in this effort. | ||
11 | */ | ||
12 | |||
13 | #include <linux/module.h> | ||
14 | #include <linux/types.h> | ||
15 | #include <linux/version.h> | ||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <asm/io.h> | ||
19 | #include <linux/mtd/mtd.h> | ||
20 | #include <linux/mtd/map.h> | ||
21 | #include <linux/mtd/cfi.h> | ||
22 | #include <linux/mtd/flashchip.h> | ||
23 | #include <linux/pci.h> | ||
24 | #include <linux/pci_ids.h> | ||
25 | #include <linux/list.h> | ||
26 | |||
27 | #define MOD_NAME KBUILD_BASENAME | ||
28 | |||
29 | #define ADDRESS_NAME_LEN 18 | ||
30 | |||
31 | #define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */ | ||
32 | |||
33 | #define BIOS_CNTL 0xDC | ||
34 | #define BIOS_LOCK_ENABLE 0x02 | ||
35 | #define BIOS_WRITE_ENABLE 0x01 | ||
36 | |||
37 | /* This became a 16-bit register, and EN2 has disappeared */ | ||
38 | #define FWH_DEC_EN1 0xD8 | ||
39 | #define FWH_F8_EN 0x8000 | ||
40 | #define FWH_F0_EN 0x4000 | ||
41 | #define FWH_E8_EN 0x2000 | ||
42 | #define FWH_E0_EN 0x1000 | ||
43 | #define FWH_D8_EN 0x0800 | ||
44 | #define FWH_D0_EN 0x0400 | ||
45 | #define FWH_C8_EN 0x0200 | ||
46 | #define FWH_C0_EN 0x0100 | ||
47 | #define FWH_LEGACY_F_EN 0x0080 | ||
48 | #define FWH_LEGACY_E_EN 0x0040 | ||
49 | /* reserved 0x0020 and 0x0010 */ | ||
50 | #define FWH_70_EN 0x0008 | ||
51 | #define FWH_60_EN 0x0004 | ||
52 | #define FWH_50_EN 0x0002 | ||
53 | #define FWH_40_EN 0x0001 | ||
54 | |||
55 | /* these are 32-bit values */ | ||
56 | #define FWH_SEL1 0xD0 | ||
57 | #define FWH_SEL2 0xD4 | ||
58 | |||
59 | #define FWH_8MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ | ||
60 | FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ | ||
61 | FWH_70_EN | FWH_60_EN | FWH_50_EN | FWH_40_EN) | ||
62 | |||
63 | #define FWH_7MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ | ||
64 | FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ | ||
65 | FWH_70_EN | FWH_60_EN | FWH_50_EN) | ||
66 | |||
67 | #define FWH_6MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ | ||
68 | FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ | ||
69 | FWH_70_EN | FWH_60_EN) | ||
70 | |||
71 | #define FWH_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ | ||
72 | FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ | ||
73 | FWH_70_EN) | ||
74 | |||
75 | #define FWH_4MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ | ||
76 | FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN) | ||
77 | |||
78 | #define FWH_3_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ | ||
79 | FWH_D8_EN | FWH_D0_EN | FWH_C8_EN) | ||
80 | |||
81 | #define FWH_3MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ | ||
82 | FWH_D8_EN | FWH_D0_EN) | ||
83 | |||
84 | #define FWH_2_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ | ||
85 | FWH_D8_EN) | ||
86 | |||
87 | #define FWH_2MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN) | ||
88 | |||
89 | #define FWH_1_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN) | ||
90 | |||
91 | #define FWH_1MiB (FWH_F8_EN | FWH_F0_EN) | ||
92 | |||
93 | #define FWH_0_5MiB (FWH_F8_EN) | ||
94 | |||
95 | |||
96 | struct esb2rom_window { | ||
97 | void __iomem* virt; | ||
98 | unsigned long phys; | ||
99 | unsigned long size; | ||
100 | struct list_head maps; | ||
101 | struct resource rsrc; | ||
102 | struct pci_dev *pdev; | ||
103 | }; | ||
104 | |||
105 | struct esb2rom_map_info { | ||
106 | struct list_head list; | ||
107 | struct map_info map; | ||
108 | struct mtd_info *mtd; | ||
109 | struct resource rsrc; | ||
110 | char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN]; | ||
111 | }; | ||
112 | |||
113 | static struct esb2rom_window esb2rom_window = { | ||
114 | .maps = LIST_HEAD_INIT(esb2rom_window.maps), | ||
115 | }; | ||
116 | |||
117 | static void esb2rom_cleanup(struct esb2rom_window *window) | ||
118 | { | ||
119 | struct esb2rom_map_info *map, *scratch; | ||
120 | u8 byte; | ||
121 | |||
122 | /* Disable writes through the rom window */ | ||
123 | pci_read_config_byte(window->pdev, BIOS_CNTL, &byte); | ||
124 | pci_write_config_byte(window->pdev, BIOS_CNTL, | ||
125 | byte & ~BIOS_WRITE_ENABLE); | ||
126 | |||
127 | /* Free all of the mtd devices */ | ||
128 | list_for_each_entry_safe(map, scratch, &window->maps, list) { | ||
129 | if (map->rsrc.parent) | ||
130 | release_resource(&map->rsrc); | ||
131 | del_mtd_device(map->mtd); | ||
132 | map_destroy(map->mtd); | ||
133 | list_del(&map->list); | ||
134 | kfree(map); | ||
135 | } | ||
136 | if (window->rsrc.parent) | ||
137 | release_resource(&window->rsrc); | ||
138 | if (window->virt) { | ||
139 | iounmap(window->virt); | ||
140 | window->virt = NULL; | ||
141 | window->phys = 0; | ||
142 | window->size = 0; | ||
143 | window->pdev = NULL; | ||
144 | } | ||
145 | } | ||
146 | |||
147 | static int __devinit esb2rom_init_one(struct pci_dev *pdev, | ||
148 | const struct pci_device_id *ent) | ||
149 | { | ||
150 | static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; | ||
151 | struct esb2rom_window *window = &esb2rom_window; | ||
152 | struct esb2rom_map_info *map = NULL; | ||
153 | unsigned long map_top; | ||
154 | u8 byte; | ||
155 | u16 word; | ||
156 | |||
157 | /* For now I just handle the ecb2 and I assume there | ||
158 | * are not a lot of resources up at the top of the address | ||
159 | * space. It is possible to handle other devices in the | ||
160 | * top 16MiB but it is very painful. Also since | ||
161 | * you can only really attach a FWH to an ICHX there | ||
162 | * a number of simplifications you can make. | ||
163 | * | ||
164 | * Also you can page firmware hubs if an 8MiB window isn't enough | ||
165 | * but don't currently handle that case either. | ||
166 | */ | ||
167 | window->pdev = pdev; | ||
168 | |||
169 | /* RLG: experiment 2. Force the window registers to the widest values */ | ||
170 | |||
171 | /* | ||
172 | pci_read_config_word(pdev, FWH_DEC_EN1, &word); | ||
173 | printk(KERN_DEBUG "Original FWH_DEC_EN1 : %x\n", word); | ||
174 | pci_write_config_byte(pdev, FWH_DEC_EN1, 0xff); | ||
175 | pci_read_config_byte(pdev, FWH_DEC_EN1, &byte); | ||
176 | printk(KERN_DEBUG "New FWH_DEC_EN1 : %x\n", byte); | ||
177 | |||
178 | pci_read_config_byte(pdev, FWH_DEC_EN2, &byte); | ||
179 | printk(KERN_DEBUG "Original FWH_DEC_EN2 : %x\n", byte); | ||
180 | pci_write_config_byte(pdev, FWH_DEC_EN2, 0x0f); | ||
181 | pci_read_config_byte(pdev, FWH_DEC_EN2, &byte); | ||
182 | printk(KERN_DEBUG "New FWH_DEC_EN2 : %x\n", byte); | ||
183 | */ | ||
184 | |||
185 | /* Find a region continuous to the end of the ROM window */ | ||
186 | window->phys = 0; | ||
187 | pci_read_config_word(pdev, FWH_DEC_EN1, &word); | ||
188 | printk(KERN_DEBUG "pci_read_config_byte : %x\n", word); | ||
189 | |||
190 | if ((word & FWH_8MiB) == FWH_8MiB) | ||
191 | window->phys = 0xff400000; | ||
192 | else if ((word & FWH_7MiB) == FWH_7MiB) | ||
193 | window->phys = 0xff500000; | ||
194 | else if ((word & FWH_6MiB) == FWH_6MiB) | ||
195 | window->phys = 0xff600000; | ||
196 | else if ((word & FWH_5MiB) == FWH_5MiB) | ||
197 | window->phys = 0xFF700000; | ||
198 | else if ((word & FWH_4MiB) == FWH_4MiB) | ||
199 | window->phys = 0xffc00000; | ||
200 | else if ((word & FWH_3_5MiB) == FWH_3_5MiB) | ||
201 | window->phys = 0xffc80000; | ||
202 | else if ((word & FWH_3MiB) == FWH_3MiB) | ||
203 | window->phys = 0xffd00000; | ||
204 | else if ((word & FWH_2_5MiB) == FWH_2_5MiB) | ||
205 | window->phys = 0xffd80000; | ||
206 | else if ((word & FWH_2MiB) == FWH_2MiB) | ||
207 | window->phys = 0xffe00000; | ||
208 | else if ((word & FWH_1_5MiB) == FWH_1_5MiB) | ||
209 | window->phys = 0xffe80000; | ||
210 | else if ((word & FWH_1MiB) == FWH_1MiB) | ||
211 | window->phys = 0xfff00000; | ||
212 | else if ((word & FWH_0_5MiB) == FWH_0_5MiB) | ||
213 | window->phys = 0xfff80000; | ||
214 | |||
215 | /* reserved 0x0020 and 0x0010 */ | ||
216 | window->phys -= 0x400000UL; | ||
217 | window->size = (0xffffffffUL - window->phys) + 1UL; | ||
218 | |||
219 | /* Enable writes through the rom window */ | ||
220 | pci_read_config_byte(pdev, BIOS_CNTL, &byte); | ||
221 | if (!(byte & BIOS_WRITE_ENABLE) && (byte & (BIOS_LOCK_ENABLE))) { | ||
222 | /* The BIOS will generate an error if I enable | ||
223 | * this device, so don't even try. | ||
224 | */ | ||
225 | printk(KERN_ERR MOD_NAME ": firmware access control, I can't enable writes\n"); | ||
226 | goto out; | ||
227 | } | ||
228 | pci_write_config_byte(pdev, BIOS_CNTL, byte | BIOS_WRITE_ENABLE); | ||
229 | |||
230 | /* | ||
231 | * Try to reserve the window mem region. If this fails then | ||
232 | * it is likely due to the window being "reseved" by the BIOS. | ||
233 | */ | ||
234 | window->rsrc.name = MOD_NAME; | ||
235 | window->rsrc.start = window->phys; | ||
236 | window->rsrc.end = window->phys + window->size - 1; | ||
237 | window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | ||
238 | if (request_resource(&iomem_resource, &window->rsrc)) { | ||
239 | window->rsrc.parent = NULL; | ||
240 | printk(KERN_DEBUG MOD_NAME | ||
241 | ": %s(): Unable to register resource" | ||
242 | " 0x%.08llx-0x%.08llx - kernel bug?\n", | ||
243 | __func__, | ||
244 | (unsigned long long)window->rsrc.start, | ||
245 | (unsigned long long)window->rsrc.end); | ||
246 | } | ||
247 | |||
248 | /* Map the firmware hub into my address space. */ | ||
249 | window->virt = ioremap_nocache(window->phys, window->size); | ||
250 | if (!window->virt) { | ||
251 | printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n", | ||
252 | window->phys, window->size); | ||
253 | goto out; | ||
254 | } | ||
255 | |||
256 | /* Get the first address to look for an rom chip at */ | ||
257 | map_top = window->phys; | ||
258 | if ((window->phys & 0x3fffff) != 0) { | ||
259 | /* if not aligned on 4MiB, look 4MiB lower in address space */ | ||
260 | map_top = window->phys + 0x400000; | ||
261 | } | ||
262 | #if 1 | ||
263 | /* The probe sequence run over the firmware hub lock | ||
264 | * registers sets them to 0x7 (no access). | ||
265 | * (Insane hardware design, but most copied Intel's.) | ||
266 | * ==> Probe at most the last 4M of the address space. | ||
267 | */ | ||
268 | if (map_top < 0xffc00000) | ||
269 | map_top = 0xffc00000; | ||
270 | #endif | ||
271 | /* Loop through and look for rom chips */ | ||
272 | while ((map_top - 1) < 0xffffffffUL) { | ||
273 | struct cfi_private *cfi; | ||
274 | unsigned long offset; | ||
275 | int i; | ||
276 | |||
277 | if (!map) | ||
278 | map = kmalloc(sizeof(*map), GFP_KERNEL); | ||
279 | if (!map) { | ||
280 | printk(KERN_ERR MOD_NAME ": kmalloc failed"); | ||
281 | goto out; | ||
282 | } | ||
283 | memset(map, 0, sizeof(*map)); | ||
284 | INIT_LIST_HEAD(&map->list); | ||
285 | map->map.name = map->map_name; | ||
286 | map->map.phys = map_top; | ||
287 | offset = map_top - window->phys; | ||
288 | map->map.virt = (void __iomem *) | ||
289 | (((unsigned long)(window->virt)) + offset); | ||
290 | map->map.size = 0xffffffffUL - map_top + 1UL; | ||
291 | /* Set the name of the map to the address I am trying */ | ||
292 | sprintf(map->map_name, "%s @%08lx", | ||
293 | MOD_NAME, map->map.phys); | ||
294 | |||
295 | /* Firmware hubs only use vpp when being programmed | ||
296 | * in a factory setting. So in-place programming | ||
297 | * needs to use a different method. | ||
298 | */ | ||
299 | for(map->map.bankwidth = 32; map->map.bankwidth; | ||
300 | map->map.bankwidth >>= 1) { | ||
301 | char **probe_type; | ||
302 | /* Skip bankwidths that are not supported */ | ||
303 | if (!map_bankwidth_supported(map->map.bankwidth)) | ||
304 | continue; | ||
305 | |||
306 | /* Setup the map methods */ | ||
307 | simple_map_init(&map->map); | ||
308 | |||
309 | /* Try all of the probe methods */ | ||
310 | probe_type = rom_probe_types; | ||
311 | for(; *probe_type; probe_type++) { | ||
312 | map->mtd = do_map_probe(*probe_type, &map->map); | ||
313 | if (map->mtd) | ||
314 | goto found; | ||
315 | } | ||
316 | } | ||
317 | map_top += ROM_PROBE_STEP_SIZE; | ||
318 | continue; | ||
319 | found: | ||
320 | /* Trim the size if we are larger than the map */ | ||
321 | if (map->mtd->size > map->map.size) { | ||
322 | printk(KERN_WARNING MOD_NAME | ||
323 | " rom(%u) larger than window(%lu). fixing...\n", | ||
324 | map->mtd->size, map->map.size); | ||
325 | map->mtd->size = map->map.size; | ||
326 | } | ||
327 | if (window->rsrc.parent) { | ||
328 | /* | ||
329 | * Registering the MTD device in iomem may not be possible | ||
330 | * if there is a BIOS "reserved" and BUSY range. If this | ||
331 | * fails then continue anyway. | ||
332 | */ | ||
333 | map->rsrc.name = map->map_name; | ||
334 | map->rsrc.start = map->map.phys; | ||
335 | map->rsrc.end = map->map.phys + map->mtd->size - 1; | ||
336 | map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | ||
337 | if (request_resource(&window->rsrc, &map->rsrc)) { | ||
338 | printk(KERN_ERR MOD_NAME | ||
339 | ": cannot reserve MTD resource\n"); | ||
340 | map->rsrc.parent = NULL; | ||
341 | } | ||
342 | } | ||
343 | |||
344 | /* Make the whole region visible in the map */ | ||
345 | map->map.virt = window->virt; | ||
346 | map->map.phys = window->phys; | ||
347 | cfi = map->map.fldrv_priv; | ||
348 | for(i = 0; i < cfi->numchips; i++) | ||
349 | cfi->chips[i].start += offset; | ||
350 | |||
351 | /* Now that the mtd devices is complete claim and export it */ | ||
352 | map->mtd->owner = THIS_MODULE; | ||
353 | if (add_mtd_device(map->mtd)) { | ||
354 | map_destroy(map->mtd); | ||
355 | map->mtd = NULL; | ||
356 | goto out; | ||
357 | } | ||
358 | |||
359 | /* Calculate the new value of map_top */ | ||
360 | map_top += map->mtd->size; | ||
361 | |||
362 | /* File away the map structure */ | ||
363 | list_add(&map->list, &window->maps); | ||
364 | map = NULL; | ||
365 | } | ||
366 | |||
367 | out: | ||
368 | /* Free any left over map structures */ | ||
369 | kfree(map); | ||
370 | |||
371 | /* See if I have any map structures */ | ||
372 | if (list_empty(&window->maps)) { | ||
373 | esb2rom_cleanup(window); | ||
374 | return -ENODEV; | ||
375 | } | ||
376 | return 0; | ||
377 | } | ||
378 | |||
379 | static void __devexit esb2rom_remove_one (struct pci_dev *pdev) | ||
380 | { | ||
381 | struct esb2rom_window *window = &esb2rom_window; | ||
382 | esb2rom_cleanup(window); | ||
383 | } | ||
384 | |||
385 | static struct pci_device_id esb2rom_pci_tbl[] __devinitdata = { | ||
386 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, | ||
387 | PCI_ANY_ID, PCI_ANY_ID, }, | ||
388 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, | ||
389 | PCI_ANY_ID, PCI_ANY_ID, }, | ||
390 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, | ||
391 | PCI_ANY_ID, PCI_ANY_ID, }, | ||
392 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, | ||
393 | PCI_ANY_ID, PCI_ANY_ID, }, | ||
394 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, | ||
395 | PCI_ANY_ID, PCI_ANY_ID, }, | ||
396 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, | ||
397 | PCI_ANY_ID, PCI_ANY_ID, }, | ||
398 | { 0, }, | ||
399 | }; | ||
400 | |||
401 | #if 0 | ||
402 | MODULE_DEVICE_TABLE(pci, esb2rom_pci_tbl); | ||
403 | |||
404 | static struct pci_driver esb2rom_driver = { | ||
405 | .name = MOD_NAME, | ||
406 | .id_table = esb2rom_pci_tbl, | ||
407 | .probe = esb2rom_init_one, | ||
408 | .remove = esb2rom_remove_one, | ||
409 | }; | ||
410 | #endif | ||
411 | |||
412 | static int __init init_esb2rom(void) | ||
413 | { | ||
414 | struct pci_dev *pdev; | ||
415 | struct pci_device_id *id; | ||
416 | int retVal; | ||
417 | |||
418 | pdev = NULL; | ||
419 | for (id = esb2rom_pci_tbl; id->vendor; id++) { | ||
420 | printk(KERN_DEBUG "device id = %x\n", id->device); | ||
421 | pdev = pci_find_device(id->vendor, id->device, NULL); | ||
422 | if (pdev) { | ||
423 | printk(KERN_DEBUG "matched device = %x\n", id->device); | ||
424 | break; | ||
425 | } | ||
426 | } | ||
427 | if (pdev) { | ||
428 | printk(KERN_DEBUG "matched device id %x\n", id->device); | ||
429 | retVal = esb2rom_init_one(pdev, &esb2rom_pci_tbl[0]); | ||
430 | printk(KERN_DEBUG "retVal = %d\n", retVal); | ||
431 | return retVal; | ||
432 | } | ||
433 | return -ENXIO; | ||
434 | #if 0 | ||
435 | return pci_register_driver(&esb2rom_driver); | ||
436 | #endif | ||
437 | } | ||
438 | |||
439 | static void __exit cleanup_esb2rom(void) | ||
440 | { | ||
441 | esb2rom_remove_one(esb2rom_window.pdev); | ||
442 | } | ||
443 | |||
444 | module_init(init_esb2rom); | ||
445 | module_exit(cleanup_esb2rom); | ||
446 | |||
447 | MODULE_LICENSE("GPL"); | ||
448 | MODULE_AUTHOR("Lew Glendenning <lglendenning@lnxi.com>"); | ||
449 | MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ESB2 southbridge"); | ||