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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-12-06 03:25:16 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-12-13 04:12:07 -0500
commit70d13e083c8589dd3edc2313777655da39cb3568 (patch)
tree41478a4699b3cbc8c5598ccc1863ea058948741e /drivers/mtd/maps
parent7ec80ddf0455ff3854a5ca524952d91b5eb676b2 (diff)
[ARM] netwinder: clean up GPIO naming
Netwinder was using gpio_xxx names which could clash with the GPIO layer. Add a 'nw_' prefix to ensure that these remain separate. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/mtd/maps')
-rw-r--r--drivers/mtd/maps/dc21285.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/mtd/maps/dc21285.c b/drivers/mtd/maps/dc21285.c
index 3aa018c092f8..42969fe051b2 100644
--- a/drivers/mtd/maps/dc21285.c
+++ b/drivers/mtd/maps/dc21285.c
@@ -32,16 +32,15 @@ static struct mtd_info *dc21285_mtd;
32 */ 32 */
33static void nw_en_write(void) 33static void nw_en_write(void)
34{ 34{
35 extern spinlock_t gpio_lock;
36 unsigned long flags; 35 unsigned long flags;
37 36
38 /* 37 /*
39 * we want to write a bit pattern XXX1 to Xilinx to enable 38 * we want to write a bit pattern XXX1 to Xilinx to enable
40 * the write gate, which will be open for about the next 2ms. 39 * the write gate, which will be open for about the next 2ms.
41 */ 40 */
42 spin_lock_irqsave(&gpio_lock, flags); 41 spin_lock_irqsave(&nw_gpio_lock, flags);
43 cpld_modify(1, 1); 42 nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
44 spin_unlock_irqrestore(&gpio_lock, flags); 43 spin_unlock_irqrestore(&nw_gpio_lock, flags);
45 44
46 /* 45 /*
47 * let the ISA bus to catch on... 46 * let the ISA bus to catch on...