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authorKevin Cernekee <cernekee@gmail.com>2011-05-08 13:48:01 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2011-05-24 21:02:34 -0400
commitbaa9ae3cfdf8ca2cb019c02c0a9e16f63cdd0260 (patch)
tree8cf2212342449c1ad5f15ad8268b5f3ac0ef187b /drivers/mtd/devices
parentaa0846534b9c7238187b4276e83efb9969d4c6e3 (diff)
mtd: m25p80: Add Spansion S25FL256S
These are 32MiB parts which use a slightly different 4-byte enable sequence from Macronix. Default to the Spansion 4-byte scheme in set_4byte(), as it is more likely to be copied by other vendors. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/devices')
-rw-r--r--drivers/mtd/devices/m25p80.c22
1 files changed, 17 insertions, 5 deletions
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 16adfaa78018..e050cc8b3ee7 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -56,6 +56,9 @@
56#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ 56#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
57#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ 57#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
58 58
59/* Used for Spansion flashes only. */
60#define OPCODE_BRWR 0x17 /* Bank register write */
61
59/* Status Register bits. */ 62/* Status Register bits. */
60#define SR_WIP 1 /* Write in progress */ 63#define SR_WIP 1 /* Write in progress */
61#define SR_WEL 2 /* Write enable latch */ 64#define SR_WEL 2 /* Write enable latch */
@@ -161,11 +164,18 @@ static inline int write_disable(struct m25p *flash)
161/* 164/*
162 * Enable/disable 4-byte addressing mode. 165 * Enable/disable 4-byte addressing mode.
163 */ 166 */
164static inline int set_4byte(struct m25p *flash, int enable) 167static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
165{ 168{
166 u8 code = enable ? OPCODE_EN4B : OPCODE_EX4B; 169 switch (JEDEC_MFR(jedec_id)) {
167 170 case CFI_MFR_MACRONIX:
168 return spi_write_then_read(flash->spi, &code, 1, NULL, 0); 171 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
172 return spi_write(flash->spi, flash->command, 1);
173 default:
174 /* Spansion style */
175 flash->command[0] = OPCODE_BRWR;
176 flash->command[1] = enable << 7;
177 return spi_write(flash->spi, flash->command, 2);
178 }
169} 179}
170 180
171/* 181/*
@@ -688,6 +698,8 @@ static const struct spi_device_id m25p_ids[] = {
688 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, 698 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
689 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SECT_4K) }, 699 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SECT_4K) },
690 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, 700 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
701 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
702 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
691 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, 703 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
692 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, 704 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
693 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) }, 705 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
@@ -921,7 +933,7 @@ static int __devinit m25p_probe(struct spi_device *spi)
921 /* enable 4-byte addressing if the device exceeds 16MiB */ 933 /* enable 4-byte addressing if the device exceeds 16MiB */
922 if (flash->mtd.size > 0x1000000) { 934 if (flash->mtd.size > 0x1000000) {
923 flash->addr_width = 4; 935 flash->addr_width = 4;
924 set_4byte(flash, 1); 936 set_4byte(flash, info->jedec_id, 1);
925 } else 937 } else
926 flash->addr_width = 3; 938 flash->addr_width = 3;
927 } 939 }