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authorChristopher Moore <moore@free.fr>2008-10-16 23:32:22 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2008-10-18 07:41:51 -0400
commit87e92c062b19eea6054532f8143a91242f104a6f (patch)
tree09a79d6497093bd488444428ae2d5d2aefbd1ea8 /drivers/mtd/chips
parent6b8520296d67622dfa225436ef325f7dfd6ece8e (diff)
[MTD] cfi_cmdset_0002.c: Add Macronix CFI V1.0 TopBottom detection
This patch adds TopBottom detection for most Macronix chips with CFI V1.0. The main purpose of this patch is to add detection of the MX29LV400C B used on the LaCie Ethernet Disk mini V2 NAS. It detects the following parts correctly:- MX28F640C3B T MX29LV002C B MX29LV002NC B MX29LV004C T MX29LV400C T/B MX29LV800C T/B MX29LV160C T/B MX29SL800C T/B MX29SL802C T/B It detects the following uniform part as bottom but it should work correctly:- MX29LV040C For T parts it causes the erase block table to be reversed correctly. For other parts it avoids the bogus "Assuming top" message. It does not detect the following correctly:- MX28F640C3B B MX29LV002C T MX29LV002NC T MX29LV004C B MX29SL400C T/B MX29SL402C T/B If desired I could supply a more complicated patch to handle these as well. Only the MX29LV400C B has been physically tested; others were checked against their data sheets. Signed-off-by: Christopher Moore <moore@free.fr> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/chips')
-rw-r--r--drivers/mtd/chips/cfi_cmdset_0002.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
index a972cc6be436..db16b7b0723f 100644
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -13,6 +13,8 @@
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash 13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
14 * by Nicolas Pitre) 14 * by Nicolas Pitre)
15 * 15 *
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
17 *
16 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com 18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
17 * 19 *
18 * This code is GPL 20 * This code is GPL
@@ -43,6 +45,7 @@
43 45
44#define MANUFACTURER_AMD 0x0001 46#define MANUFACTURER_AMD 0x0001
45#define MANUFACTURER_ATMEL 0x001F 47#define MANUFACTURER_ATMEL 0x001F
48#define MANUFACTURER_MACRONIX 0x00C2
46#define MANUFACTURER_SST 0x00BF 49#define MANUFACTURER_SST 0x00BF
47#define SST49LF004B 0x0060 50#define SST49LF004B 0x0060
48#define SST49LF040B 0x0050 51#define SST49LF040B 0x0050
@@ -144,12 +147,44 @@ static void fixup_amd_bootblock(struct mtd_info *mtd, void* param)
144 147
145 if (((major << 8) | minor) < 0x3131) { 148 if (((major << 8) | minor) < 0x3131) {
146 /* CFI version 1.0 => don't trust bootloc */ 149 /* CFI version 1.0 => don't trust bootloc */
150
151 DEBUG(MTD_DEBUG_LEVEL1,
152 "%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
153 map->name, cfi->mfr, cfi->id);
154
155 /* AFAICS all 29LV400 with a bottom boot block have a device ID
156 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
157 * These were badly detected as they have the 0x80 bit set
158 * so treat them as a special case.
159 */
160 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
161
162 /* Macronix added CFI to their 2nd generation
163 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
164 * Fujitsu, Spansion, EON, ESI and older Macronix)
165 * has CFI.
166 *
167 * Therefore also check the manufacturer.
168 * This reduces the risk of false detection due to
169 * the 8-bit device ID.
170 */
171 (cfi->mfr == MANUFACTURER_MACRONIX)) {
172 DEBUG(MTD_DEBUG_LEVEL1,
173 "%s: Macronix MX29LV400C with bottom boot block"
174 " detected\n", map->name);
175 extp->TopBottom = 2; /* bottom boot */
176 } else
147 if (cfi->id & 0x80) { 177 if (cfi->id & 0x80) {
148 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id); 178 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
149 extp->TopBottom = 3; /* top boot */ 179 extp->TopBottom = 3; /* top boot */
150 } else { 180 } else {
151 extp->TopBottom = 2; /* bottom boot */ 181 extp->TopBottom = 2; /* bottom boot */
152 } 182 }
183
184 DEBUG(MTD_DEBUG_LEVEL1,
185 "%s: AMD CFI PRI V%c.%c has no boot block field;"
186 " deduced %s from Device ID\n", map->name, major, minor,
187 extp->TopBottom == 2 ? "bottom" : "top");
153 } 188 }
154} 189}
155#endif 190#endif
@@ -243,6 +278,7 @@ static struct cfi_fixup cfi_fixup_table[] = {
243 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL }, 278 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
244#ifdef AMD_BOOTLOC_BUG 279#ifdef AMD_BOOTLOC_BUG
245 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL }, 280 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
281 { MANUFACTURER_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock, NULL },
246#endif 282#endif
247 { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, }, 283 { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, },
248 { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, }, 284 { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, },