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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-03 12:46:29 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-03 12:46:29 -0400
commitfb2af0020a51709ad87ea8055c325d3fbde04158 (patch)
tree88f3bc38d5604c6eed00597873f209726f9aaeb5 /drivers/mmc
parent790eac5640abf7a57fa3a644386df330e18c11b0 (diff)
parent3c0c01ab742ddfaf6b6f2d64b890e77cda4b7727 (diff)
Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM updates from Russell King: "This contains the usual updates from other people (listed below) and the usual random muddle of miscellaneous ARM updates which cover some low priority bug fixes and performance improvements. I've started to put the pull request wording into the merge commits, which are: - NoMMU stuff: This includes the following series sent earlier to the list: - nommu-fixes - R7 Support - MPU support I've left out the ARCH_MULTIPLATFORM/!MMU stuff that Arnd and I were discussing today until we've reached a conclusion/that's had some more review. This is rebased (and re-tested) on your devel-stable branch because otherwise there were going to be conflicts with Uwe's V7M work now that you've merged that. I've included the fix for limiting MPU to CPU_V7. - Huge page support These changes bring both HugeTLB support and Transparent HugePage (THP) support to ARM. Only long descriptors (LPAE) are supported in this series. The code has been tested on an Arndale board (Exynos 5250). - LPAE updates Please pull these miscellaneous LPAE fixes I've been collecting for a while now for 3.11. They've been tested and reviewed by quite a few people, and most of the patches are pretty trivial. -- Will Deacon. - arch_timer cleanups Please pull these arch_timer cleanups I've been holding onto for a while. They're the same as my last posting, but have been rebased to v3.10-rc3. - mpidr linearisation (multiprocessor id register - identifies which CPU number we are in the system) This patch series that implements MPIDR linearization through a simple hashing algorithm and updates current cpu_{suspend}/{resume} code to use the newly created hash structures to retrieve context pointers. It represents a stepping stone for the implementation of power management code on forthcoming multi-cluster ARM systems. It has been tested on TC2 (dual cluster A15xA7 system), iMX6q, OMAP4 and Tegra, with processors hitting low-power states requiring warm-boot resume through the cpu_resume code path" * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (77 commits) ARM: 7775/1: mm: Remove do_sect_fault from LPAE code ARM: 7777/1: Avoid extra calls to the C compiler ARM: 7774/1: Fix dtb dependency to use order-only prerequisites ARM: 7770/1: remove residual ARMv2 support from decompressor ARM: 7769/1: Cortex-A15: fix erratum 798181 implementation ARM: 7768/1: prevent risks of out-of-bound access in ASID allocator ARM: 7767/1: let the ASID allocator handle suspended animation ARM: 7766/1: versatile: don't mark pen as __INIT ARM: 7765/1: perf: Record the user-mode PC in the call chain. ARM: 7735/2: Preserve the user r/w register TPIDRURW on context switch and fork ARM: kernel: implement stack pointer save array through MPIDR hashing ARM: kernel: build MPIDR hash function data structure ARM: mpu: Ensure that MPU depends on CPU_V7 ARM: mpu: protect the vectors page with an MPU region ARM: mpu: Allow enabling of the MPU via kconfig ARM: 7758/1: introduce config HAS_BANDGAP ARM: 7757/1: mm: don't flush icache in switch_mm with hardware broadcasting ARM: 7751/1: zImage: don't overwrite ourself with a page table ARM: 7749/1: spinlock: retry trylock operation if strex fails on free lock ARM: 7748/1: oabi: handle faults when loading swi instruction from userspace ...
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/mmci.c165
-rw-r--r--drivers/mmc/host/mmci.h4
2 files changed, 130 insertions, 39 deletions
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index f4f3038c1df0..c3785edc0e92 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -61,6 +61,7 @@ static unsigned int fmax = 515633;
61 * @pwrreg_powerup: power up value for MMCIPOWER register 61 * @pwrreg_powerup: power up value for MMCIPOWER register
62 * @signal_direction: input/out direction of bus signals can be indicated 62 * @signal_direction: input/out direction of bus signals can be indicated
63 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 63 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
64 * @busy_detect: true if busy detection on dat0 is supported
64 */ 65 */
65struct variant_data { 66struct variant_data {
66 unsigned int clkreg; 67 unsigned int clkreg;
@@ -74,6 +75,7 @@ struct variant_data {
74 u32 pwrreg_powerup; 75 u32 pwrreg_powerup;
75 bool signal_direction; 76 bool signal_direction;
76 bool pwrreg_clkgate; 77 bool pwrreg_clkgate;
78 bool busy_detect;
77}; 79};
78 80
79static struct variant_data variant_arm = { 81static struct variant_data variant_arm = {
@@ -132,6 +134,7 @@ static struct variant_data variant_ux500 = {
132 .pwrreg_powerup = MCI_PWR_ON, 134 .pwrreg_powerup = MCI_PWR_ON,
133 .signal_direction = true, 135 .signal_direction = true,
134 .pwrreg_clkgate = true, 136 .pwrreg_clkgate = true,
137 .busy_detect = true,
135}; 138};
136 139
137static struct variant_data variant_ux500v2 = { 140static struct variant_data variant_ux500v2 = {
@@ -146,8 +149,28 @@ static struct variant_data variant_ux500v2 = {
146 .pwrreg_powerup = MCI_PWR_ON, 149 .pwrreg_powerup = MCI_PWR_ON,
147 .signal_direction = true, 150 .signal_direction = true,
148 .pwrreg_clkgate = true, 151 .pwrreg_clkgate = true,
152 .busy_detect = true,
149}; 153};
150 154
155static int mmci_card_busy(struct mmc_host *mmc)
156{
157 struct mmci_host *host = mmc_priv(mmc);
158 unsigned long flags;
159 int busy = 0;
160
161 pm_runtime_get_sync(mmc_dev(mmc));
162
163 spin_lock_irqsave(&host->lock, flags);
164 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
165 busy = 1;
166 spin_unlock_irqrestore(&host->lock, flags);
167
168 pm_runtime_mark_last_busy(mmc_dev(mmc));
169 pm_runtime_put_autosuspend(mmc_dev(mmc));
170
171 return busy;
172}
173
151/* 174/*
152 * Validate mmc prerequisites 175 * Validate mmc prerequisites
153 */ 176 */
@@ -191,11 +214,28 @@ static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
191/* 214/*
192 * This must be called with host->lock held 215 * This must be called with host->lock held
193 */ 216 */
217static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
218{
219 /* Keep ST Micro busy mode if enabled */
220 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;
221
222 if (host->datactrl_reg != datactrl) {
223 host->datactrl_reg = datactrl;
224 writel(datactrl, host->base + MMCIDATACTRL);
225 }
226}
227
228/*
229 * This must be called with host->lock held
230 */
194static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 231static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
195{ 232{
196 struct variant_data *variant = host->variant; 233 struct variant_data *variant = host->variant;
197 u32 clk = variant->clkreg; 234 u32 clk = variant->clkreg;
198 235
236 /* Make sure cclk reflects the current calculated clock */
237 host->cclk = 0;
238
199 if (desired) { 239 if (desired) {
200 if (desired >= host->mclk) { 240 if (desired >= host->mclk) {
201 clk = MCI_CLK_BYPASS; 241 clk = MCI_CLK_BYPASS;
@@ -230,6 +270,9 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
230 /* clk |= MCI_CLK_PWRSAVE; */ 270 /* clk |= MCI_CLK_PWRSAVE; */
231 } 271 }
232 272
273 /* Set actual clock for debug */
274 host->mmc->actual_clock = host->cclk;
275
233 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 276 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
234 clk |= MCI_4BIT_BUS; 277 clk |= MCI_4BIT_BUS;
235 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 278 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
@@ -275,7 +318,7 @@ static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
275 318
276static void mmci_stop_data(struct mmci_host *host) 319static void mmci_stop_data(struct mmci_host *host)
277{ 320{
278 writel(0, host->base + MMCIDATACTRL); 321 mmci_write_datactrlreg(host, 0);
279 mmci_set_mask1(host, 0); 322 mmci_set_mask1(host, 0);
280 host->data = NULL; 323 host->data = NULL;
281} 324}
@@ -304,10 +347,8 @@ static void mmci_dma_setup(struct mmci_host *host)
304 const char *rxname, *txname; 347 const char *rxname, *txname;
305 dma_cap_mask_t mask; 348 dma_cap_mask_t mask;
306 349
307 if (!plat || !plat->dma_filter) { 350 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
308 dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); 351 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
309 return;
310 }
311 352
312 /* initialize pre request cookie */ 353 /* initialize pre request cookie */
313 host->next_data.cookie = 1; 354 host->next_data.cookie = 1;
@@ -316,30 +357,33 @@ static void mmci_dma_setup(struct mmci_host *host)
316 dma_cap_zero(mask); 357 dma_cap_zero(mask);
317 dma_cap_set(DMA_SLAVE, mask); 358 dma_cap_set(DMA_SLAVE, mask);
318 359
319 /* 360 if (plat && plat->dma_filter) {
320 * If only an RX channel is specified, the driver will 361 if (!host->dma_rx_channel && plat->dma_rx_param) {
321 * attempt to use it bidirectionally, however if it is 362 host->dma_rx_channel = dma_request_channel(mask,
322 * is specified but cannot be located, DMA will be disabled.
323 */
324 if (plat->dma_rx_param) {
325 host->dma_rx_channel = dma_request_channel(mask,
326 plat->dma_filter, 363 plat->dma_filter,
327 plat->dma_rx_param); 364 plat->dma_rx_param);
328 /* E.g if no DMA hardware is present */ 365 /* E.g if no DMA hardware is present */
329 if (!host->dma_rx_channel) 366 if (!host->dma_rx_channel)
330 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 367 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
331 } 368 }
332 369
333 if (plat->dma_tx_param) { 370 if (!host->dma_tx_channel && plat->dma_tx_param) {
334 host->dma_tx_channel = dma_request_channel(mask, 371 host->dma_tx_channel = dma_request_channel(mask,
335 plat->dma_filter, 372 plat->dma_filter,
336 plat->dma_tx_param); 373 plat->dma_tx_param);
337 if (!host->dma_tx_channel) 374 if (!host->dma_tx_channel)
338 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 375 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
339 } else { 376 }
340 host->dma_tx_channel = host->dma_rx_channel;
341 } 377 }
342 378
379 /*
380 * If only an RX channel is specified, the driver will
381 * attempt to use it bidirectionally, however if it is
382 * is specified but cannot be located, DMA will be disabled.
383 */
384 if (host->dma_rx_channel && !host->dma_tx_channel)
385 host->dma_tx_channel = host->dma_rx_channel;
386
343 if (host->dma_rx_channel) 387 if (host->dma_rx_channel)
344 rxname = dma_chan_name(host->dma_rx_channel); 388 rxname = dma_chan_name(host->dma_rx_channel);
345 else 389 else
@@ -552,7 +596,7 @@ static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
552 datactrl |= MCI_DPSM_DMAENABLE; 596 datactrl |= MCI_DPSM_DMAENABLE;
553 597
554 /* Trigger the DMA transfer */ 598 /* Trigger the DMA transfer */
555 writel(datactrl, host->base + MMCIDATACTRL); 599 mmci_write_datactrlreg(host, datactrl);
556 600
557 /* 601 /*
558 * Let the MMCI say when the data is ended and it's time 602 * Let the MMCI say when the data is ended and it's time
@@ -750,7 +794,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
750 irqmask = MCI_TXFIFOHALFEMPTYMASK; 794 irqmask = MCI_TXFIFOHALFEMPTYMASK;
751 } 795 }
752 796
753 writel(datactrl, base + MMCIDATACTRL); 797 mmci_write_datactrlreg(host, datactrl);
754 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 798 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
755 mmci_set_mask1(host, irqmask); 799 mmci_set_mask1(host, irqmask);
756} 800}
@@ -842,7 +886,7 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
842 /* The error clause is handled above, success! */ 886 /* The error clause is handled above, success! */
843 data->bytes_xfered = data->blksz * data->blocks; 887 data->bytes_xfered = data->blksz * data->blocks;
844 888
845 if (!data->stop) { 889 if (!data->stop || host->mrq->sbc) {
846 mmci_request_end(host, data->mrq); 890 mmci_request_end(host, data->mrq);
847 } else { 891 } else {
848 mmci_start_command(host, data->stop, 0); 892 mmci_start_command(host, data->stop, 0);
@@ -855,6 +899,7 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
855 unsigned int status) 899 unsigned int status)
856{ 900{
857 void __iomem *base = host->base; 901 void __iomem *base = host->base;
902 bool sbc = (cmd == host->mrq->sbc);
858 903
859 host->cmd = NULL; 904 host->cmd = NULL;
860 905
@@ -869,7 +914,7 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
869 cmd->resp[3] = readl(base + MMCIRESPONSE3); 914 cmd->resp[3] = readl(base + MMCIRESPONSE3);
870 } 915 }
871 916
872 if (!cmd->data || cmd->error) { 917 if ((!sbc && !cmd->data) || cmd->error) {
873 if (host->data) { 918 if (host->data) {
874 /* Terminate the DMA transfer */ 919 /* Terminate the DMA transfer */
875 if (dma_inprogress(host)) { 920 if (dma_inprogress(host)) {
@@ -878,7 +923,9 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
878 } 923 }
879 mmci_stop_data(host); 924 mmci_stop_data(host);
880 } 925 }
881 mmci_request_end(host, cmd->mrq); 926 mmci_request_end(host, host->mrq);
927 } else if (sbc) {
928 mmci_start_command(host, host->mrq->cmd, 0);
882 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 929 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
883 mmci_start_data(host, cmd->data); 930 mmci_start_data(host, cmd->data);
884 } 931 }
@@ -1119,7 +1166,10 @@ static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1119 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1166 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1120 mmci_start_data(host, mrq->data); 1167 mmci_start_data(host, mrq->data);
1121 1168
1122 mmci_start_command(host, mrq->cmd, 0); 1169 if (mrq->sbc)
1170 mmci_start_command(host, mrq->sbc, 0);
1171 else
1172 mmci_start_command(host, mrq->cmd, 0);
1123 1173
1124 spin_unlock_irqrestore(&host->lock, flags); 1174 spin_unlock_irqrestore(&host->lock, flags);
1125} 1175}
@@ -1143,9 +1193,10 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1143 if (!IS_ERR(mmc->supply.vmmc)) 1193 if (!IS_ERR(mmc->supply.vmmc))
1144 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1194 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1145 1195
1146 if (!IS_ERR(mmc->supply.vqmmc) && 1196 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1147 regulator_is_enabled(mmc->supply.vqmmc))
1148 regulator_disable(mmc->supply.vqmmc); 1197 regulator_disable(mmc->supply.vqmmc);
1198 host->vqmmc_enabled = false;
1199 }
1149 1200
1150 break; 1201 break;
1151 case MMC_POWER_UP: 1202 case MMC_POWER_UP:
@@ -1161,12 +1212,13 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1161 1212
1162 break; 1213 break;
1163 case MMC_POWER_ON: 1214 case MMC_POWER_ON:
1164 if (!IS_ERR(mmc->supply.vqmmc) && 1215 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1165 !regulator_is_enabled(mmc->supply.vqmmc)) {
1166 ret = regulator_enable(mmc->supply.vqmmc); 1216 ret = regulator_enable(mmc->supply.vqmmc);
1167 if (ret < 0) 1217 if (ret < 0)
1168 dev_err(mmc_dev(mmc), 1218 dev_err(mmc_dev(mmc),
1169 "failed to enable vqmmc regulator\n"); 1219 "failed to enable vqmmc regulator\n");
1220 else
1221 host->vqmmc_enabled = true;
1170 } 1222 }
1171 1223
1172 pwr |= MCI_PWR_ON; 1224 pwr |= MCI_PWR_ON;
@@ -1251,6 +1303,39 @@ static int mmci_get_cd(struct mmc_host *mmc)
1251 return status; 1303 return status;
1252} 1304}
1253 1305
1306static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1307{
1308 int ret = 0;
1309
1310 if (!IS_ERR(mmc->supply.vqmmc)) {
1311
1312 pm_runtime_get_sync(mmc_dev(mmc));
1313
1314 switch (ios->signal_voltage) {
1315 case MMC_SIGNAL_VOLTAGE_330:
1316 ret = regulator_set_voltage(mmc->supply.vqmmc,
1317 2700000, 3600000);
1318 break;
1319 case MMC_SIGNAL_VOLTAGE_180:
1320 ret = regulator_set_voltage(mmc->supply.vqmmc,
1321 1700000, 1950000);
1322 break;
1323 case MMC_SIGNAL_VOLTAGE_120:
1324 ret = regulator_set_voltage(mmc->supply.vqmmc,
1325 1100000, 1300000);
1326 break;
1327 }
1328
1329 if (ret)
1330 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1331
1332 pm_runtime_mark_last_busy(mmc_dev(mmc));
1333 pm_runtime_put_autosuspend(mmc_dev(mmc));
1334 }
1335
1336 return ret;
1337}
1338
1254static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1339static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1255{ 1340{
1256 struct mmci_host *host = dev_id; 1341 struct mmci_host *host = dev_id;
@@ -1260,13 +1345,14 @@ static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1260 return IRQ_HANDLED; 1345 return IRQ_HANDLED;
1261} 1346}
1262 1347
1263static const struct mmc_host_ops mmci_ops = { 1348static struct mmc_host_ops mmci_ops = {
1264 .request = mmci_request, 1349 .request = mmci_request,
1265 .pre_req = mmci_pre_request, 1350 .pre_req = mmci_pre_request,
1266 .post_req = mmci_post_request, 1351 .post_req = mmci_post_request,
1267 .set_ios = mmci_set_ios, 1352 .set_ios = mmci_set_ios,
1268 .get_ro = mmci_get_ro, 1353 .get_ro = mmci_get_ro,
1269 .get_cd = mmci_get_cd, 1354 .get_cd = mmci_get_cd,
1355 .start_signal_voltage_switch = mmci_sig_volt_switch,
1270}; 1356};
1271 1357
1272#ifdef CONFIG_OF 1358#ifdef CONFIG_OF
@@ -1362,16 +1448,15 @@ static int mmci_probe(struct amba_device *dev,
1362 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1448 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1363 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1449 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1364 1450
1365 host->clk = clk_get(&dev->dev, NULL); 1451 host->clk = devm_clk_get(&dev->dev, NULL);
1366 if (IS_ERR(host->clk)) { 1452 if (IS_ERR(host->clk)) {
1367 ret = PTR_ERR(host->clk); 1453 ret = PTR_ERR(host->clk);
1368 host->clk = NULL;
1369 goto host_free; 1454 goto host_free;
1370 } 1455 }
1371 1456
1372 ret = clk_prepare_enable(host->clk); 1457 ret = clk_prepare_enable(host->clk);
1373 if (ret) 1458 if (ret)
1374 goto clk_free; 1459 goto host_free;
1375 1460
1376 host->plat = plat; 1461 host->plat = plat;
1377 host->variant = variant; 1462 host->variant = variant;
@@ -1396,6 +1481,11 @@ static int mmci_probe(struct amba_device *dev,
1396 goto clk_disable; 1481 goto clk_disable;
1397 } 1482 }
1398 1483
1484 if (variant->busy_detect) {
1485 mmci_ops.card_busy = mmci_card_busy;
1486 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
1487 }
1488
1399 mmc->ops = &mmci_ops; 1489 mmc->ops = &mmci_ops;
1400 /* 1490 /*
1401 * The ARM and ST versions of the block have slightly different 1491 * The ARM and ST versions of the block have slightly different
@@ -1576,8 +1666,6 @@ static int mmci_probe(struct amba_device *dev,
1576 iounmap(host->base); 1666 iounmap(host->base);
1577 clk_disable: 1667 clk_disable:
1578 clk_disable_unprepare(host->clk); 1668 clk_disable_unprepare(host->clk);
1579 clk_free:
1580 clk_put(host->clk);
1581 host_free: 1669 host_free:
1582 mmc_free_host(mmc); 1670 mmc_free_host(mmc);
1583 rel_regions: 1671 rel_regions:
@@ -1623,7 +1711,6 @@ static int mmci_remove(struct amba_device *dev)
1623 1711
1624 iounmap(host->base); 1712 iounmap(host->base);
1625 clk_disable_unprepare(host->clk); 1713 clk_disable_unprepare(host->clk);
1626 clk_put(host->clk);
1627 1714
1628 mmc_free_host(mmc); 1715 mmc_free_host(mmc);
1629 1716
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 1f33ad5333a0..69080fab6375 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -94,6 +94,7 @@
94/* Extended status bits for the ST Micro variants */ 94/* Extended status bits for the ST Micro variants */
95#define MCI_ST_SDIOIT (1 << 22) 95#define MCI_ST_SDIOIT (1 << 22)
96#define MCI_ST_CEATAEND (1 << 23) 96#define MCI_ST_CEATAEND (1 << 23)
97#define MCI_ST_CARDBUSY (1 << 24)
97 98
98#define MMCICLEAR 0x038 99#define MMCICLEAR 0x038
99#define MCI_CMDCRCFAILCLR (1 << 0) 100#define MCI_CMDCRCFAILCLR (1 << 0)
@@ -110,6 +111,7 @@
110/* Extended status bits for the ST Micro variants */ 111/* Extended status bits for the ST Micro variants */
111#define MCI_ST_SDIOITC (1 << 22) 112#define MCI_ST_SDIOITC (1 << 22)
112#define MCI_ST_CEATAENDC (1 << 23) 113#define MCI_ST_CEATAENDC (1 << 23)
114#define MCI_ST_BUSYENDC (1 << 24)
113 115
114#define MMCIMASK0 0x03c 116#define MMCIMASK0 0x03c
115#define MCI_CMDCRCFAILMASK (1 << 0) 117#define MCI_CMDCRCFAILMASK (1 << 0)
@@ -183,6 +185,8 @@ struct mmci_host {
183 unsigned int cclk; 185 unsigned int cclk;
184 u32 pwr_reg; 186 u32 pwr_reg;
185 u32 clk_reg; 187 u32 clk_reg;
188 u32 datactrl_reg;
189 bool vqmmc_enabled;
186 struct mmci_platform_data *plat; 190 struct mmci_platform_data *plat;
187 struct variant_data *variant; 191 struct variant_data *variant;
188 192