diff options
author | Shawn Guo <shawn.guo@linaro.org> | 2013-01-21 06:02:24 -0500 |
---|---|---|
committer | Chris Ball <cjb@laptop.org> | 2013-02-24 14:37:01 -0500 |
commit | 69f5469822132c4ae0637eef2980dbaec5bb2b31 (patch) | |
tree | b6bc7696a8fbb558d1ef65ea64397a99372bc4ab /drivers/mmc | |
parent | 881d926d9d0bd2eb50f8f90c993bc403853382ce (diff) |
mmc: sdhci-esdhc-imx: separate transfer mode from command write for usdhc
The combining of SDHCI_TRANSFER_MODE and SDHCI_COMMAND writes is only
required for esdhc, but not necessarily for usdhc. Different from
esdhc where the bits for transfer mode and command are all in the same
register CMD_XFR_TYP, usdhc has a newly introduced register MIX_CTRL
to hold transfer mode bits. So it makes more sense to separate transfer
mode from command write for usdhc.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r-- | drivers/mmc/host/sdhci-esdhc-imx.c | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 370c052f4293..48832c567f72 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c | |||
@@ -239,10 +239,6 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) | |||
239 | 239 | ||
240 | switch (reg) { | 240 | switch (reg) { |
241 | case SDHCI_TRANSFER_MODE: | 241 | case SDHCI_TRANSFER_MODE: |
242 | /* | ||
243 | * Postpone this write, we must do it together with a | ||
244 | * command write that is down below. | ||
245 | */ | ||
246 | if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) | 242 | if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
247 | && (host->cmd->opcode == SD_IO_RW_EXTENDED) | 243 | && (host->cmd->opcode == SD_IO_RW_EXTENDED) |
248 | && (host->cmd->data->blocks > 1) | 244 | && (host->cmd->data->blocks > 1) |
@@ -252,7 +248,18 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) | |||
252 | v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; | 248 | v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; |
253 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | 249 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); |
254 | } | 250 | } |
255 | imx_data->scratchpad = val; | 251 | |
252 | if (is_imx6q_usdhc(imx_data)) { | ||
253 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | ||
254 | m = val | (m & 0xffff0000); | ||
255 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | ||
256 | } else { | ||
257 | /* | ||
258 | * Postpone this write, we must do it together with a | ||
259 | * command write that is down below. | ||
260 | */ | ||
261 | imx_data->scratchpad = val; | ||
262 | } | ||
256 | return; | 263 | return; |
257 | case SDHCI_COMMAND: | 264 | case SDHCI_COMMAND: |
258 | if ((host->cmd->opcode == MMC_STOP_TRANSMISSION || | 265 | if ((host->cmd->opcode == MMC_STOP_TRANSMISSION || |
@@ -260,16 +267,12 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) | |||
260 | (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) | 267 | (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) |
261 | val |= SDHCI_CMD_ABORTCMD; | 268 | val |= SDHCI_CMD_ABORTCMD; |
262 | 269 | ||
263 | if (is_imx6q_usdhc(imx_data)) { | 270 | if (is_imx6q_usdhc(imx_data)) |
264 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | ||
265 | m = imx_data->scratchpad | (m & 0xffff0000); | ||
266 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | ||
267 | writel(val << 16, | 271 | writel(val << 16, |
268 | host->ioaddr + SDHCI_TRANSFER_MODE); | 272 | host->ioaddr + SDHCI_TRANSFER_MODE); |
269 | } else { | 273 | else |
270 | writel(val << 16 | imx_data->scratchpad, | 274 | writel(val << 16 | imx_data->scratchpad, |
271 | host->ioaddr + SDHCI_TRANSFER_MODE); | 275 | host->ioaddr + SDHCI_TRANSFER_MODE); |
272 | } | ||
273 | return; | 276 | return; |
274 | case SDHCI_BLOCK_SIZE: | 277 | case SDHCI_BLOCK_SIZE: |
275 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); | 278 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); |