Merge branch 'upstream'

13 files changed, 3496 insertions, 53 deletions

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 3f5d77f633fa..003b077c2324 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -60,6 +60,17 @@ config MMC_SDHCI
 
           If unsure, say N.
 
+config MMC_OMAP
+        tristate "TI OMAP Multimedia Card Interface support"
+        depends on ARCH_OMAP && MMC
+        select TPS65010 if MACH_OMAP_H2
+        help
+          This selects the TI OMAP Multimedia card Interface.
+          If you have an OMAP board with a Multimedia Card slot,
+          say Y or M here.
+
+          If unsure, say N.
+
 config MMC_WBSD
         tristate "Winbond W83L51xD SD/MMC Card Interface support"
         depends on MMC && ISA_DMA_API
@@ -80,4 +91,22 @@ config MMC_AU1X
 
           If unsure, say N.
 
+config MMC_AT91RM9200
+        tristate "AT91RM9200 SD/MMC Card Interface support"
+        depends on ARCH_AT91RM9200 && MMC
+        help
+          This selects the AT91RM9200 MCI controller.
+
+          If unsure, say N.
+
+config MMC_IMX
+        tristate "Motorola i.MX Multimedia Card Interface support"
+        depends on ARCH_IMX && MMC
+        help
+          This selects the Motorola i.MX Multimedia card Interface.
+          If you have a i.MX platform with a Multimedia Card slot,
+          say Y or M here.
+
+          If unsure, say N.
+
 endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 769d545284a4..d2957e35cc6f 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -17,8 +17,15 @@ obj-$(CONFIG_MMC_BLOCK)		+= mmc_block.o
 #
 obj-$(CONFIG_MMC_ARMMMCI)       += mmci.o
 obj-$(CONFIG_MMC_PXA)           += pxamci.o
+obj-$(CONFIG_MMC_IMX)           += imxmmc.o
 obj-$(CONFIG_MMC_SDHCI)         += sdhci.o
 obj-$(CONFIG_MMC_WBSD)          += wbsd.o
 obj-$(CONFIG_MMC_AU1X)          += au1xmmc.o
+obj-$(CONFIG_MMC_OMAP)          += omap.o
+obj-$(CONFIG_MMC_AT91RM9200)    += at91_mci.o
 
 mmc_core-y := mmc.o mmc_queue.o mmc_sysfs.o
+
+ifeq ($(CONFIG_MMC_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
diff --git a/drivers/mmc/at91_mci.c b/drivers/mmc/at91_mci.c
new file mode 100644
index 000000000000..6061c2d101a0
--- /dev/null
+++ b/drivers/mmc/at91_mci.c
@@ -0,0 +1,988 @@
+/*
+ *  linux/drivers/mmc/at91_mci.c - ATMEL AT91RM9200 MCI Driver
+ *
+ *  Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
+ *
+ *  Copyright (C) 2006 Malcolm Noyes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+   This is the AT91RM9200 MCI driver that has been tested with both MMC cards
+   and SD-cards.  Boards that support write protect are now supported.
+   The CCAT91SBC001 board does not support SD cards.
+
+   The three entry points are at91_mci_request, at91_mci_set_ios
+   and at91_mci_get_ro.
+
+   SET IOS
+     This configures the device to put it into the correct mode and clock speed
+     required.
+
+   MCI REQUEST
+     MCI request processes the commands sent in the mmc_request structure. This
+     can consist of a processing command and a stop command in the case of
+     multiple block transfers.
+
+     There are three main types of request, commands, reads and writes.
+
+     Commands are straight forward. The command is submitted to the controller and
+     the request function returns. When the controller generates an interrupt to indicate
+     the command is finished, the response to the command are read and the mmc_request_done
+     function called to end the request.
+
+     Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
+     controller to manage the transfers.
+
+     A read is done from the controller directly to the scatterlist passed in from the request.
+     Due to a bug in the controller, when a read is completed, all the words are byte
+     swapped in the scatterlist buffers.
+
+     The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
+
+     A write is slightly different in that the bytes to write are read from the scatterlist
+     into a dma memory buffer (this is in case the source buffer should be read only). The
+     entire write buffer is then done from this single dma memory buffer.
+
+     The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
+
+   GET RO
+     Gets the status of the write protect pin, if available.
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+
+#include <linux/mmc/host.h>
+#include <linux/mmc/protocol.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/mmc.h>
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91rm9200_mci.h>
+#include <asm/arch/at91rm9200_pdc.h>
+
+#define DRIVER_NAME "at91_mci"
+
+#undef  SUPPORT_4WIRE
+
+#ifdef CONFIG_MMC_DEBUG
+#define DBG(fmt...)     \
+        printk(fmt)
+#else
+#define DBG(fmt...)     do { } while (0)
+#endif
+
+static struct clk *mci_clk;
+
+#define FL_SENT_COMMAND (1 << 0)
+#define FL_SENT_STOP (1 << 1)
+
+
+
+/*
+ * Read from a MCI register.
+ */
+static inline unsigned long at91_mci_read(unsigned int reg)
+{
+        void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
+
+        return __raw_readl(mci_base + reg);
+}
+
+/*
+ * Write to a MCI register.
+ */
+static inline void at91_mci_write(unsigned int reg, unsigned long value)
+{
+        void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
+
+        __raw_writel(value, mci_base + reg);
+}
+
+/*
+ * Low level type for this driver
+ */
+struct at91mci_host
+{
+        struct mmc_host *mmc;
+        struct mmc_command *cmd;
+        struct mmc_request *request;
+
+        struct at91_mmc_data *board;
+        int present;
+
+        /*
+         * Flag indicating when the command has been sent. This is used to
+         * work out whether or not to send the stop
+         */
+        unsigned int flags;
+        /* flag for current bus settings */
+        u32 bus_mode;
+
+        /* DMA buffer used for transmitting */
+        unsigned int* buffer;
+        dma_addr_t physical_address;
+        unsigned int total_length;
+
+        /* Latest in the scatterlist that has been enabled for transfer, but not freed */
+        int in_use_index;
+
+        /* Latest in the scatterlist that has been enabled for transfer */
+        int transfer_index;
+};
+
+/*
+ * Copy from sg to a dma block - used for transfers
+ */
+static inline void at91mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
+{
+        unsigned int len, i, size;
+        unsigned *dmabuf = host->buffer;
+
+        size = host->total_length;
+        len = data->sg_len;
+
+        /*
+         * Just loop through all entries. Size might not
+         * be the entire list though so make sure that
+         * we do not transfer too much.
+         */
+        for (i = 0; i < len; i++) {
+                struct scatterlist *sg;
+                int amount;
+                int index;
+                unsigned int *sgbuffer;
+
+                sg = &data->sg[i];
+
+                sgbuffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
+                amount = min(size, sg->length);
+                size -= amount;
+                amount /= 4;
+
+                for (index = 0; index < amount; index++)
+                        *dmabuf++ = swab32(sgbuffer[index]);
+
+                kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
+
+                if (size == 0)
+                        break;
+        }
+
+        /*
+         * Check that we didn't get a request to transfer
+         * more data than can fit into the SG list.
+         */
+        BUG_ON(size != 0);
+}
+
+/*
+ * Prepare a dma read
+ */
+static void at91mci_pre_dma_read(struct at91mci_host *host)
+{
+        int i;
+        struct scatterlist *sg;
+        struct mmc_command *cmd;
+        struct mmc_data *data;
+
+        DBG("pre dma read\n");
+
+        cmd = host->cmd;
+        if (!cmd) {
+                DBG("no command\n");
+                return;
+        }
+
+        data = cmd->data;
+        if (!data) {
+                DBG("no data\n");
+                return;
+        }
+
+        for (i = 0; i < 2; i++) {
+                /* nothing left to transfer */
+                if (host->transfer_index >= data->sg_len) {
+                        DBG("Nothing left to transfer (index = %d)\n", host->transfer_index);
+                        break;
+                }
+
+                /* Check to see if this needs filling */
+                if (i == 0) {
+                        if (at91_mci_read(AT91_PDC_RCR) != 0) {
+                                DBG("Transfer active in current\n");
+                                continue;
+                        }
+                }
+                else {
+                        if (at91_mci_read(AT91_PDC_RNCR) != 0) {
+                                DBG("Transfer active in next\n");
+                                continue;
+                        }
+                }
+
+                /* Setup the next transfer */
+                DBG("Using transfer index %d\n", host->transfer_index);
+
+                sg = &data->sg[host->transfer_index++];
+                DBG("sg = %p\n", sg);
+
+                sg->dma_address = dma_map_page(NULL, sg->page, sg->offset, sg->length, DMA_FROM_DEVICE);
+
+                DBG("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
+
+                if (i == 0) {
+                        at91_mci_write(AT91_PDC_RPR, sg->dma_address);
+                        at91_mci_write(AT91_PDC_RCR, sg->length / 4);
+                }
+                else {
+                        at91_mci_write(AT91_PDC_RNPR, sg->dma_address);
+                        at91_mci_write(AT91_PDC_RNCR, sg->length / 4);
+                }
+        }
+
+        DBG("pre dma read done\n");
+}
+
+/*
+ * Handle after a dma read
+ */
+static void at91mci_post_dma_read(struct at91mci_host *host)
+{
+        struct mmc_command *cmd;
+        struct mmc_data *data;
+
+        DBG("post dma read\n");
+
+        cmd = host->cmd;
+        if (!cmd) {
+                DBG("no command\n");
+                return;
+        }
+
+        data = cmd->data;
+        if (!data) {
+                DBG("no data\n");
+                return;
+        }
+
+        while (host->in_use_index < host->transfer_index) {
+                unsigned int *buffer;
+                int index;
+                int len;
+
+                struct scatterlist *sg;
+
+                DBG("finishing index %d\n", host->in_use_index);
+
+                sg = &data->sg[host->in_use_index++];
+
+                DBG("Unmapping page %08X\n", sg->dma_address);
+
+                dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE);
+
+                /* Swap the contents of the buffer */
+                buffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
+                DBG("buffer = %p, length = %d\n", buffer, sg->length);
+
+                data->bytes_xfered += sg->length;
+
+                len = sg->length / 4;
+
+                for (index = 0; index < len; index++) {
+                        buffer[index] = swab32(buffer[index]);
+                }
+                kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
+                flush_dcache_page(sg->page);
+        }
+
+        /* Is there another transfer to trigger? */
+        if (host->transfer_index < data->sg_len)
+                at91mci_pre_dma_read(host);
+        else {
+                at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF);
+                at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
+        }
+
+        DBG("post dma read done\n");
+}
+
+/*
+ * Handle transmitted data
+ */
+static void at91_mci_handle_transmitted(struct at91mci_host *host)
+{
+        struct mmc_command *cmd;
+        struct mmc_data *data;
+
+        DBG("Handling the transmit\n");
+
+        /* Disable the transfer */
+        at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
+
+        /* Now wait for cmd ready */
+        at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE);
+        at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
+
+        cmd = host->cmd;
+        if (!cmd) return;
+
+        data = cmd->data;
+        if (!data) return;
+
+        data->bytes_xfered = host->total_length;
+}
+
+/*
+ * Enable the controller
+ */
+static void at91_mci_enable(void)
+{
+        at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
+        at91_mci_write(AT91_MCI_IDR, 0xFFFFFFFF);
+        at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
+        at91_mci_write(AT91_MCI_MR, 0x834A);
+        at91_mci_write(AT91_MCI_SDCR, 0x0);
+}
+
+/*
+ * Disable the controller
+ */
+static void at91_mci_disable(void)
+{
+        at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
+}
+
+/*
+ * Send a command
+ * return the interrupts to enable
+ */
+static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
+{
+        unsigned int cmdr, mr;
+        unsigned int block_length;
+        struct mmc_data *data = cmd->data;
+
+        unsigned int blocks;
+        unsigned int ier = 0;
+
+        host->cmd = cmd;
+
+        /* Not sure if this is needed */
+#if 0
+        if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
+                DBG("Clearing timeout\n");
+                at91_mci_write(AT91_MCI_ARGR, 0);
+                at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD);
+                while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
+                        /* spin */
+                        DBG("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR));
+                }
+        }
+#endif
+        cmdr = cmd->opcode;
+
+        if (mmc_resp_type(cmd) == MMC_RSP_NONE)
+                cmdr |= AT91_MCI_RSPTYP_NONE;
+        else {
+                /* if a response is expected then allow maximum response latancy */
+                cmdr |= AT91_MCI_MAXLAT;
+                /* set 136 bit response for R2, 48 bit response otherwise */
+                if (mmc_resp_type(cmd) == MMC_RSP_R2)
+                        cmdr |= AT91_MCI_RSPTYP_136;
+                else
+                        cmdr |= AT91_MCI_RSPTYP_48;
+        }
+
+        if (data) {
+                block_length = 1 << data->blksz_bits;
+                blocks = data->blocks;
+
+                /* always set data start - also set direction flag for read */
+                if (data->flags & MMC_DATA_READ)
+                        cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
+                else if (data->flags & MMC_DATA_WRITE)
+                        cmdr |= AT91_MCI_TRCMD_START;
+
+                if (data->flags & MMC_DATA_STREAM)
+                        cmdr |= AT91_MCI_TRTYP_STREAM;
+                if (data->flags & MMC_DATA_MULTI)
+                        cmdr |= AT91_MCI_TRTYP_MULTIPLE;
+        }
+        else {
+                block_length = 0;
+                blocks = 0;
+        }
+
+        if (cmd->opcode == MMC_STOP_TRANSMISSION)
+                cmdr |= AT91_MCI_TRCMD_STOP;
+
+        if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
+                cmdr |= AT91_MCI_OPDCMD;
+
+        /*
+         * Set the arguments and send the command
+         */
+        DBG("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08lX)\n",
+                cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR));
+
+        if (!data) {
+                at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
+                at91_mci_write(AT91_PDC_RPR, 0);
+                at91_mci_write(AT91_PDC_RCR, 0);
+                at91_mci_write(AT91_PDC_RNPR, 0);
+                at91_mci_write(AT91_PDC_RNCR, 0);
+                at91_mci_write(AT91_PDC_TPR, 0);
+                at91_mci_write(AT91_PDC_TCR, 0);
+                at91_mci_write(AT91_PDC_TNPR, 0);
+                at91_mci_write(AT91_PDC_TNCR, 0);
+
+                at91_mci_write(AT91_MCI_ARGR, cmd->arg);
+                at91_mci_write(AT91_MCI_CMDR, cmdr);
+                return AT91_MCI_CMDRDY;
+        }
+
+        mr = at91_mci_read(AT91_MCI_MR) & 0x7fff;       /* zero block length and PDC mode */
+        at91_mci_write(AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE);
+
+        /*
+         * Disable the PDC controller
+         */
+        at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
+
+        if (cmdr & AT91_MCI_TRCMD_START) {
+                data->bytes_xfered = 0;
+                host->transfer_index = 0;
+                host->in_use_index = 0;
+                if (cmdr & AT91_MCI_TRDIR) {
+                        /*
+                         * Handle a read
+                         */
+                        host->buffer = NULL;
+                        host->total_length = 0;
+
+                        at91mci_pre_dma_read(host);
+                        ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
+                }
+                else {
+                        /*
+                         * Handle a write
+                         */
+                        host->total_length = block_length * blocks;
+                        host->buffer = dma_alloc_coherent(NULL,
+                                                  host->total_length,
+                                                  &host->physical_address, GFP_KERNEL);
+
+                        at91mci_sg_to_dma(host, data);
+
+                        DBG("Transmitting %d bytes\n", host->total_length);
+
+                        at91_mci_write(AT91_PDC_TPR, host->physical_address);
+                        at91_mci_write(AT91_PDC_TCR, host->total_length / 4);
+                        ier = AT91_MCI_TXBUFE;
+                }
+        }
+
+        /*
+         * Send the command and then enable the PDC - not the other way round as
+         * the data sheet says
+         */
+
+        at91_mci_write(AT91_MCI_ARGR, cmd->arg);
+        at91_mci_write(AT91_MCI_CMDR, cmdr);
+
+        if (cmdr & AT91_MCI_TRCMD_START) {
+                if (cmdr & AT91_MCI_TRDIR)
+                        at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN);
+                else
+                        at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN);
+        }
+        return ier;
+}
+
+/*
+ * Wait for a command to complete
+ */
+static void at91mci_process_command(struct at91mci_host *host, struct mmc_command *cmd)
+{
+        unsigned int ier;
+
+        ier = at91_mci_send_command(host, cmd);
+
+        DBG("setting ier to %08X\n", ier);
+
+        /* Stop on errors or the required value */
+        at91_mci_write(AT91_MCI_IER, 0xffff0000 | ier);
+}
+
+/*
+ * Process the next step in the request
+ */
+static void at91mci_process_next(struct at91mci_host *host)
+{
+        if (!(host->flags & FL_SENT_COMMAND)) {
+                host->flags |= FL_SENT_COMMAND;
+                at91mci_process_command(host, host->request->cmd);
+        }
+        else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
+                host->flags |= FL_SENT_STOP;
+                at91mci_process_command(host, host->request->stop);
+        }
+        else
+                mmc_request_done(host->mmc, host->request);
+}
+
+/*
+ * Handle a command that has been completed
+ */
+static void at91mci_completed_command(struct at91mci_host *host)
+{
+        struct mmc_command *cmd = host->cmd;
+        unsigned int status;
+
+        at91_mci_write(AT91_MCI_IDR, 0xffffffff);
+
+        cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0));
+        cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1));
+        cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2));
+        cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3));
+
+        if (host->buffer) {
+                dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address);
+                host->buffer = NULL;
+        }
+
+        status = at91_mci_read(AT91_MCI_SR);
+
+        DBG("Status = %08X [%08X %08X %08X %08X]\n",
+                 status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+
+        if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE |
+                        AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE |
+                        AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) {
+                if ((status & AT91_MCI_RCRCE) &&
+                        ((cmd->opcode == MMC_SEND_OP_COND) || (cmd->opcode == SD_APP_OP_COND))) {
+                        cmd->error = MMC_ERR_NONE;
+                }
+                else {
+                        if (status & (AT91_MCI_RTOE | AT91_MCI_DTOE))
+                                cmd->error = MMC_ERR_TIMEOUT;
+                        else if (status & (AT91_MCI_RCRCE | AT91_MCI_DCRCE))
+                                cmd->error = MMC_ERR_BADCRC;
+                        else if (status & (AT91_MCI_OVRE | AT91_MCI_UNRE))
+                                cmd->error = MMC_ERR_FIFO;
+                        else
+                                cmd->error = MMC_ERR_FAILED;
+
+                        DBG("Error detected and set to %d (cmd = %d, retries = %d)\n",
+                                 cmd->error, cmd->opcode, cmd->retries);
+                }
+        }
+        else
+                cmd->error = MMC_ERR_NONE;
+
+        at91mci_process_next(host);
+}
+
+/*
+ * Handle an MMC request
+ */
+static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+        struct at91mci_host *host = mmc_priv(mmc);
+        host->request = mrq;
+        host->flags = 0;
+
+        at91mci_process_next(host);
+}
+
+/*
+ * Set the IOS
+ */
+static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+        int clkdiv;
+        struct at91mci_host *host = mmc_priv(mmc);
+        unsigned long at91_master_clock = clk_get_rate(mci_clk);
+
+        DBG("Clock %uHz, busmode %u, powermode %u, Vdd %u\n",
+                ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);
+
+        if (host)
+                host->bus_mode = ios->bus_mode;
+        else
+                printk("MMC: No host for bus_mode\n");
+
+        if (ios->clock == 0) {
+                /* Disable the MCI controller */
+                at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS);
+                clkdiv = 0;
+        }
+        else {
+                /* Enable the MCI controller */
+                at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
+
+                if ((at91_master_clock % (ios->clock * 2)) == 0)
+                        clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
+                else
+                        clkdiv = (at91_master_clock / ios->clock) / 2;
+
+                DBG("clkdiv = %d. mcck = %ld\n", clkdiv,
+                        at91_master_clock / (2 * (clkdiv + 1)));
+        }
+        if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
+                DBG("MMC: Setting controller bus width to 4\n");
+                at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
+        }
+        else {
+                DBG("MMC: Setting controller bus width to 1\n");
+                at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
+        }
+
+        /* Set the clock divider */
+        at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
+
+        /* maybe switch power to the card */
+        if (host && host->board->vcc_pin) {
+                switch (ios->power_mode) {
+                        case MMC_POWER_OFF:
+                                at91_set_gpio_output(host->board->vcc_pin, 0);
+                                break;
+                        case MMC_POWER_UP:
+                        case MMC_POWER_ON:
+                                at91_set_gpio_output(host->board->vcc_pin, 1);
+                                break;
+                }
+        }
+}
+
+/*
+ * Handle an interrupt
+ */
+static irqreturn_t at91_mci_irq(int irq, void *devid, struct pt_regs *regs)
+{
+        struct at91mci_host *host = devid;
+        int completed = 0;
+
+        unsigned int int_status;
+
+        if (host == NULL)
+                return IRQ_HANDLED;
+
+        int_status = at91_mci_read(AT91_MCI_SR);
+        DBG("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(AT91_MCI_IMR),
+                int_status & at91_mci_read(AT91_MCI_IMR));
+
+        if ((int_status & at91_mci_read(AT91_MCI_IMR)) & 0xffff0000)
+                completed = 1;
+
+        int_status &= at91_mci_read(AT91_MCI_IMR);
+
+        if (int_status & AT91_MCI_UNRE)
+                DBG("MMC: Underrun error\n");
+        if (int_status & AT91_MCI_OVRE)
+                DBG("MMC: Overrun error\n");
+        if (int_status & AT91_MCI_DTOE)
+                DBG("MMC: Data timeout\n");
+        if (int_status & AT91_MCI_DCRCE)
+                DBG("MMC: CRC error in data\n");
+        if (int_status & AT91_MCI_RTOE)
+                DBG("MMC: Response timeout\n");
+        if (int_status & AT91_MCI_RENDE)
+                DBG("MMC: Response end bit error\n");
+        if (int_status & AT91_MCI_RCRCE)
+                DBG("MMC: Response CRC error\n");
+        if (int_status & AT91_MCI_RDIRE)
+                DBG("MMC: Response direction error\n");
+        if (int_status & AT91_MCI_RINDE)
+                DBG("MMC: Response index error\n");
+
+        /* Only continue processing if no errors */
+        if (!completed) {
+                if (int_status & AT91_MCI_TXBUFE) {
+                        DBG("TX buffer empty\n");
+                        at91_mci_handle_transmitted(host);
+                }
+
+                if (int_status & AT91_MCI_RXBUFF) {
+                        DBG("RX buffer full\n");
+                        at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
+                }
+
+                if (int_status & AT91_MCI_ENDTX) {
+                        DBG("Transmit has ended\n");
+                }
+
+                if (int_status & AT91_MCI_ENDRX) {
+                        DBG("Receive has ended\n");
+                        at91mci_post_dma_read(host);
+                }
+
+                if (int_status & AT91_MCI_NOTBUSY) {
+                        DBG("Card is ready\n");
+                        at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
+                }
+
+                if (int_status & AT91_MCI_DTIP) {
+                        DBG("Data transfer in progress\n");
+                }
+
+                if (int_status & AT91_MCI_BLKE) {
+                        DBG("Block transfer has ended\n");
+                }
+
+                if (int_status & AT91_MCI_TXRDY) {
+                        DBG("Ready to transmit\n");
+                }
+
+                if (int_status & AT91_MCI_RXRDY) {
+                        DBG("Ready to receive\n");
+                }
+
+                if (int_status & AT91_MCI_CMDRDY) {
+                        DBG("Command ready\n");
+                        completed = 1;
+                }
+        }
+        at91_mci_write(AT91_MCI_IDR, int_status);
+
+        if (completed) {
+                DBG("Completed command\n");
+                at91_mci_write(AT91_MCI_IDR, 0xffffffff);
+                at91mci_completed_command(host);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t at91_mmc_det_irq(int irq, void *_host, struct pt_regs *regs)
+{
+        struct at91mci_host *host = _host;
+        int present = !at91_get_gpio_value(irq);
+
+        /*
+         * we expect this irq on both insert and remove,
+         * and use a short delay to debounce.
+         */
+        if (present != host->present) {
+                host->present = present;
+                DBG("%s: card %s\n", mmc_hostname(host->mmc),
+                        present ? "insert" : "remove");
+                if (!present) {
+                        DBG("****** Resetting SD-card bus width ******\n");
+                        at91_mci_write(AT91_MCI_SDCR, 0);
+                }
+                mmc_detect_change(host->mmc, msecs_to_jiffies(100));
+        }
+        return IRQ_HANDLED;
+}
+
+int at91_mci_get_ro(struct mmc_host *mmc)
+{
+        int read_only = 0;
+        struct at91mci_host *host = mmc_priv(mmc);
+
+        if (host->board->wp_pin) {
+                read_only = at91_get_gpio_value(host->board->wp_pin);
+                printk(KERN_WARNING "%s: card is %s\n", mmc_hostname(mmc),
+                                (read_only ? "read-only" : "read-write") );
+        }
+        else {
+                printk(KERN_WARNING "%s: host does not support reading read-only "
+                                "switch.  Assuming write-enable.\n", mmc_hostname(mmc));
+        }
+        return read_only;
+}
+
+static struct mmc_host_ops at91_mci_ops = {
+        .request        = at91_mci_request,
+        .set_ios        = at91_mci_set_ios,
+        .get_ro         = at91_mci_get_ro,
+};
+
+/*
+ * Probe for the device
+ */
+static int at91_mci_probe(struct platform_device *pdev)
+{
+        struct mmc_host *mmc;
+        struct at91mci_host *host;
+        int ret;
+
+        DBG("Probe MCI devices\n");
+        at91_mci_disable();
+        at91_mci_enable();
+
+        mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
+        if (!mmc) {
+                DBG("Failed to allocate mmc host\n");
+                return -ENOMEM;
+        }
+
+        mmc->ops = &at91_mci_ops;
+        mmc->f_min = 375000;
+        mmc->f_max = 25000000;
+        mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+        host = mmc_priv(mmc);
+        host->mmc = mmc;
+        host->buffer = NULL;
+        host->bus_mode = 0;
+        host->board = pdev->dev.platform_data;
+        if (host->board->wire4) {
+#ifdef SUPPORT_4WIRE
+                mmc->caps |= MMC_CAP_4_BIT_DATA;
+#else
+                printk("MMC: 4 wire bus mode not supported by this driver - using 1 wire\n");
+#endif
+        }
+
+        /*
+         * Get Clock
+         */
+        mci_clk = clk_get(&pdev->dev, "mci_clk");
+        if (!mci_clk) {
+                printk(KERN_ERR "AT91 MMC: no clock defined.\n");
+                return -ENODEV;
+        }
+        clk_enable(mci_clk);                    /* Enable the peripheral clock */
+
+        /*
+         * Allocate the MCI interrupt
+         */
+        ret = request_irq(AT91_ID_MCI, at91_mci_irq, SA_SHIRQ, DRIVER_NAME, host);
+        if (ret) {
+                DBG("Failed to request MCI interrupt\n");
+                return ret;
+        }
+
+        platform_set_drvdata(pdev, mmc);
+
+        /*
+         * Add host to MMC layer
+         */
+        if (host->board->det_pin)
+                host->present = !at91_get_gpio_value(host->board->det_pin);
+        else
+                host->present = -1;
+
+        mmc_add_host(mmc);
+
+        /*
+         * monitor card insertion/removal if we can
+         */
+        if (host->board->det_pin) {
+                ret = request_irq(host->board->det_pin, at91_mmc_det_irq,
+                                SA_SAMPLE_RANDOM, DRIVER_NAME, host);
+                if (ret)
+                        DBG("couldn't allocate MMC detect irq\n");
+        }
+
+        DBG(KERN_INFO "Added MCI driver\n");
+
+        return 0;
+}
+
+/*
+ * Remove a device
+ */
+static int at91_mci_remove(struct platform_device *pdev)
+{
+        struct mmc_host *mmc = platform_get_drvdata(pdev);
+        struct at91mci_host *host;
+
+        if (!mmc)
+                return -1;
+
+        host = mmc_priv(mmc);
+
+        if (host->present != -1) {
+                free_irq(host->board->det_pin, host);
+                cancel_delayed_work(&host->mmc->detect);
+        }
+
+        mmc_remove_host(mmc);
+        at91_mci_disable();
+        free_irq(AT91_ID_MCI, host);
+        mmc_free_host(mmc);
+
+        clk_disable(mci_clk);                           /* Disable the peripheral clock */
+        clk_put(mci_clk);
+
+        platform_set_drvdata(pdev, NULL);
+
+        DBG("Removed\n");
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
+{
+        struct mmc_host *mmc = platform_get_drvdata(pdev);
+        int ret = 0;
+
+        if (mmc)
+                ret = mmc_suspend_host(mmc, state);
+
+        return ret;
+}
+
+static int at91_mci_resume(struct platform_device *pdev)
+{
+        struct mmc_host *mmc = platform_get_drvdata(pdev);
+        int ret = 0;
+
+        if (mmc)
+                ret = mmc_resume_host(mmc);
+
+        return ret;
+}
+#else
+#define at91_mci_suspend        NULL
+#define at91_mci_resume         NULL
+#endif
+
+static struct platform_driver at91_mci_driver = {
+        .probe          = at91_mci_probe,
+        .remove         = at91_mci_remove,
+        .suspend        = at91_mci_suspend,
+        .resume         = at91_mci_resume,
+        .driver         = {
+                .name   = DRIVER_NAME,
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init at91_mci_init(void)
+{
+        return platform_driver_register(&at91_mci_driver);
+}
+
+static void __exit at91_mci_exit(void)
+{
+        platform_driver_unregister(&at91_mci_driver);
+}
+
+module_init(at91_mci_init);
+module_exit(at91_mci_exit);
+
+MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver");
+MODULE_AUTHOR("Nick Randell");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/au1xmmc.c b/drivers/mmc/au1xmmc.c
index 85e89c77bdea..c0326bbc5f28 100644
--- a/drivers/mmc/au1xmmc.c
+++ b/drivers/mmc/au1xmmc.c
@@ -56,12 +56,11 @@
 #define DRIVER_NAME "au1xxx-mmc"
 
 /* Set this to enable special debugging macros */
-/* #define MMC_DEBUG */
 
-#ifdef MMC_DEBUG
-#define DEBUG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
+#ifdef DEBUG
+#define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
 #else
-#define DEBUG(fmt, idx, args...)
+#define DBG(fmt, idx, args...)
 #endif
 
 const struct {
@@ -424,18 +423,18 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host)
                         break;
 
                 if (status & SD_STATUS_RC) {
-                        DEBUG("RX CRC Error [%d + %d].\n", host->id,
+                        DBG("RX CRC Error [%d + %d].\n", host->id,
                                         host->pio.len, count);
                         break;
                 }
 
                 if (status & SD_STATUS_RO) {
-                        DEBUG("RX Overrun [%d + %d]\n", host->id,
+                        DBG("RX Overrun [%d + %d]\n", host->id,
                                         host->pio.len, count);
                         break;
                 }
                 else if (status & SD_STATUS_RU) {
-                        DEBUG("RX Underrun [%d + %d]\n", host->id,
+                        DBG("RX Underrun [%d + %d]\n", host->id,
                                         host->pio.len,  count);
                         break;
                 }
@@ -721,7 +720,7 @@ static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
 {
         struct au1xmmc_host *host = mmc_priv(mmc);
 
-        DEBUG("set_ios (power=%u, clock=%uHz, vdd=%u, mode=%u)\n",
+        DBG("set_ios (power=%u, clock=%uHz, vdd=%u, mode=%u)\n",
               host->id, ios->power_mode, ios->clock, ios->vdd,
               ios->bus_mode);
 
@@ -810,7 +809,7 @@ static irqreturn_t au1xmmc_irq(int irq, void *dev_id, struct pt_regs *regs)
                                 au1xmmc_receive_pio(host);
                 }
                 else if (status & 0x203FBC70) {
-                        DEBUG("Unhandled status %8.8x\n", host->id, status);
+                        DBG("Unhandled status %8.8x\n", host->id, status);
                         handled = 0;
                 }
 
@@ -839,7 +838,7 @@ static void au1xmmc_poll_event(unsigned long arg)
 
         if (host->mrq != NULL) {
                 u32 status = au_readl(HOST_STATUS(host));
-                DEBUG("PENDING - %8.8x\n", host->id, status);
+                DBG("PENDING - %8.8x\n", host->id, status);
         }
 
         mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
diff --git a/drivers/mmc/imxmmc.c b/drivers/mmc/imxmmc.c
new file mode 100644
index 000000000000..ffb7f55d3467
--- /dev/null
+++ b/drivers/mmc/imxmmc.c
@@ -0,0 +1,1096 @@
+/*
+ *  linux/drivers/mmc/imxmmc.c - Motorola i.MX MMCI driver
+ *
+ *  Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
+ *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
+ *
+ *  derived from pxamci.c by Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *             Changed to conform redesigned i.MX scatter gather DMA interface
+ *
+ *  2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *             Updated for 2.6.14 kernel
+ *
+ *  2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
+ *             Found and corrected problems in the write path
+ *
+ *  2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *             The event handling rewritten right way in softirq.
+ *             Added many ugly hacks and delays to overcome SDHC
+ *             deficiencies
+ *
+ */
+#include <linux/config.h>
+
+#ifdef CONFIG_MMC_DEBUG
+#define DEBUG
+#else
+#undef  DEBUG
+#endif
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/blkdev.h>
+#include <linux/dma-mapping.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/protocol.h>
+#include <linux/delay.h>
+
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/imx-dma.h>
+
+#include "imxmmc.h"
+
+#define DRIVER_NAME "imx-mmc"
+
+#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
+                      INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
+                      INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
+
+struct imxmci_host {
+        struct mmc_host         *mmc;
+        spinlock_t              lock;
+        struct resource         *res;
+        int                     irq;
+        imx_dmach_t             dma;
+        unsigned int            clkrt;
+        unsigned int            cmdat;
+        volatile unsigned int   imask;
+        unsigned int            power_mode;
+        unsigned int            present;
+        struct imxmmc_platform_data *pdata;
+
+        struct mmc_request      *req;
+        struct mmc_command      *cmd;
+        struct mmc_data         *data;
+
+        struct timer_list       timer;
+        struct tasklet_struct   tasklet;
+        unsigned int            status_reg;
+        unsigned long           pending_events;
+        /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */
+        u16                     *data_ptr;
+        unsigned int            data_cnt;
+        atomic_t                stuck_timeout;
+
+        unsigned int            dma_nents;
+        unsigned int            dma_size;
+        unsigned int            dma_dir;
+        int                     dma_allocated;
+
+        unsigned char           actual_bus_width;
+};
+
+#define IMXMCI_PEND_IRQ_b       0
+#define IMXMCI_PEND_DMA_END_b   1
+#define IMXMCI_PEND_DMA_ERR_b   2
+#define IMXMCI_PEND_WAIT_RESP_b 3
+#define IMXMCI_PEND_DMA_DATA_b  4
+#define IMXMCI_PEND_CPU_DATA_b  5
+#define IMXMCI_PEND_CARD_XCHG_b 6
+#define IMXMCI_PEND_SET_INIT_b  7
+
+#define IMXMCI_PEND_IRQ_m       (1 << IMXMCI_PEND_IRQ_b)
+#define IMXMCI_PEND_DMA_END_m   (1 << IMXMCI_PEND_DMA_END_b)
+#define IMXMCI_PEND_DMA_ERR_m   (1 << IMXMCI_PEND_DMA_ERR_b)
+#define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
+#define IMXMCI_PEND_DMA_DATA_m  (1 << IMXMCI_PEND_DMA_DATA_b)
+#define IMXMCI_PEND_CPU_DATA_m  (1 << IMXMCI_PEND_CPU_DATA_b)
+#define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
+#define IMXMCI_PEND_SET_INIT_m  (1 << IMXMCI_PEND_SET_INIT_b)
+
+static void imxmci_stop_clock(struct imxmci_host *host)
+{
+        int i = 0;
+        MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
+        while(i < 0x1000) {
+                if(!(i & 0x7f))
+                        MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
+
+                if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
+                        /* Check twice before cut */
+                        if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
+                                return;
+                }
+
+                i++;
+        }
+        dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
+}
+
+static void imxmci_start_clock(struct imxmci_host *host)
+{
+        int i = 0;
+        MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
+        while(i < 0x1000) {
+                if(!(i & 0x7f))
+                        MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
+
+                if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) {
+                        /* Check twice before cut */
+                        if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
+                                return;
+                }
+
+                i++;
+        }
+        dev_dbg(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
+}
+
+static void imxmci_softreset(void)
+{
+        /* reset sequence */
+        MMC_STR_STP_CLK = 0x8;
+        MMC_STR_STP_CLK = 0xD;
+        MMC_STR_STP_CLK = 0x5;
+        MMC_STR_STP_CLK = 0x5;
+        MMC_STR_STP_CLK = 0x5;
+        MMC_STR_STP_CLK = 0x5;
+        MMC_STR_STP_CLK = 0x5;
+        MMC_STR_STP_CLK = 0x5;
+        MMC_STR_STP_CLK = 0x5;
+        MMC_STR_STP_CLK = 0x5;
+
+        MMC_RES_TO = 0xff;
+        MMC_BLK_LEN = 512;
+        MMC_NOB = 1;
+}
+
+static int imxmci_busy_wait_for_status(struct imxmci_host *host,
+                        unsigned int *pstat, unsigned int stat_mask,
+                        int timeout, const char *where)
+{
+        int loops=0;
+        while(!(*pstat & stat_mask)) {
+                loops+=2;
+                if(loops >= timeout) {
+                        dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
+                                where, *pstat, stat_mask);
+                        return -1;
+                }
+                udelay(2);
+                *pstat |= MMC_STATUS;
+        }
+        if(!loops)
+                return 0;
+
+        dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
+                loops, where, *pstat, stat_mask);
+        return loops;
+}
+
+static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
+{
+        unsigned int nob = data->blocks;
+        unsigned int blksz = 1 << data->blksz_bits;
+        unsigned int datasz = nob * blksz;
+        int i;
+
+        if (data->flags & MMC_DATA_STREAM)
+                nob = 0xffff;
+
+        host->data = data;
+        data->bytes_xfered = 0;
+
+        MMC_NOB = nob;
+        MMC_BLK_LEN = blksz;
+
+        /*
+         * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
+         * We are in big troubles for non-512 byte transfers according to note in the paragraph
+         * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
+         * The situation is even more complex in reality. The SDHC in not able to handle wll
+         * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
+         * This is required for SCR read at least.
+         */
+        if (datasz < 64) {
+                host->dma_size = datasz;
+                if (data->flags & MMC_DATA_READ) {
+                        host->dma_dir = DMA_FROM_DEVICE;
+
+                        /* Hack to enable read SCR */
+                        if(datasz < 16) {
+                                MMC_NOB = 1;
+                                MMC_BLK_LEN = 16;
+                        }
+                } else {
+                        host->dma_dir = DMA_TO_DEVICE;
+                }
+
+                /* Convert back to virtual address */
+                host->data_ptr = (u16*)(page_address(data->sg->page) + data->sg->offset);
+                host->data_cnt = 0;
+
+                clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
+                set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
+
+                return;
+        }
+
+        if (data->flags & MMC_DATA_READ) {
+                host->dma_dir = DMA_FROM_DEVICE;
+                host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
+                                                data->sg_len,  host->dma_dir);
+
+                imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
+                        host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
+
+                /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
+                CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
+        } else {
+                host->dma_dir = DMA_TO_DEVICE;
+
+                host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
+                                                data->sg_len,  host->dma_dir);
+
+                imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
+                        host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
+
+                /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
+                CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
+        }
+
+#if 1   /* This code is there only for consistency checking and can be disabled in future */
+        host->dma_size = 0;
+        for(i=0; i<host->dma_nents; i++)
+                host->dma_size+=data->sg[i].length;
+
+        if (datasz > host->dma_size) {
+                dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
+                       datasz, host->dma_size);
+        }
+#endif
+
+        host->dma_size = datasz;
+
+        wmb();
+
+        if(host->actual_bus_width == MMC_BUS_WIDTH_4)
+                BLR(host->dma) = 0;     /* burst 64 byte read / 64 bytes write */
+        else
+                BLR(host->dma) = 16;    /* burst 16 byte read / 16 bytes write */
+
+        RSSR(host->dma) = DMA_REQ_SDHC;
+
+        set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
+        clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
+
+        /* start DMA engine for read, write is delayed after initial response */
+        if (host->dma_dir == DMA_FROM_DEVICE) {
+                imx_dma_enable(host->dma);
+        }
+}
+
+static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
+{
+        unsigned long flags;
+        u32 imask;
+
+        WARN_ON(host->cmd != NULL);
+        host->cmd = cmd;
+
+        if (cmd->flags & MMC_RSP_BUSY)
+                cmdat |= CMD_DAT_CONT_BUSY;
+
+        switch (mmc_resp_type(cmd)) {
+        case MMC_RSP_R1: /* short CRC, OPCODE */
+        case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
+                cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
+                break;
+        case MMC_RSP_R2: /* long 136 bit + CRC */
+                cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
+                break;
+        case MMC_RSP_R3: /* short */
+                cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
+                break;
+        case MMC_RSP_R6: /* short CRC */
+                cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R6;
+                break;
+        default:
+                break;
+        }
+
+        if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) )
+                cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
+
+        if ( host->actual_bus_width == MMC_BUS_WIDTH_4 )
+                cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
+
+        MMC_CMD = cmd->opcode;
+        MMC_ARGH = cmd->arg >> 16;
+        MMC_ARGL = cmd->arg & 0xffff;
+        MMC_CMD_DAT_CONT = cmdat;
+
+        atomic_set(&host->stuck_timeout, 0);
+        set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
+
+
+        imask = IMXMCI_INT_MASK_DEFAULT;
+        imask &= ~INT_MASK_END_CMD_RES;
+        if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) {
+                /*imask &= ~INT_MASK_BUF_READY;*/
+                imask &= ~INT_MASK_DATA_TRAN;
+                if ( cmdat & CMD_DAT_CONT_WRITE )
+                        imask &= ~INT_MASK_WRITE_OP_DONE;
+                if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
+                        imask &= ~INT_MASK_BUF_READY;
+        }
+
+        spin_lock_irqsave(&host->lock, flags);
+        host->imask = imask;
+        MMC_INT_MASK = host->imask;
+        spin_unlock_irqrestore(&host->lock, flags);
+
+        dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
+                cmd->opcode, cmd->opcode, imask);
+
+        imxmci_start_clock(host);
+}
+
+static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&host->lock, flags);
+
+        host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
+                        IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
+
+        host->imask = IMXMCI_INT_MASK_DEFAULT;
+        MMC_INT_MASK = host->imask;
+
+        spin_unlock_irqrestore(&host->lock, flags);
+
+        host->req = NULL;
+        host->cmd = NULL;
+        host->data = NULL;
+        mmc_request_done(host->mmc, req);
+}
+
+static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
+{
+        struct mmc_data *data = host->data;
+        int data_error;
+
+        if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){
+                imx_dma_disable(host->dma);
+                dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
+                             host->dma_dir);
+        }
+
+        if ( stat & STATUS_ERR_MASK ) {
+                dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat);
+                if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
+                        data->error = MMC_ERR_BADCRC;
+                else if(stat & STATUS_TIME_OUT_READ)
+                        data->error = MMC_ERR_TIMEOUT;
+                else
+                        data->error = MMC_ERR_FAILED;
+        } else {
+                data->bytes_xfered = host->dma_size;
+        }
+
+        data_error = data->error;
+
+        host->data = NULL;
+
+        return data_error;
+}
+
+static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
+{
+        struct mmc_command *cmd = host->cmd;
+        int i;
+        u32 a,b,c;
+        struct mmc_data *data = host->data;
+
+        if (!cmd)
+                return 0;
+
+        host->cmd = NULL;
+
+        if (stat & STATUS_TIME_OUT_RESP) {
+                dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
+                cmd->error = MMC_ERR_TIMEOUT;
+        } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
+                dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
+                cmd->error = MMC_ERR_BADCRC;
+        }
+
+        if(cmd->flags & MMC_RSP_PRESENT) {
+                if(cmd->flags & MMC_RSP_136) {
+                        for (i = 0; i < 4; i++) {
+                                u32 a = MMC_RES_FIFO & 0xffff;
+                                u32 b = MMC_RES_FIFO & 0xffff;
+                                cmd->resp[i] = a<<16 | b;
+                        }
+                } else {
+                        a = MMC_RES_FIFO & 0xffff;
+                        b = MMC_RES_FIFO & 0xffff;
+                        c = MMC_RES_FIFO & 0xffff;
+                        cmd->resp[0] = a<<24 | b<<8 | c>>8;
+                }
+        }
+
+        dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
+                cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
+
+        if (data && (cmd->error == MMC_ERR_NONE) && !(stat & STATUS_ERR_MASK)) {
+                if (host->req->data->flags & MMC_DATA_WRITE) {
+
+                        /* Wait for FIFO to be empty before starting DMA write */
+
+                        stat = MMC_STATUS;
+                        if(imxmci_busy_wait_for_status(host, &stat,
+                                STATUS_APPL_BUFF_FE,
+                                40, "imxmci_cmd_done DMA WR") < 0) {
+                                cmd->error = MMC_ERR_FIFO;
+                                imxmci_finish_data(host, stat);
+                                if(host->req)
+                                        imxmci_finish_request(host, host->req);
+                                dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
+                                       stat);
+                                return 0;
+                        }
+
+                        if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
+                                imx_dma_enable(host->dma);
+                        }
+                }
+        } else {
+                struct mmc_request *req;
+                imxmci_stop_clock(host);
+                req = host->req;
+
+                if(data)
+                        imxmci_finish_data(host, stat);
+
+                if( req ) {
+                        imxmci_finish_request(host, req);
+                } else {
+                        dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
+                }
+        }
+
+        return 1;
+}
+
+static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
+{
+        struct mmc_data *data = host->data;
+        int data_error;
+
+        if (!data)
+                return 0;
+
+        data_error = imxmci_finish_data(host, stat);
+
+        if (host->req->stop && (data_error == MMC_ERR_NONE)) {
+                imxmci_stop_clock(host);
+                imxmci_start_cmd(host, host->req->stop, 0);
+        } else {
+                struct mmc_request *req;
+                req = host->req;
+                if( req ) {
+                        imxmci_finish_request(host, req);
+                } else {
+                        dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
+                }
+        }
+
+        return 1;
+}
+
+static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
+{
+        int i;
+        int burst_len;
+        int flush_len;
+        int trans_done = 0;
+        unsigned int stat = *pstat;
+
+        if(host->actual_bus_width == MMC_BUS_WIDTH_4)
+                burst_len = 16;
+        else
+                burst_len = 64;
+
+        /* This is unfortunately required */
+        dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
+                stat);
+
+        if(host->dma_dir == DMA_FROM_DEVICE) {
+                imxmci_busy_wait_for_status(host, &stat,
+                                STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE,
+                                20, "imxmci_cpu_driven_data read");
+
+                while((stat & (STATUS_APPL_BUFF_FF |  STATUS_DATA_TRANS_DONE)) &&
+                      (host->data_cnt < host->dma_size)) {
+                        if(burst_len >= host->dma_size - host->data_cnt) {
+                                flush_len = burst_len;
+                                burst_len = host->dma_size - host->data_cnt;
+                                flush_len -= burst_len;
+                                host->data_cnt = host->dma_size;
+                                trans_done = 1;
+                        } else {
+                                flush_len = 0;
+                                host->data_cnt += burst_len;
+                        }
+
+                        for(i = burst_len; i>=2 ; i-=2) {
+                                *(host->data_ptr++) = MMC_BUFFER_ACCESS;
+                                udelay(20);     /* required for clocks < 8MHz*/
+                        }
+
+                        if(i == 1)
+                                *(u8*)(host->data_ptr) = MMC_BUFFER_ACCESS;
+
+                        stat = MMC_STATUS;
+
+                        /* Flush extra bytes from FIFO */
+                        while(flush_len >= 2){
+                                flush_len -= 2;
+                                i = MMC_BUFFER_ACCESS;
+                                stat = MMC_STATUS;
+                                stat &= ~STATUS_CRC_READ_ERR; /* Stupid but required there */
+                        }
+
+                        dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read burst %d STATUS = 0x%x\n",
+                                burst_len, stat);
+                }
+        } else {
+                imxmci_busy_wait_for_status(host, &stat,
+                                STATUS_APPL_BUFF_FE,
+                                20, "imxmci_cpu_driven_data write");
+
+                while((stat & STATUS_APPL_BUFF_FE) &&
+                      (host->data_cnt < host->dma_size)) {
+                        if(burst_len >= host->dma_size - host->data_cnt) {
+                                burst_len = host->dma_size - host->data_cnt;
+                                host->data_cnt = host->dma_size;
+                                trans_done = 1;
+                        } else {
+                                host->data_cnt += burst_len;
+                        }
+
+                        for(i = burst_len; i>0 ; i-=2)
+                                MMC_BUFFER_ACCESS = *(host->data_ptr++);
+
+                        stat = MMC_STATUS;
+
+                        dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
+                                burst_len, stat);
+                }
+        }
+
+        *pstat = stat;
+
+        return trans_done;
+}
+
+static void imxmci_dma_irq(int dma, void *devid, struct pt_regs *regs)
+{
+        struct imxmci_host *host = devid;
+        uint32_t stat = MMC_STATUS;
+
+        atomic_set(&host->stuck_timeout, 0);
+        host->status_reg = stat;
+        set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
+        tasklet_schedule(&host->tasklet);
+}
+
+static irqreturn_t imxmci_irq(int irq, void *devid, struct pt_regs *regs)
+{
+        struct imxmci_host *host = devid;
+        uint32_t stat = MMC_STATUS;
+        int handled = 1;
+
+        MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
+
+        atomic_set(&host->stuck_timeout, 0);
+        host->status_reg = stat;
+        set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
+        tasklet_schedule(&host->tasklet);
+
+        return IRQ_RETVAL(handled);;
+}
+
+static void imxmci_tasklet_fnc(unsigned long data)
+{
+        struct imxmci_host *host = (struct imxmci_host *)data;
+        u32 stat;
+        unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
+        int timeout = 0;
+
+        if(atomic_read(&host->stuck_timeout) > 4) {
+                char *what;
+                timeout = 1;
+                stat = MMC_STATUS;
+                host->status_reg = stat;
+                if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
+                        if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
+                                what = "RESP+DMA";
+                        else
+                                what = "RESP";
+                else
+                        if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
+                                if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
+                                        what = "DATA";
+                                else
+                                        what = "DMA";
+                        else
+                                what = "???";
+
+                dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
+                       what, stat, MMC_INT_MASK);
+                dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
+                       MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
+                dev_err(mmc_dev(host->mmc), "CMD%d, bus %d-bit, dma_size = 0x%x\n",
+                       host->cmd?host->cmd->opcode:0, 1<<host->actual_bus_width, host->dma_size);
+        }
+
+        if(!host->present || timeout)
+                host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
+                                    STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
+
+        if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
+                clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
+
+                stat = MMC_STATUS;
+                /*
+                 * This is not required in theory, but there is chance to miss some flag
+                 * which clears automatically by mask write, FreeScale original code keeps
+                 * stat from IRQ time so do I
+                 */
+                stat |= host->status_reg;
+
+                if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
+                        imxmci_busy_wait_for_status(host, &stat,
+                                        STATUS_END_CMD_RESP | STATUS_ERR_MASK,
+                                        20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
+                }
+
+                if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
+                        if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
+                                imxmci_cmd_done(host, stat);
+                        if(host->data && (stat & STATUS_ERR_MASK))
+                                imxmci_data_done(host, stat);
+                }
+
+                if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
+                        stat |= MMC_STATUS;
+                        if(imxmci_cpu_driven_data(host, &stat)){
+                                if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
+                                        imxmci_cmd_done(host, stat);
+                                atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
+                                                        &host->pending_events);
+                                imxmci_data_done(host, stat);
+                        }
+                }
+        }
+
+        if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
+           !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
+
+                stat = MMC_STATUS;
+                /* Same as above */
+                stat |= host->status_reg;
+
+                if(host->dma_dir == DMA_TO_DEVICE) {
+                        data_dir_mask = STATUS_WRITE_OP_DONE;
+                } else {
+                        data_dir_mask = STATUS_DATA_TRANS_DONE;
+                }
+
+                imxmci_busy_wait_for_status(host, &stat,
+                                data_dir_mask,
+                                50, "imxmci_tasklet_fnc data");
+
+                if(stat & data_dir_mask) {
+                        clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
+                        imxmci_data_done(host, stat);
+                }
+        }
+
+        if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
+
+                if(host->cmd)
+                        imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
+
+                if(host->data)
+                        imxmci_data_done(host, STATUS_TIME_OUT_READ |
+                                         STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
+
+                if(host->req)
+                        imxmci_finish_request(host, host->req);
+
+                mmc_detect_change(host->mmc, msecs_to_jiffies(100));
+
+        }
+}
+
+static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
+{
+        struct imxmci_host *host = mmc_priv(mmc);
+        unsigned int cmdat;
+
+        WARN_ON(host->req != NULL);
+
+        host->req = req;
+
+        cmdat = 0;
+
+        if (req->data) {
+                imxmci_setup_data(host, req->data);
+
+                cmdat |= CMD_DAT_CONT_DATA_ENABLE;
+
+                if (req->data->flags & MMC_DATA_WRITE)
+                        cmdat |= CMD_DAT_CONT_WRITE;
+
+                if (req->data->flags & MMC_DATA_STREAM) {
+                        cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
+                }
+        }
+
+        imxmci_start_cmd(host, req->cmd, cmdat);
+}
+
+#define CLK_RATE 19200000
+
+static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+        struct imxmci_host *host = mmc_priv(mmc);
+        int prescaler;
+
+        dev_dbg(mmc_dev(host->mmc), "clock %u power %u vdd %u width %u\n",
+                ios->clock, ios->power_mode, ios->vdd,
+                (ios->bus_width==MMC_BUS_WIDTH_4)?4:1);
+
+        if( ios->bus_width==MMC_BUS_WIDTH_4 ) {
+                host->actual_bus_width = MMC_BUS_WIDTH_4;
+                imx_gpio_mode(PB11_PF_SD_DAT3);
+        }else{
+                host->actual_bus_width = MMC_BUS_WIDTH_1;
+                imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
+        }
+
+        if ( host->power_mode != ios->power_mode ) {
+                switch (ios->power_mode) {
+                case MMC_POWER_OFF:
+                        break;
+                case MMC_POWER_UP:
+                        set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
+                        break;
+                case MMC_POWER_ON:
+                        break;
+                }
+                host->power_mode = ios->power_mode;
+        }
+
+        if ( ios->clock ) {
+                unsigned int clk;
+
+                /* The prescaler is 5 for PERCLK2 equal to 96MHz
+                 * then 96MHz / 5 = 19.2 MHz
+                 */
+                clk=imx_get_perclk2();
+                prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE;
+                switch(prescaler) {
+                case 0:
+                case 1: prescaler = 0;
+                        break;
+                case 2: prescaler = 1;
+                        break;
+                case 3: prescaler = 2;
+                        break;
+                case 4: prescaler = 4;
+                        break;
+                default:
+                case 5: prescaler = 5;
+                        break;
+                }
+
+                dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
+                        clk, prescaler);
+
+                for(clk=0; clk<8; clk++) {
+                        int x;
+                        x = CLK_RATE / (1<<clk);
+                        if( x <= ios->clock)
+                                break;
+                }
+
+                MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
+
+                imxmci_stop_clock(host);
+                MMC_CLK_RATE = (prescaler<<3) | clk;
+                imxmci_start_clock(host);
+
+                dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
+        } else {
+                imxmci_stop_clock(host);
+        }
+}
+
+static struct mmc_host_ops imxmci_ops = {
+        .request        = imxmci_request,
+        .set_ios        = imxmci_set_ios,
+};
+
+static struct resource *platform_device_resource(struct platform_device *dev, unsigned int mask, int nr)
+{
+        int i;
+
+        for (i = 0; i < dev->num_resources; i++)
+                if (dev->resource[i].flags == mask && nr-- == 0)
+                        return &dev->resource[i];
+        return NULL;
+}
+
+static int platform_device_irq(struct platform_device *dev, int nr)
+{
+        int i;
+
+        for (i = 0; i < dev->num_resources; i++)
+                if (dev->resource[i].flags == IORESOURCE_IRQ && nr-- == 0)
+                        return dev->resource[i].start;
+        return NO_IRQ;
+}
+
+static void imxmci_check_status(unsigned long data)
+{
+        struct imxmci_host *host = (struct imxmci_host *)data;
+
+        if( host->pdata->card_present() != host->present ) {
+                host->present ^= 1;
+                dev_info(mmc_dev(host->mmc), "card %s\n",
+                      host->present ? "inserted" : "removed");
+
+                set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
+                tasklet_schedule(&host->tasklet);
+        }
+
+        if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
+           test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
+                atomic_inc(&host->stuck_timeout);
+                if(atomic_read(&host->stuck_timeout) > 4)
+                        tasklet_schedule(&host->tasklet);
+        } else {
+                atomic_set(&host->stuck_timeout, 0);
+
+        }
+
+        mod_timer(&host->timer, jiffies + (HZ>>1));
+}
+
+static int imxmci_probe(struct platform_device *pdev)
+{
+        struct mmc_host *mmc;
+        struct imxmci_host *host = NULL;
+        struct resource *r;
+        int ret = 0, irq;
+
+        printk(KERN_INFO "i.MX mmc driver\n");
+
+        r = platform_device_resource(pdev, IORESOURCE_MEM, 0);
+        irq = platform_device_irq(pdev, 0);
+        if (!r || irq == NO_IRQ)
+                return -ENXIO;
+
+        r = request_mem_region(r->start, 0x100, "IMXMCI");
+        if (!r)
+                return -EBUSY;
+
+        mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
+        if (!mmc) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        mmc->ops = &imxmci_ops;
+        mmc->f_min = 150000;
+        mmc->f_max = CLK_RATE/2;
+        mmc->ocr_avail = MMC_VDD_32_33;
+        mmc->caps |= MMC_CAP_4_BIT_DATA;
+
+        /* MMC core transfer sizes tunable parameters */
+        mmc->max_hw_segs = 64;
+        mmc->max_phys_segs = 64;
+        mmc->max_sectors = 64;          /* default 1 << (PAGE_CACHE_SHIFT - 9) */
+        mmc->max_seg_size = 64*512;     /* default PAGE_CACHE_SIZE */
+
+        host = mmc_priv(mmc);
+        host->mmc = mmc;
+        host->dma_allocated = 0;
+        host->pdata = pdev->dev.platform_data;
+
+        spin_lock_init(&host->lock);
+        host->res = r;
+        host->irq = irq;
+
+        imx_gpio_mode(PB8_PF_SD_DAT0);
+        imx_gpio_mode(PB9_PF_SD_DAT1);
+        imx_gpio_mode(PB10_PF_SD_DAT2);
+        /* Configured as GPIO with pull-up to ensure right MCC card mode */
+        /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
+        imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
+        /* imx_gpio_mode(PB11_PF_SD_DAT3); */
+        imx_gpio_mode(PB12_PF_SD_CLK);
+        imx_gpio_mode(PB13_PF_SD_CMD);
+
+        imxmci_softreset();
+
+        if ( MMC_REV_NO != 0x390 ) {
+                dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
+                        MMC_REV_NO);
+                goto out;
+        }
+
+        MMC_READ_TO = 0x2db4; /* recommended in data sheet */
+
+        host->imask = IMXMCI_INT_MASK_DEFAULT;
+        MMC_INT_MASK = host->imask;
+
+
+        if(imx_dma_request_by_prio(&host->dma, DRIVER_NAME, DMA_PRIO_LOW)<0){
+                dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
+                ret = -EBUSY;
+                goto out;
+        }
+        host->dma_allocated=1;
+        imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
+
+        tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
+        host->status_reg=0;
+        host->pending_events=0;
+
+        ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
+        if (ret)
+                goto out;
+
+        host->present = host->pdata->card_present();
+        init_timer(&host->timer);
+        host->timer.data = (unsigned long)host;
+        host->timer.function = imxmci_check_status;
+        add_timer(&host->timer);
+        mod_timer(&host->timer, jiffies + (HZ>>1));
+
+        platform_set_drvdata(pdev, mmc);
+
+        mmc_add_host(mmc);
+
+        return 0;
+
+out:
+        if (host) {
+                if(host->dma_allocated){
+                        imx_dma_free(host->dma);
+                        host->dma_allocated=0;
+                }
+        }
+        if (mmc)
+                mmc_free_host(mmc);
+        release_resource(r);
+        return ret;
+}
+
+static int imxmci_remove(struct platform_device *pdev)
+{
+        struct mmc_host *mmc = platform_get_drvdata(pdev);
+
+        platform_set_drvdata(pdev, NULL);
+
+        if (mmc) {
+                struct imxmci_host *host = mmc_priv(mmc);
+
+                tasklet_disable(&host->tasklet);
+
+                del_timer_sync(&host->timer);
+                mmc_remove_host(mmc);
+
+                free_irq(host->irq, host);
+                if(host->dma_allocated){
+                        imx_dma_free(host->dma);
+                        host->dma_allocated=0;
+                }
+
+                tasklet_kill(&host->tasklet);
+
+                release_resource(host->res);
+
+                mmc_free_host(mmc);
+        }
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
+{
+        struct mmc_host *mmc = platform_get_drvdata(dev);
+        int ret = 0;
+
+        if (mmc)
+                ret = mmc_suspend_host(mmc, state);
+
+        return ret;
+}
+
+static int imxmci_resume(struct platform_device *dev)
+{
+        struct mmc_host *mmc = platform_get_drvdata(dev);
+        struct imxmci_host *host;
+        int ret = 0;
+
+        if (mmc) {
+                host = mmc_priv(mmc);
+                if(host)
+                        set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
+                ret = mmc_resume_host(mmc);
+        }
+
+        return ret;
+}
+#else
+#define imxmci_suspend  NULL
+#define imxmci_resume   NULL
+#endif /* CONFIG_PM */
+
+static struct platform_driver imxmci_driver = {
+        .probe          = imxmci_probe,
+        .remove         = imxmci_remove,
+        .suspend        = imxmci_suspend,
+        .resume         = imxmci_resume,
+        .driver         = {
+                .name           = DRIVER_NAME,
+        }
+};
+
+static int __init imxmci_init(void)
+{
+        return platform_driver_register(&imxmci_driver);
+}
+
+static void __exit imxmci_exit(void)
+{
+        platform_driver_unregister(&imxmci_driver);
+}
+
+module_init(imxmci_init);
+module_exit(imxmci_exit);
+
+MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
+MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/imxmmc.h b/drivers/mmc/imxmmc.h
new file mode 100644
index 000000000000..e5339e334dbb
--- /dev/null
+++ b/drivers/mmc/imxmmc.h
@@ -0,0 +1,67 @@
+
+# define __REG16(x)     (*((volatile u16 *)IO_ADDRESS(x)))
+
+#define MMC_STR_STP_CLK  __REG16(IMX_MMC_BASE + 0x00)
+#define MMC_STATUS       __REG16(IMX_MMC_BASE + 0x04)
+#define MMC_CLK_RATE     __REG16(IMX_MMC_BASE + 0x08)
+#define MMC_CMD_DAT_CONT __REG16(IMX_MMC_BASE + 0x0C)
+#define MMC_RES_TO       __REG16(IMX_MMC_BASE + 0x10)
+#define MMC_READ_TO      __REG16(IMX_MMC_BASE + 0x14)
+#define MMC_BLK_LEN      __REG16(IMX_MMC_BASE + 0x18)
+#define MMC_NOB          __REG16(IMX_MMC_BASE + 0x1C)
+#define MMC_REV_NO       __REG16(IMX_MMC_BASE + 0x20)
+#define MMC_INT_MASK     __REG16(IMX_MMC_BASE + 0x24)
+#define MMC_CMD          __REG16(IMX_MMC_BASE + 0x28)
+#define MMC_ARGH         __REG16(IMX_MMC_BASE + 0x2C)
+#define MMC_ARGL         __REG16(IMX_MMC_BASE + 0x30)
+#define MMC_RES_FIFO     __REG16(IMX_MMC_BASE + 0x34)
+#define MMC_BUFFER_ACCESS __REG16(IMX_MMC_BASE + 0x38)
+#define MMC_BUFFER_ACCESS_OFS 0x38
+
+
+#define STR_STP_CLK_ENDIAN              (1<<5)
+#define STR_STP_CLK_RESET               (1<<3)
+#define STR_STP_CLK_ENABLE              (1<<2)
+#define STR_STP_CLK_START_CLK           (1<<1)
+#define STR_STP_CLK_STOP_CLK            (1<<0)
+#define STATUS_CARD_PRESENCE            (1<<15)
+#define STATUS_SDIO_INT_ACTIVE          (1<<14)
+#define STATUS_END_CMD_RESP             (1<<13)
+#define STATUS_WRITE_OP_DONE            (1<<12)
+#define STATUS_DATA_TRANS_DONE          (1<<11)
+#define STATUS_WR_CRC_ERROR_CODE_MASK   (3<<10)
+#define STATUS_CARD_BUS_CLK_RUN         (1<<8)
+#define STATUS_APPL_BUFF_FF             (1<<7)
+#define STATUS_APPL_BUFF_FE             (1<<6)
+#define STATUS_RESP_CRC_ERR             (1<<5)
+#define STATUS_CRC_READ_ERR             (1<<3)
+#define STATUS_CRC_WRITE_ERR            (1<<2)
+#define STATUS_TIME_OUT_RESP            (1<<1)
+#define STATUS_TIME_OUT_READ            (1<<0)
+#define STATUS_ERR_MASK                 0x2f
+#define CLK_RATE_PRESCALER(x)           ((x) & 0x7)
+#define CLK_RATE_CLK_RATE(x)            (((x) & 0x7) << 3)
+#define CMD_DAT_CONT_CMD_RESP_LONG_OFF  (1<<12)
+#define CMD_DAT_CONT_STOP_READWAIT      (1<<11)
+#define CMD_DAT_CONT_START_READWAIT     (1<<10)
+#define CMD_DAT_CONT_BUS_WIDTH_1        (0<<8)
+#define CMD_DAT_CONT_BUS_WIDTH_4        (2<<8)
+#define CMD_DAT_CONT_INIT               (1<<7)
+#define CMD_DAT_CONT_BUSY               (1<<6)
+#define CMD_DAT_CONT_STREAM_BLOCK       (1<<5)
+#define CMD_DAT_CONT_WRITE              (1<<4)
+#define CMD_DAT_CONT_DATA_ENABLE        (1<<3)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R1 (1)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R2 (2)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R3 (3)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R4 (4)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R5 (5)
+#define CMD_DAT_CONT_RESPONSE_FORMAT_R6 (6)
+#define INT_MASK_AUTO_CARD_DETECT       (1<<6)
+#define INT_MASK_DAT0_EN                (1<<5)
+#define INT_MASK_SDIO                   (1<<4)
+#define INT_MASK_BUF_READY              (1<<3)
+#define INT_MASK_END_CMD_RES            (1<<2)
+#define INT_MASK_WRITE_OP_DONE          (1<<1)
+#define INT_MASK_DATA_TRAN              (1<<0)
+#define INT_ALL                         (0x7f)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 1888060c5e0c..da6ddd910fc5 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -27,12 +27,6 @@
 
 #include "mmc.h"
 
-#ifdef CONFIG_MMC_DEBUG
-#define DBG(x...)       printk(KERN_DEBUG x)
-#else
-#define DBG(x...)       do { } while (0)
-#endif
-
 #define CMD_RETRIES     3
 
 /*
@@ -77,8 +71,9 @@ void mmc_request_done(struct mmc_host *host, struct mmc_request *mrq)
 {
         struct mmc_command *cmd = mrq->cmd;
         int err = mrq->cmd->error;
-        DBG("MMC: req done (%02x): %d: %08x %08x %08x %08x\n", cmd->opcode,
-            err, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+        pr_debug("MMC: req done (%02x): %d: %08x %08x %08x %08x\n",
+                 cmd->opcode, err, cmd->resp[0], cmd->resp[1],
+                 cmd->resp[2], cmd->resp[3]);
 
         if (err && cmd->retries) {
                 cmd->retries--;
@@ -102,8 +97,8 @@ EXPORT_SYMBOL(mmc_request_done);
 void
 mmc_start_request(struct mmc_host *host, struct mmc_request *mrq)
 {
-        DBG("MMC: starting cmd %02x arg %08x flags %08x\n",
-            mrq->cmd->opcode, mrq->cmd->arg, mrq->cmd->flags);
+        pr_debug("MMC: starting cmd %02x arg %08x flags %08x\n",
+                 mrq->cmd->opcode, mrq->cmd->arg, mrq->cmd->flags);
 
         WARN_ON(host->card_busy == NULL);
 
@@ -976,8 +971,8 @@ static unsigned int mmc_calculate_clock(struct mmc_host *host)
                 if (!mmc_card_dead(card) && max_dtr > card->csd.max_dtr)
                         max_dtr = card->csd.max_dtr;
 
-        DBG("MMC: selected %d.%03dMHz transfer rate\n",
-            max_dtr / 1000000, (max_dtr / 1000) % 1000);
+        pr_debug("MMC: selected %d.%03dMHz transfer rate\n",
+                 max_dtr / 1000000, (max_dtr / 1000) % 1000);
 
         return max_dtr;
 }
diff --git a/drivers/mmc/mmci.c b/drivers/mmc/mmci.c
index 9fef29d978b5..df7e861e2fc7 100644
--- a/drivers/mmc/mmci.c
+++ b/drivers/mmc/mmci.c
@@ -33,12 +33,8 @@
 
 #define DRIVER_NAME "mmci-pl18x"
 
-#ifdef CONFIG_MMC_DEBUG
 #define DBG(host,fmt,args...)   \
         pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
-#else
-#define DBG(host,fmt,args...)   do { } while (0)
-#endif
 
 static unsigned int fmax = 515633;
 
diff --git a/drivers/mmc/omap.c b/drivers/mmc/omap.c
new file mode 100644
index 000000000000..becb3c68c34d
--- /dev/null
+++ b/drivers/mmc/omap.c
@@ -0,0 +1,1226 @@
+/*
+ *  linux/drivers/media/mmc/omap.c
+ *
+ *  Copyright (C) 2004 Nokia Corporation
+ *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
+ *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
+ *  Other hacks (DMA, SD, etc) by David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/timer.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/protocol.h>
+#include <linux/mmc/card.h>
+#include <linux/clk.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/scatterlist.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/dma.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/fpga.h>
+#include <asm/arch/tps65010.h>
+
+#include "omap.h"
+
+#define DRIVER_NAME "mmci-omap"
+#define RSP_TYPE(x)     ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
+
+/* Specifies how often in millisecs to poll for card status changes
+ * when the cover switch is open */
+#define OMAP_MMC_SWITCH_POLL_DELAY      500
+
+static int mmc_omap_enable_poll = 1;
+
+struct mmc_omap_host {
+        int                     initialized;
+        int                     suspended;
+        struct mmc_request *    mrq;
+        struct mmc_command *    cmd;
+        struct mmc_data *       data;
+        struct mmc_host *       mmc;
+        struct device *         dev;
+        unsigned char           id; /* 16xx chips have 2 MMC blocks */
+        struct clk *            iclk;
+        struct clk *            fclk;
+        void __iomem            *base;
+        int                     irq;
+        unsigned char           bus_mode;
+        unsigned char           hw_bus_mode;
+
+        unsigned int            sg_len;
+        int                     sg_idx;
+        u16 *                   buffer;
+        u32                     buffer_bytes_left;
+        u32                     total_bytes_left;
+
+        unsigned                use_dma:1;
+        unsigned                brs_received:1, dma_done:1;
+        unsigned                dma_is_read:1;
+        unsigned                dma_in_use:1;
+        int                     dma_ch;
+        spinlock_t              dma_lock;
+        struct timer_list       dma_timer;
+        unsigned                dma_len;
+
+        short                   power_pin;
+        short                   wp_pin;
+
+        int                     switch_pin;
+        struct work_struct      switch_work;
+        struct timer_list       switch_timer;
+        int                     switch_last_state;
+};
+
+static inline int
+mmc_omap_cover_is_open(struct mmc_omap_host *host)
+{
+        if (host->switch_pin < 0)
+                return 0;
+        return omap_get_gpio_datain(host->switch_pin);
+}
+
+static ssize_t
+mmc_omap_show_cover_switch(struct device *dev,
+        struct device_attribute *attr, char *buf)
+{
+        struct mmc_omap_host *host = dev_get_drvdata(dev);
+
+        return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
+                        "closed");
+}
+
+static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
+
+static ssize_t
+mmc_omap_show_enable_poll(struct device *dev,
+        struct device_attribute *attr, char *buf)
+{
+        return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
+}
+
+static ssize_t
+mmc_omap_store_enable_poll(struct device *dev,
+        struct device_attribute *attr, const char *buf,
+        size_t size)
+{
+        int enable_poll;
+
+        if (sscanf(buf, "%10d", &enable_poll) != 1)
+                return -EINVAL;
+
+        if (enable_poll != mmc_omap_enable_poll) {
+                struct mmc_omap_host *host = dev_get_drvdata(dev);
+
+                mmc_omap_enable_poll = enable_poll;
+                if (enable_poll && host->switch_pin >= 0)
+                        schedule_work(&host->switch_work);
+        }
+        return size;
+}
+
+static DEVICE_ATTR(enable_poll, 0664,
+                   mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
+
+static void
+mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
+{
+        u32 cmdreg;
+        u32 resptype;
+        u32 cmdtype;
+
+        host->cmd = cmd;
+
+        resptype = 0;
+        cmdtype = 0;
+
+        /* Our hardware needs to know exact type */
+        switch (RSP_TYPE(mmc_resp_type(cmd))) {
+        case RSP_TYPE(MMC_RSP_R1):
+                /* resp 1, resp 1b */
+                resptype = 1;
+                break;
+        case RSP_TYPE(MMC_RSP_R2):
+                resptype = 2;
+                break;
+        case RSP_TYPE(MMC_RSP_R3):
+                resptype = 3;
+                break;
+        default:
+                break;
+        }
+
+        if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
+                cmdtype = OMAP_MMC_CMDTYPE_ADTC;
+        } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
+                cmdtype = OMAP_MMC_CMDTYPE_BC;
+        } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
+                cmdtype = OMAP_MMC_CMDTYPE_BCR;
+        } else {
+                cmdtype = OMAP_MMC_CMDTYPE_AC;
+        }
+
+        cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
+
+        if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
+                cmdreg |= 1 << 6;
+
+        if (cmd->flags & MMC_RSP_BUSY)
+                cmdreg |= 1 << 11;
+
+        if (host->data && !(host->data->flags & MMC_DATA_WRITE))
+                cmdreg |= 1 << 15;
+
+        clk_enable(host->fclk);
+
+        OMAP_MMC_WRITE(host->base, CTO, 200);
+        OMAP_MMC_WRITE(host->base, ARGL, cmd->arg & 0xffff);
+        OMAP_MMC_WRITE(host->base, ARGH, cmd->arg >> 16);
+        OMAP_MMC_WRITE(host->base, IE,
+                       OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
+                       OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
+                       OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
+                       OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
+                       OMAP_MMC_STAT_END_OF_DATA);
+        OMAP_MMC_WRITE(host->base, CMD, cmdreg);
+}
+
+static void
+mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
+{
+        if (host->dma_in_use) {
+                enum dma_data_direction dma_data_dir;
+
+                BUG_ON(host->dma_ch < 0);
+                if (data->error != MMC_ERR_NONE)
+                        omap_stop_dma(host->dma_ch);
+                /* Release DMA channel lazily */
+                mod_timer(&host->dma_timer, jiffies + HZ);
+                if (data->flags & MMC_DATA_WRITE)
+                        dma_data_dir = DMA_TO_DEVICE;
+                else
+                        dma_data_dir = DMA_FROM_DEVICE;
+                dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
+                             dma_data_dir);
+        }
+        host->data = NULL;
+        host->sg_len = 0;
+        clk_disable(host->fclk);
+
+        /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
+         * dozens of requests until the card finishes writing data.
+         * It'd be cheaper to just wait till an EOFB interrupt arrives...
+         */
+
+        if (!data->stop) {
+                host->mrq = NULL;
+                mmc_request_done(host->mmc, data->mrq);
+                return;
+        }
+
+        mmc_omap_start_command(host, data->stop);
+}
+
+static void
+mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
+{
+        unsigned long flags;
+        int done;
+
+        if (!host->dma_in_use) {
+                mmc_omap_xfer_done(host, data);
+                return;
+        }
+        done = 0;
+        spin_lock_irqsave(&host->dma_lock, flags);
+        if (host->dma_done)
+                done = 1;
+        else
+                host->brs_received = 1;
+        spin_unlock_irqrestore(&host->dma_lock, flags);
+        if (done)
+                mmc_omap_xfer_done(host, data);
+}
+
+static void
+mmc_omap_dma_timer(unsigned long data)
+{
+        struct mmc_omap_host *host = (struct mmc_omap_host *) data;
+
+        BUG_ON(host->dma_ch < 0);
+        omap_free_dma(host->dma_ch);
+        host->dma_ch = -1;
+}
+
+static void
+mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
+{
+        unsigned long flags;
+        int done;
+
+        done = 0;
+        spin_lock_irqsave(&host->dma_lock, flags);
+        if (host->brs_received)
+                done = 1;
+        else
+                host->dma_done = 1;
+        spin_unlock_irqrestore(&host->dma_lock, flags);
+        if (done)
+                mmc_omap_xfer_done(host, data);
+}
+
+static void
+mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
+{
+        host->cmd = NULL;
+
+        if (cmd->flags & MMC_RSP_PRESENT) {
+                if (cmd->flags & MMC_RSP_136) {
+                        /* response type 2 */
+                        cmd->resp[3] =
+                                OMAP_MMC_READ(host->base, RSP0) |
+                                (OMAP_MMC_READ(host->base, RSP1) << 16);
+                        cmd->resp[2] =
+                                OMAP_MMC_READ(host->base, RSP2) |
+                                (OMAP_MMC_READ(host->base, RSP3) << 16);
+                        cmd->resp[1] =
+                                OMAP_MMC_READ(host->base, RSP4) |
+                                (OMAP_MMC_READ(host->base, RSP5) << 16);
+                        cmd->resp[0] =
+                                OMAP_MMC_READ(host->base, RSP6) |
+                                (OMAP_MMC_READ(host->base, RSP7) << 16);
+                } else {
+                        /* response types 1, 1b, 3, 4, 5, 6 */
+                        cmd->resp[0] =
+                                OMAP_MMC_READ(host->base, RSP6) |
+                                (OMAP_MMC_READ(host->base, RSP7) << 16);
+                }
+        }
+
+        if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
+                host->mrq = NULL;
+                clk_disable(host->fclk);
+                mmc_request_done(host->mmc, cmd->mrq);
+        }
+}
+
+/* PIO only */
+static void
+mmc_omap_sg_to_buf(struct mmc_omap_host *host)
+{
+        struct scatterlist *sg;
+
+        sg = host->data->sg + host->sg_idx;
+        host->buffer_bytes_left = sg->length;
+        host->buffer = page_address(sg->page) + sg->offset;
+        if (host->buffer_bytes_left > host->total_bytes_left)
+                host->buffer_bytes_left = host->total_bytes_left;
+}
+
+/* PIO only */
+static void
+mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
+{
+        int n;
+        void __iomem *reg;
+        u16 *p;
+
+        if (host->buffer_bytes_left == 0) {
+                host->sg_idx++;
+                BUG_ON(host->sg_idx == host->sg_len);
+                mmc_omap_sg_to_buf(host);
+        }
+        n = 64;
+        if (n > host->buffer_bytes_left)
+                n = host->buffer_bytes_left;
+        host->buffer_bytes_left -= n;
+        host->total_bytes_left -= n;
+        host->data->bytes_xfered += n;
+
+        if (write) {
+                __raw_writesw(host->base + OMAP_MMC_REG_DATA, host->buffer, n);
+        } else {
+                __raw_readsw(host->base + OMAP_MMC_REG_DATA, host->buffer, n);
+        }
+}
+
+static inline void mmc_omap_report_irq(u16 status)
+{
+        static const char *mmc_omap_status_bits[] = {
+                "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
+                "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
+        };
+        int i, c = 0;
+
+        for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
+                if (status & (1 << i)) {
+                        if (c)
+                                printk(" ");
+                        printk("%s", mmc_omap_status_bits[i]);
+                        c++;
+                }
+}
+
+static irqreturn_t mmc_omap_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+        struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
+        u16 status;
+        int end_command;
+        int end_transfer;
+        int transfer_error;
+
+        if (host->cmd == NULL && host->data == NULL) {
+                status = OMAP_MMC_READ(host->base, STAT);
+                dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
+                if (status != 0) {
+                        OMAP_MMC_WRITE(host->base, STAT, status);
+                        OMAP_MMC_WRITE(host->base, IE, 0);
+                }
+                return IRQ_HANDLED;
+        }
+
+        end_command = 0;
+        end_transfer = 0;
+        transfer_error = 0;
+
+        while ((status = OMAP_MMC_READ(host->base, STAT)) != 0) {
+                OMAP_MMC_WRITE(host->base, STAT, status);
+#ifdef CONFIG_MMC_DEBUG
+                dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
+                        status, host->cmd != NULL ? host->cmd->opcode : -1);
+                mmc_omap_report_irq(status);
+                printk("\n");
+#endif
+                if (host->total_bytes_left) {
+                        if ((status & OMAP_MMC_STAT_A_FULL) ||
+                            (status & OMAP_MMC_STAT_END_OF_DATA))
+                                mmc_omap_xfer_data(host, 0);
+                        if (status & OMAP_MMC_STAT_A_EMPTY)
+                                mmc_omap_xfer_data(host, 1);
+                }
+
+                if (status & OMAP_MMC_STAT_END_OF_DATA) {
+                        end_transfer = 1;
+                }
+
+                if (status & OMAP_MMC_STAT_DATA_TOUT) {
+                        dev_dbg(mmc_dev(host->mmc), "data timeout\n");
+                        if (host->data) {
+                                host->data->error |= MMC_ERR_TIMEOUT;
+                                transfer_error = 1;
+                        }
+                }
+
+                if (status & OMAP_MMC_STAT_DATA_CRC) {
+                        if (host->data) {
+                                host->data->error |= MMC_ERR_BADCRC;
+                                dev_dbg(mmc_dev(host->mmc),
+                                         "data CRC error, bytes left %d\n",
+                                        host->total_bytes_left);
+                                transfer_error = 1;
+                        } else {
+                                dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
+                        }
+                }
+
+                if (status & OMAP_MMC_STAT_CMD_TOUT) {
+                        /* Timeouts are routine with some commands */
+                        if (host->cmd) {
+                                if (host->cmd->opcode != MMC_ALL_SEND_CID &&
+                                                host->cmd->opcode !=
+                                                MMC_SEND_OP_COND &&
+                                                host->cmd->opcode !=
+                                                MMC_APP_CMD &&
+                                                !mmc_omap_cover_is_open(host))
+                                        dev_err(mmc_dev(host->mmc),
+                                                "command timeout, CMD %d\n",
+                                                host->cmd->opcode);
+                                host->cmd->error = MMC_ERR_TIMEOUT;
+                                end_command = 1;
+                        }
+                }
+
+                if (status & OMAP_MMC_STAT_CMD_CRC) {
+                        if (host->cmd) {
+                                dev_err(mmc_dev(host->mmc),
+                                        "command CRC error (CMD%d, arg 0x%08x)\n",
+                                        host->cmd->opcode, host->cmd->arg);
+                                host->cmd->error = MMC_ERR_BADCRC;
+                                end_command = 1;
+                        } else
+                                dev_err(mmc_dev(host->mmc),
+                                        "command CRC error without cmd?\n");
+                }
+
+                if (status & OMAP_MMC_STAT_CARD_ERR) {
+                        if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
+                                u32 response = OMAP_MMC_READ(host->base, RSP6)
+                                        | (OMAP_MMC_READ(host->base, RSP7) << 16);
+                                /* STOP sometimes sets must-ignore bits */
+                                if (!(response & (R1_CC_ERROR
+                                                                | R1_ILLEGAL_COMMAND
+                                                                | R1_COM_CRC_ERROR))) {
+                                        end_command = 1;
+                                        continue;
+                                }
+                        }
+
+                        dev_dbg(mmc_dev(host->mmc), "card status error (CMD%d)\n",
+                                host->cmd->opcode);
+                        if (host->cmd) {
+                                host->cmd->error = MMC_ERR_FAILED;
+                                end_command = 1;
+                        }
+                        if (host->data) {
+                                host->data->error = MMC_ERR_FAILED;
+                                transfer_error = 1;
+                        }
+                }
+
+                /*
+                 * NOTE: On 1610 the END_OF_CMD may come too early when
+                 * starting a write 
+                 */
+                if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
+                    (!(status & OMAP_MMC_STAT_A_EMPTY))) {
+                        end_command = 1;
+                }
+        }
+
+        if (end_command) {
+                mmc_omap_cmd_done(host, host->cmd);
+        }
+        if (transfer_error)
+                mmc_omap_xfer_done(host, host->data);
+        else if (end_transfer)
+                mmc_omap_end_of_data(host, host->data);
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+        struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
+
+        schedule_work(&host->switch_work);
+
+        return IRQ_HANDLED;
+}
+
+static void mmc_omap_switch_timer(unsigned long arg)
+{
+        struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
+
+        schedule_work(&host->switch_work);
+}
+
+/* FIXME: Handle card insertion and removal properly. Maybe use a mask
+ * for MMC state? */
+static void mmc_omap_switch_callback(unsigned long data, u8 mmc_mask)
+{
+}
+
+static void mmc_omap_switch_handler(void *data)
+{
+        struct mmc_omap_host *host = (struct mmc_omap_host *) data;
+        struct mmc_card *card;
+        static int complained = 0;
+        int cards = 0, cover_open;
+
+        if (host->switch_pin == -1)
+                return;
+        cover_open = mmc_omap_cover_is_open(host);
+        if (cover_open != host->switch_last_state) {
+                kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
+                host->switch_last_state = cover_open;
+        }
+        mmc_detect_change(host->mmc, 0);
+        list_for_each_entry(card, &host->mmc->cards, node) {
+                if (mmc_card_present(card))
+                        cards++;
+        }
+        if (mmc_omap_cover_is_open(host)) {
+                if (!complained) {
+                        dev_info(mmc_dev(host->mmc), "cover is open");
+                        complained = 1;
+                }
+                if (mmc_omap_enable_poll)
+                        mod_timer(&host->switch_timer, jiffies +
+                                msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
+        } else {
+                complained = 0;
+        }
+}
+
+/* Prepare to transfer the next segment of a scatterlist */
+static void
+mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
+{
+        int dma_ch = host->dma_ch;
+        unsigned long data_addr;
+        u16 buf, frame;
+        u32 count;
+        struct scatterlist *sg = &data->sg[host->sg_idx];
+        int src_port = 0;
+        int dst_port = 0;
+        int sync_dev = 0;
+
+        data_addr = io_v2p((u32) host->base) + OMAP_MMC_REG_DATA;
+        frame = 1 << data->blksz_bits;
+        count = sg_dma_len(sg);
+
+        if ((data->blocks == 1) && (count > (1 << data->blksz_bits)))
+                count = frame;
+
+        host->dma_len = count;
+
+        /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
+         * Use 16 or 32 word frames when the blocksize is at least that large.
+         * Blocksize is usually 512 bytes; but not for some SD reads.
+         */
+        if (cpu_is_omap15xx() && frame > 32)
+                frame = 32;
+        else if (frame > 64)
+                frame = 64;
+        count /= frame;
+        frame >>= 1;
+
+        if (!(data->flags & MMC_DATA_WRITE)) {
+                buf = 0x800f | ((frame - 1) << 8);
+
+                if (cpu_class_is_omap1()) {
+                        src_port = OMAP_DMA_PORT_TIPB;
+                        dst_port = OMAP_DMA_PORT_EMIFF;
+                }
+                if (cpu_is_omap24xx())
+                        sync_dev = OMAP24XX_DMA_MMC1_RX;
+
+                omap_set_dma_src_params(dma_ch, src_port,
+                                        OMAP_DMA_AMODE_CONSTANT,
+                                        data_addr, 0, 0);
+                omap_set_dma_dest_params(dma_ch, dst_port,
+                                         OMAP_DMA_AMODE_POST_INC,
+                                         sg_dma_address(sg), 0, 0);
+                omap_set_dma_dest_data_pack(dma_ch, 1);
+                omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
+        } else {
+                buf = 0x0f80 | ((frame - 1) << 0);
+
+                if (cpu_class_is_omap1()) {
+                        src_port = OMAP_DMA_PORT_EMIFF;
+                        dst_port = OMAP_DMA_PORT_TIPB;
+                }
+                if (cpu_is_omap24xx())
+                        sync_dev = OMAP24XX_DMA_MMC1_TX;
+
+                omap_set_dma_dest_params(dma_ch, dst_port,
+                                         OMAP_DMA_AMODE_CONSTANT,
+                                         data_addr, 0, 0);
+                omap_set_dma_src_params(dma_ch, src_port,
+                                        OMAP_DMA_AMODE_POST_INC,
+                                        sg_dma_address(sg), 0, 0);
+                omap_set_dma_src_data_pack(dma_ch, 1);
+                omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
+        }
+
+        /* Max limit for DMA frame count is 0xffff */
+        if (unlikely(count > 0xffff))
+                BUG();
+
+        OMAP_MMC_WRITE(host->base, BUF, buf);
+        omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
+                                     frame, count, OMAP_DMA_SYNC_FRAME,
+                                     sync_dev, 0);
+}
+
+/* A scatterlist segment completed */
+static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
+{
+        struct mmc_omap_host *host = (struct mmc_omap_host *) data;
+        struct mmc_data *mmcdat = host->data;
+
+        if (unlikely(host->dma_ch < 0)) {
+                dev_err(mmc_dev(host->mmc), "DMA callback while DMA not
+                                enabled\n");
+                return;
+        }
+        /* FIXME: We really should do something to _handle_ the errors */
+        if (ch_status & OMAP_DMA_TOUT_IRQ) {
+                dev_err(mmc_dev(host->mmc),"DMA timeout\n");
+                return;
+        }
+        if (ch_status & OMAP_DMA_DROP_IRQ) {
+                dev_err(mmc_dev(host->mmc), "DMA sync error\n");
+                return;
+        }
+        if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
+                return;
+        }
+        mmcdat->bytes_xfered += host->dma_len;
+        host->sg_idx++;
+        if (host->sg_idx < host->sg_len) {
+                mmc_omap_prepare_dma(host, host->data);
+                omap_start_dma(host->dma_ch);
+        } else
+                mmc_omap_dma_done(host, host->data);
+}
+
+static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
+{
+        const char *dev_name;
+        int sync_dev, dma_ch, is_read, r;
+
+        is_read = !(data->flags & MMC_DATA_WRITE);
+        del_timer_sync(&host->dma_timer);
+        if (host->dma_ch >= 0) {
+                if (is_read == host->dma_is_read)
+                        return 0;
+                omap_free_dma(host->dma_ch);
+                host->dma_ch = -1;
+        }
+
+        if (is_read) {
+                if (host->id == 1) {
+                        sync_dev = OMAP_DMA_MMC_RX;
+                        dev_name = "MMC1 read";
+                } else {
+                        sync_dev = OMAP_DMA_MMC2_RX;
+                        dev_name = "MMC2 read";
+                }
+        } else {
+                if (host->id == 1) {
+                        sync_dev = OMAP_DMA_MMC_TX;
+                        dev_name = "MMC1 write";
+                } else {
+                        sync_dev = OMAP_DMA_MMC2_TX;
+                        dev_name = "MMC2 write";
+                }
+        }
+        r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
+                             host, &dma_ch);
+        if (r != 0) {
+                dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
+                return r;
+        }
+        host->dma_ch = dma_ch;
+        host->dma_is_read = is_read;
+
+        return 0;
+}
+
+static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
+{
+        u16 reg;
+
+        reg = OMAP_MMC_READ(host->base, SDIO);
+        reg &= ~(1 << 5);
+        OMAP_MMC_WRITE(host->base, SDIO, reg);
+        /* Set maximum timeout */
+        OMAP_MMC_WRITE(host->base, CTO, 0xff);
+}
+
+static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
+{
+        int timeout;
+        u16 reg;
+
+        /* Convert ns to clock cycles by assuming 20MHz frequency
+         * 1 cycle at 20MHz = 500 ns
+         */
+        timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
+
+        /* Check if we need to use timeout multiplier register */
+        reg = OMAP_MMC_READ(host->base, SDIO);
+        if (timeout > 0xffff) {
+                reg |= (1 << 5);
+                timeout /= 1024;
+        } else
+                reg &= ~(1 << 5);
+        OMAP_MMC_WRITE(host->base, SDIO, reg);
+        OMAP_MMC_WRITE(host->base, DTO, timeout);
+}
+
+static void
+mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
+{
+        struct mmc_data *data = req->data;
+        int i, use_dma, block_size;
+        unsigned sg_len;
+
+        host->data = data;
+        if (data == NULL) {
+                OMAP_MMC_WRITE(host->base, BLEN, 0);
+                OMAP_MMC_WRITE(host->base, NBLK, 0);
+                OMAP_MMC_WRITE(host->base, BUF, 0);
+                host->dma_in_use = 0;
+                set_cmd_timeout(host, req);
+                return;
+        }
+
+
+        block_size = 1 << data->blksz_bits;
+
+        OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1);
+        OMAP_MMC_WRITE(host->base, BLEN, block_size - 1);
+        set_data_timeout(host, req);
+
+        /* cope with calling layer confusion; it issues "single
+         * block" writes using multi-block scatterlists.
+         */
+        sg_len = (data->blocks == 1) ? 1 : data->sg_len;
+
+        /* Only do DMA for entire blocks */
+        use_dma = host->use_dma;
+        if (use_dma) {
+                for (i = 0; i < sg_len; i++) {
+                        if ((data->sg[i].length % block_size) != 0) {
+                                use_dma = 0;
+                                break;
+                        }
+                }
+        }
+
+        host->sg_idx = 0;
+        if (use_dma) {
+                if (mmc_omap_get_dma_channel(host, data) == 0) {
+                        enum dma_data_direction dma_data_dir;
+
+                        if (data->flags & MMC_DATA_WRITE)
+                                dma_data_dir = DMA_TO_DEVICE;
+                        else
+                                dma_data_dir = DMA_FROM_DEVICE;
+
+                        host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
+                                                sg_len, dma_data_dir);
+                        host->total_bytes_left = 0;
+                        mmc_omap_prepare_dma(host, req->data);
+                        host->brs_received = 0;
+                        host->dma_done = 0;
+                        host->dma_in_use = 1;
+                } else
+                        use_dma = 0;
+        }
+
+        /* Revert to PIO? */
+        if (!use_dma) {
+                OMAP_MMC_WRITE(host->base, BUF, 0x1f1f);
+                host->total_bytes_left = data->blocks * block_size;
+                host->sg_len = sg_len;
+                mmc_omap_sg_to_buf(host);
+                host->dma_in_use = 0;
+        }
+}
+
+static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
+{
+        struct mmc_omap_host *host = mmc_priv(mmc);
+
+        WARN_ON(host->mrq != NULL);
+
+        host->mrq = req;
+
+        /* only touch fifo AFTER the controller readies it */
+        mmc_omap_prepare_data(host, req);
+        mmc_omap_start_command(host, req->cmd);
+        if (host->dma_in_use)
+                omap_start_dma(host->dma_ch);
+}
+
+static void innovator_fpga_socket_power(int on)
+{
+#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
+
+        if (on) {
+                fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
+                     OMAP1510_FPGA_POWER);
+        } else {
+                fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
+                     OMAP1510_FPGA_POWER);
+        }
+#endif
+}
+
+/*
+ * Turn the socket power on/off. Innovator uses FPGA, most boards
+ * probably use GPIO.
+ */
+static void mmc_omap_power(struct mmc_omap_host *host, int on)
+{
+        if (on) {
+                if (machine_is_omap_innovator())
+                        innovator_fpga_socket_power(1);
+                else if (machine_is_omap_h2())
+                        tps65010_set_gpio_out_value(GPIO3, HIGH);
+                else if (machine_is_omap_h3())
+                        /* GPIO 4 of TPS65010 sends SD_EN signal */
+                        tps65010_set_gpio_out_value(GPIO4, HIGH);
+                else if (cpu_is_omap24xx()) {
+                        u16 reg = OMAP_MMC_READ(host->base, CON);
+                        OMAP_MMC_WRITE(host->base, CON, reg | (1 << 11));
+                } else
+                        if (host->power_pin >= 0)
+                                omap_set_gpio_dataout(host->power_pin, 1);
+        } else {
+                if (machine_is_omap_innovator())
+                        innovator_fpga_socket_power(0);
+                else if (machine_is_omap_h2())
+                        tps65010_set_gpio_out_value(GPIO3, LOW);
+                else if (machine_is_omap_h3())
+                        tps65010_set_gpio_out_value(GPIO4, LOW);
+                else if (cpu_is_omap24xx()) {
+                        u16 reg = OMAP_MMC_READ(host->base, CON);
+                        OMAP_MMC_WRITE(host->base, CON, reg & ~(1 << 11));
+                } else
+                        if (host->power_pin >= 0)
+                                omap_set_gpio_dataout(host->power_pin, 0);
+        }
+}
+
+static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+        struct mmc_omap_host *host = mmc_priv(mmc);
+        int dsor;
+        int realclock, i;
+
+        realclock = ios->clock;
+
+        if (ios->clock == 0)
+                dsor = 0;
+        else {
+                int func_clk_rate = clk_get_rate(host->fclk);
+
+                dsor = func_clk_rate / realclock;
+                if (dsor < 1)
+                        dsor = 1;
+
+                if (func_clk_rate / dsor > realclock)
+                        dsor++;
+
+                if (dsor > 250)
+                        dsor = 250;
+                dsor++;
+
+                if (ios->bus_width == MMC_BUS_WIDTH_4)
+                        dsor |= 1 << 15;
+        }
+
+        switch (ios->power_mode) {
+        case MMC_POWER_OFF:
+                mmc_omap_power(host, 0);
+                break;
+        case MMC_POWER_UP:
+        case MMC_POWER_ON:
+                mmc_omap_power(host, 1);
+                dsor |= 1<<11;
+                break;
+        }
+
+        host->bus_mode = ios->bus_mode;
+        host->hw_bus_mode = host->bus_mode;
+
+        clk_enable(host->fclk);
+
+        /* On insanely high arm_per frequencies something sometimes
+         * goes somehow out of sync, and the POW bit is not being set,
+         * which results in the while loop below getting stuck.
+         * Writing to the CON register twice seems to do the trick. */
+        for (i = 0; i < 2; i++)
+                OMAP_MMC_WRITE(host->base, CON, dsor);
+        if (ios->power_mode == MMC_POWER_UP) {
+                /* Send clock cycles, poll completion */
+                OMAP_MMC_WRITE(host->base, IE, 0);
+                OMAP_MMC_WRITE(host->base, STAT, 0xffff);
+                OMAP_MMC_WRITE(host->base, CMD, 1<<7);
+                while (0 == (OMAP_MMC_READ(host->base, STAT) & 1));
+                OMAP_MMC_WRITE(host->base, STAT, 1);
+        }
+        clk_disable(host->fclk);
+}
+
+static int mmc_omap_get_ro(struct mmc_host *mmc)
+{
+        struct mmc_omap_host *host = mmc_priv(mmc);
+
+        return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
+}
+
+static struct mmc_host_ops mmc_omap_ops = {
+        .request        = mmc_omap_request,
+        .set_ios        = mmc_omap_set_ios,
+        .get_ro         = mmc_omap_get_ro,
+};
+
+static int __init mmc_omap_probe(struct platform_device *pdev)
+{
+        struct omap_mmc_conf *minfo = pdev->dev.platform_data;
+        struct mmc_host *mmc;
+        struct mmc_omap_host *host = NULL;
+        int ret = 0;
+        
+        if (platform_get_resource(pdev, IORESOURCE_MEM, 0) ||
+                        platform_get_irq(pdev, IORESOURCE_IRQ, 0)) {
+                dev_err(&pdev->dev, "mmc_omap_probe: invalid resource type\n");
+                return -ENODEV;
+        }
+
+        if (!request_mem_region(pdev->resource[0].start,
+                                pdev->resource[0].end - pdev->resource[0].start + 1,
+                                pdev->name)) {
+                dev_dbg(&pdev->dev, "request_mem_region failed\n");
+                return -EBUSY;
+        }
+
+        mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
+        if (!mmc) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        host = mmc_priv(mmc);
+        host->mmc = mmc;
+
+        spin_lock_init(&host->dma_lock);
+        init_timer(&host->dma_timer);
+        host->dma_timer.function = mmc_omap_dma_timer;
+        host->dma_timer.data = (unsigned long) host;
+
+        host->id = pdev->id;
+
+        if (cpu_is_omap24xx()) {
+                host->iclk = clk_get(&pdev->dev, "mmc_ick");
+                if (IS_ERR(host->iclk))
+                        goto out;
+                clk_enable(host->iclk);
+        }
+
+        if (!cpu_is_omap24xx())
+                host->fclk = clk_get(&pdev->dev, "mmc_ck");
+        else
+                host->fclk = clk_get(&pdev->dev, "mmc_fck");
+
+        if (IS_ERR(host->fclk)) {
+                ret = PTR_ERR(host->fclk);
+                goto out;
+        }
+
+        /* REVISIT:
+         * Also, use minfo->cover to decide how to manage
+         * the card detect sensing.
+         */
+        host->power_pin = minfo->power_pin;
+        host->switch_pin = minfo->switch_pin;
+        host->wp_pin = minfo->wp_pin;
+        host->use_dma = 1;
+        host->dma_ch = -1;
+
+        host->irq = pdev->resource[1].start;
+        host->base = ioremap(pdev->res.start, SZ_4K);
+        if (!host->base) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+         if (minfo->wire4)
+                 mmc->caps |= MMC_CAP_4_BIT_DATA;
+
+        mmc->ops = &mmc_omap_ops;
+        mmc->f_min = 400000;
+        mmc->f_max = 24000000;
+        mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
+
+        /* Use scatterlist DMA to reduce per-transfer costs.
+         * NOTE max_seg_size assumption that small blocks aren't
+         * normally used (except e.g. for reading SD registers).
+         */
+        mmc->max_phys_segs = 32;
+        mmc->max_hw_segs = 32;
+        mmc->max_sectors = 256; /* NBLK max 11-bits, OMAP also limited by DMA */
+        mmc->max_seg_size = mmc->max_sectors * 512;
+
+        if (host->power_pin >= 0) {
+                if ((ret = omap_request_gpio(host->power_pin)) != 0) {
+                        dev_err(mmc_dev(host->mmc), "Unable to get GPIO
+                                        pin for MMC power\n");
+                        goto out;
+                }
+                omap_set_gpio_direction(host->power_pin, 0);
+        }
+
+        ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
+        if (ret)
+                goto out;
+
+        host->dev = &pdev->dev;
+        platform_set_drvdata(pdev, host);
+
+        mmc_add_host(mmc);
+
+        if (host->switch_pin >= 0) {
+                INIT_WORK(&host->switch_work, mmc_omap_switch_handler, host);
+                init_timer(&host->switch_timer);
+                host->switch_timer.function = mmc_omap_switch_timer;
+                host->switch_timer.data = (unsigned long) host;
+                if (omap_request_gpio(host->switch_pin) != 0) {
+                        dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
+                        host->switch_pin = -1;
+                        goto no_switch;
+                }
+
+                omap_set_gpio_direction(host->switch_pin, 1);
+                ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
+                                  mmc_omap_switch_irq, SA_TRIGGER_RISING, DRIVER_NAME, host);
+                if (ret) {
+                        dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
+                        omap_free_gpio(host->switch_pin);
+                        host->switch_pin = -1;
+                        goto no_switch;
+                }
+                ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
+                if (ret == 0) {
+                        ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
+                        if (ret != 0)
+                                device_remove_file(&pdev->dev, &dev_attr_cover_switch);
+                }
+                if (ret) {
+                        dev_wan(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
+                        free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
+                        omap_free_gpio(host->switch_pin);
+                        host->switch_pin = -1;
+                        goto no_switch;
+                }
+                if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
+                        schedule_work(&host->switch_work);
+        }
+
+no_switch:
+        return 0;
+
+out:
+        /* FIXME: Free other resources too. */
+        if (host) {
+                if (host->iclk && !IS_ERR(host->iclk))
+                        clk_put(host->iclk);
+                if (host->fclk && !IS_ERR(host->fclk))
+                        clk_put(host->fclk);
+                mmc_free_host(host->mmc);
+        }
+        return ret;
+}
+
+static int mmc_omap_remove(struct platform_device *pdev)
+{
+        struct mmc_omap_host *host = platform_get_drvdata(pdev);
+
+        platform_set_drvdata(pdev, NULL);
+
+        if (host) {
+                mmc_remove_host(host->mmc);
+                free_irq(host->irq, host);
+
+                if (host->power_pin >= 0)
+                        omap_free_gpio(host->power_pin);
+                if (host->switch_pin >= 0) {
+                        device_remove_file(&pdev->dev, &dev_attr_enable_poll);
+                        device_remove_file(&pdev->dev, &dev_attr_cover_switch);
+                        free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
+                        omap_free_gpio(host->switch_pin);
+                        host->switch_pin = -1;
+                        del_timer_sync(&host->switch_timer);
+                        flush_scheduled_work();
+                }
+                if (host->iclk && !IS_ERR(host->iclk))
+                        clk_put(host->iclk);
+                if (host->fclk && !IS_ERR(host->fclk))
+                        clk_put(host->fclk);
+                mmc_free_host(host->mmc);
+        }
+
+        release_mem_region(pdev->resource[0].start,
+                        pdev->resource[0].end - pdev->resource[0].start + 1);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+        int ret = 0;
+        struct mmc_omap_host *host = platform_get_drvdata(pdev);
+
+        if (host && host->suspended)
+                return 0;
+
+        if (host) {
+                ret = mmc_suspend_host(host->mmc, mesg);
+                if (ret == 0)
+                        host->suspended = 1;
+        }
+        return ret;
+}
+
+static int mmc_omap_resume(struct platform_device *pdev)
+{
+        int ret = 0;
+        struct mmc_omap_host *host = platform_get_drvdata(pdev);
+
+        if (host && !host->suspended)
+                return 0;
+
+        if (host) {
+                ret = mmc_resume_host(host->mmc);
+                if (ret == 0)
+                        host->suspended = 0;
+        }
+
+        return ret;
+}
+#else
+#define mmc_omap_suspend        NULL
+#define mmc_omap_resume         NULL
+#endif
+
+static struct platform_driver mmc_omap_driver = {
+        .probe          = mmc_omap_probe,
+        .remove         = mmc_omap_remove,
+        .suspend        = mmc_omap_suspend,
+        .resume         = mmc_omap_resume,
+        .driver         = {
+                .name   = DRIVER_NAME,
+        },
+};
+
+static int __init mmc_omap_init(void)
+{
+        return platform_driver_register(&mmc_omap_driver);
+}
+
+static void __exit mmc_omap_exit(void)
+{
+        platform_driver_unregister(&mmc_omap_driver);
+}
+
+module_init(mmc_omap_init);
+module_exit(mmc_omap_exit);
+
+MODULE_DESCRIPTION("OMAP Multimedia Card driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS(DRIVER_NAME);
+MODULE_AUTHOR("Juha Yrjölä");
diff --git a/drivers/mmc/omap.h b/drivers/mmc/omap.h
new file mode 100644
index 000000000000..c954d355a5e3
--- /dev/null
+++ b/drivers/mmc/omap.h
@@ -0,0 +1,55 @@
+#ifndef DRIVERS_MEDIA_MMC_OMAP_H
+#define DRIVERS_MEDIA_MMC_OMAP_H
+
+#define OMAP_MMC_REG_CMD        0x00
+#define OMAP_MMC_REG_ARGL       0x04
+#define OMAP_MMC_REG_ARGH       0x08
+#define OMAP_MMC_REG_CON        0x0c
+#define OMAP_MMC_REG_STAT       0x10
+#define OMAP_MMC_REG_IE         0x14
+#define OMAP_MMC_REG_CTO        0x18
+#define OMAP_MMC_REG_DTO        0x1c
+#define OMAP_MMC_REG_DATA       0x20
+#define OMAP_MMC_REG_BLEN       0x24
+#define OMAP_MMC_REG_NBLK       0x28
+#define OMAP_MMC_REG_BUF        0x2c
+#define OMAP_MMC_REG_SDIO       0x34
+#define OMAP_MMC_REG_REV        0x3c
+#define OMAP_MMC_REG_RSP0       0x40
+#define OMAP_MMC_REG_RSP1       0x44
+#define OMAP_MMC_REG_RSP2       0x48
+#define OMAP_MMC_REG_RSP3       0x4c
+#define OMAP_MMC_REG_RSP4       0x50
+#define OMAP_MMC_REG_RSP5       0x54
+#define OMAP_MMC_REG_RSP6       0x58
+#define OMAP_MMC_REG_RSP7       0x5c
+#define OMAP_MMC_REG_IOSR       0x60
+#define OMAP_MMC_REG_SYSC       0x64
+#define OMAP_MMC_REG_SYSS       0x68
+
+#define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
+#define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
+#define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
+#define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
+#define OMAP_MMC_STAT_A_FULL            (1 << 10)
+#define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
+#define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
+#define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
+#define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
+#define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
+#define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
+#define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
+#define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
+
+#define OMAP_MMC_READ(base, reg)        __raw_readw((base) + OMAP_MMC_REG_##reg)
+#define OMAP_MMC_WRITE(base, reg, val)  __raw_writew((val), (base) + OMAP_MMC_REG_##reg)
+
+/*
+ * Command types
+ */
+#define OMAP_MMC_CMDTYPE_BC     0
+#define OMAP_MMC_CMDTYPE_BCR    1
+#define OMAP_MMC_CMDTYPE_AC     2
+#define OMAP_MMC_CMDTYPE_ADTC   3
+
+#endif
diff --git a/drivers/mmc/pxamci.c b/drivers/mmc/pxamci.c
index c32fad1ce51c..eb9a8826e9b5 100644
--- a/drivers/mmc/pxamci.c
+++ b/drivers/mmc/pxamci.c
@@ -37,12 +37,6 @@
 
 #include "pxamci.h"
 
-#ifdef CONFIG_MMC_DEBUG
-#define DBG(x...)       printk(KERN_DEBUG x)
-#else
-#define DBG(x...)       do { } while (0)
-#endif
-
 #define DRIVER_NAME     "pxa2xx-mci"
 
 #define NR_SG   1
@@ -206,7 +200,7 @@ static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd,
 
 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
 {
-        DBG("PXAMCI: request done\n");
+        pr_debug("PXAMCI: request done\n");
         host->mrq = NULL;
         host->cmd = NULL;
         host->data = NULL;
@@ -252,7 +246,7 @@ static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
                         if ((cmd->resp[0] & 0x80000000) == 0)
                                 cmd->error = MMC_ERR_BADCRC;
                 } else {
-                        DBG("ignoring CRC from command %d - *risky*\n",cmd->opcode);
+                        pr_debug("ignoring CRC from command %d - *risky*\n",cmd->opcode);
                 }
 #else
                 cmd->error = MMC_ERR_BADCRC;
@@ -317,12 +311,12 @@ static irqreturn_t pxamci_irq(int irq, void *devid, struct pt_regs *regs)
 
         ireg = readl(host->base + MMC_I_REG);
 
-        DBG("PXAMCI: irq %08x\n", ireg);
+        pr_debug("PXAMCI: irq %08x\n", ireg);
 
         if (ireg) {
                 unsigned stat = readl(host->base + MMC_STAT);
 
-                DBG("PXAMCI: stat %08x\n", stat);
+                pr_debug("PXAMCI: stat %08x\n", stat);
 
                 if (ireg & END_CMD_RES)
                         handled |= pxamci_cmd_done(host, stat);
@@ -376,9 +370,9 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
         struct pxamci_host *host = mmc_priv(mmc);
 
-        DBG("pxamci_set_ios: clock %u power %u vdd %u.%02u\n",
-            ios->clock, ios->power_mode, ios->vdd / 100,
-            ios->vdd % 100);
+        pr_debug("pxamci_set_ios: clock %u power %u vdd %u.%02u\n",
+                 ios->clock, ios->power_mode, ios->vdd / 100,
+                 ios->vdd % 100);
 
         if (ios->clock) {
                 unsigned int clk = CLOCKRATE / ios->clock;
@@ -405,8 +399,8 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
                         host->cmdat |= CMDAT_INIT;
         }
 
-        DBG("pxamci_set_ios: clkrt = %x cmdat = %x\n",
-            host->clkrt, host->cmdat);
+        pr_debug("pxamci_set_ios: clkrt = %x cmdat = %x\n",
+                 host->clkrt, host->cmdat);
 }
 
 static struct mmc_host_ops pxamci_ops = {
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 8b811d94371c..bdbfca050029 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -31,12 +31,8 @@
 
 #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
 
-#ifdef CONFIG_MMC_DEBUG
 #define DBG(f, x...) \
-        printk(KERN_DEBUG DRIVER_NAME " [%s()]: " f, __func__,## x)
-#else
-#define DBG(f, x...) do { } while (0)
-#endif
+        pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
 
 static const struct pci_device_id pci_ids[] __devinitdata = {
         /* handle any SD host controller */
diff --git a/drivers/mmc/wbsd.c b/drivers/mmc/wbsd.c
index 3be397d436fa..511f7b0b31d2 100644
--- a/drivers/mmc/wbsd.c
+++ b/drivers/mmc/wbsd.c
@@ -44,15 +44,10 @@
 #define DRIVER_NAME "wbsd"
 #define DRIVER_VERSION "1.5"
 
-#ifdef CONFIG_MMC_DEBUG
 #define DBG(x...) \
-        printk(KERN_DEBUG DRIVER_NAME ": " x)
+        pr_debug(DRIVER_NAME ": " x)
 #define DBGF(f, x...) \
-        printk(KERN_DEBUG DRIVER_NAME " [%s()]: " f, __func__ , ##x)
-#else
-#define DBG(x...)       do { } while (0)
-#define DBGF(x...)      do { } while (0)
-#endif
+        pr_debug(DRIVER_NAME " [%s()]: " f, __func__ , ##x)
 
 /*
  * Device resources