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authorPhilipp Zabel <philipp.zabel@gmail.com>2009-06-04 14:12:31 -0400
committerPierre Ossman <pierre@ossman.eu>2009-06-13 16:42:59 -0400
commitf0e46cc4971f6be96010d9248e0fc076b229d989 (patch)
tree5fc0b80993c82337b8928f063df0749fadc9d13e /drivers/mmc
parentfdd858db7113ca64132de390188d7ca00701013d (diff)
MFD,mmc: tmio_mmc: make HCLK configurable
The Toshiba parts all have a 24 MHz HCLK, but HTC ASIC3 has a 24.576 MHz HCLK and AMD Imageon w228x's HCLK is 80 MHz. With this patch, the MFD driver provides the HCLK frequency to tmio_mmc via mfd_cell->driver_data. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Acked-by: Ian Molton <ian@mnementh.co.uk> Acked-by: Samuel Ortiz <sameo@openedhand.com> Signed-off-by: Pierre Ossman <pierre@ossman.eu>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/tmio_mmc.c24
1 files changed, 11 insertions, 13 deletions
diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
index 63fbd5b7d312..49df71e6be17 100644
--- a/drivers/mmc/host/tmio_mmc.c
+++ b/drivers/mmc/host/tmio_mmc.c
@@ -35,23 +35,14 @@
35 35
36#include "tmio_mmc.h" 36#include "tmio_mmc.h"
37 37
38/*
39 * Fixme - documentation conflicts on what the clock values are for the
40 * various dividers.
41 * One document I have says that its a divisor of a 24MHz clock, another 33.
42 * This probably depends on HCLK for a given platform, so we may need to
43 * require HCLK be passed to us from the MFD core.
44 *
45 */
46
47static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock) 38static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
48{ 39{
49 void __iomem *cnf = host->cnf; 40 void __iomem *cnf = host->cnf;
50 void __iomem *ctl = host->ctl; 41 void __iomem *ctl = host->ctl;
51 u32 clk = 0, clock; 42 u32 clk = 0, clock, f_min = host->mmc->f_min;
52 43
53 if (new_clock) { 44 if (new_clock) {
54 for (clock = 46875, clk = 0x100; new_clock >= (clock<<1); ) { 45 for (clock = f_min, clk = 0x100; new_clock >= (clock<<1); ) {
55 clock <<= 1; 46 clock <<= 1;
56 clk >>= 1; 47 clk >>= 1;
57 } 48 }
@@ -545,6 +536,7 @@ out:
545static int __devinit tmio_mmc_probe(struct platform_device *dev) 536static int __devinit tmio_mmc_probe(struct platform_device *dev)
546{ 537{
547 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; 538 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
539 struct tmio_mmc_data *pdata;
548 struct resource *res_ctl, *res_cnf; 540 struct resource *res_ctl, *res_cnf;
549 struct tmio_mmc_host *host; 541 struct tmio_mmc_host *host;
550 struct mmc_host *mmc; 542 struct mmc_host *mmc;
@@ -560,6 +552,12 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
560 goto out; 552 goto out;
561 } 553 }
562 554
555 pdata = cell->driver_data;
556 if (!pdata || !pdata->hclk) {
557 ret = -EINVAL;
558 goto out;
559 }
560
563 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev); 561 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev);
564 if (!mmc) 562 if (!mmc)
565 goto out; 563 goto out;
@@ -578,8 +576,8 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
578 576
579 mmc->ops = &tmio_mmc_ops; 577 mmc->ops = &tmio_mmc_ops;
580 mmc->caps = MMC_CAP_4_BIT_DATA; 578 mmc->caps = MMC_CAP_4_BIT_DATA;
581 mmc->f_min = 46875; /* 24000000 / 512 */ 579 mmc->f_max = pdata->hclk;
582 mmc->f_max = 24000000; 580 mmc->f_min = mmc->f_max / 512;
583 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 581 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
584 582
585 /* Enable the MMC/SD Control registers */ 583 /* Enable the MMC/SD Control registers */