diff options
author | Wolfram Sang <w.sang@pengutronix.de> | 2010-10-15 06:21:03 -0400 |
---|---|---|
committer | Chris Ball <cjb@laptop.org> | 2010-10-23 09:11:22 -0400 |
commit | 80872e21b0263f016f2edb7b72dd8be5636d7ca7 (patch) | |
tree | d20f4595f8e4dede60fbf14a6787ccbed1827eae /drivers/mmc | |
parent | 012994f4fa5fc7663b51fa921c85c0a352339b24 (diff) |
mmc: sdhci-of-esdhc: factor out common stuff
Put everything which can be shared between the OF and platform version
of this driver into a local .h file.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Tested-by: Eric BĂ©nard <eric@eukrea.com>
[cjb: fix compile error: sdhci-esdhc.c->sdhci-esdhc.h]
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r-- | drivers/mmc/host/sdhci-esdhc.h | 83 | ||||
-rw-r--r-- | drivers/mmc/host/sdhci-of-esdhc.c | 70 |
2 files changed, 91 insertions, 62 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h new file mode 100644 index 000000000000..afaf1bc4913a --- /dev/null +++ b/drivers/mmc/host/sdhci-esdhc.h | |||
@@ -0,0 +1,83 @@ | |||
1 | /* | ||
2 | * Freescale eSDHC controller driver generics for OF and pltfm. | ||
3 | * | ||
4 | * Copyright (c) 2007 Freescale Semiconductor, Inc. | ||
5 | * Copyright (c) 2009 MontaVista Software, Inc. | ||
6 | * Copyright (c) 2010 Pengutronix e.K. | ||
7 | * Author: Wolfram Sang <w.sang@pengutronix.de> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | */ | ||
13 | |||
14 | #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H | ||
15 | #define _DRIVERS_MMC_SDHCI_ESDHC_H | ||
16 | |||
17 | /* | ||
18 | * Ops and quirks for the Freescale eSDHC controller. | ||
19 | */ | ||
20 | |||
21 | #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ | ||
22 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | \ | ||
23 | SDHCI_QUIRK_NO_BUSY_IRQ | \ | ||
24 | SDHCI_QUIRK_NONSTANDARD_CLOCK | \ | ||
25 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ | ||
26 | SDHCI_QUIRK_PIO_NEEDS_DELAY | \ | ||
27 | SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET | \ | ||
28 | SDHCI_QUIRK_NO_CARD_NO_RESET) | ||
29 | |||
30 | #define ESDHC_SYSTEM_CONTROL 0x2c | ||
31 | #define ESDHC_CLOCK_MASK 0x0000fff0 | ||
32 | #define ESDHC_PREDIV_SHIFT 8 | ||
33 | #define ESDHC_DIVIDER_SHIFT 4 | ||
34 | #define ESDHC_CLOCK_PEREN 0x00000004 | ||
35 | #define ESDHC_CLOCK_HCKEN 0x00000002 | ||
36 | #define ESDHC_CLOCK_IPGEN 0x00000001 | ||
37 | |||
38 | /* pltfm-specific */ | ||
39 | #define ESDHC_HOST_CONTROL_LE 0x20 | ||
40 | |||
41 | /* OF-specific */ | ||
42 | #define ESDHC_DMA_SYSCTL 0x40c | ||
43 | #define ESDHC_DMA_SNOOP 0x00000040 | ||
44 | |||
45 | #define ESDHC_HOST_CONTROL_RES 0x05 | ||
46 | |||
47 | static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock) | ||
48 | { | ||
49 | int pre_div = 2; | ||
50 | int div = 1; | ||
51 | u32 temp; | ||
52 | |||
53 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); | ||
54 | temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ||
55 | | ESDHC_CLOCK_MASK); | ||
56 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | ||
57 | |||
58 | if (clock == 0) | ||
59 | goto out; | ||
60 | |||
61 | while (host->max_clk / pre_div / 16 > clock && pre_div < 256) | ||
62 | pre_div *= 2; | ||
63 | |||
64 | while (host->max_clk / pre_div / div > clock && div < 16) | ||
65 | div++; | ||
66 | |||
67 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", | ||
68 | clock, host->max_clk / pre_div / div); | ||
69 | |||
70 | pre_div >>= 1; | ||
71 | div--; | ||
72 | |||
73 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); | ||
74 | temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ||
75 | | (div << ESDHC_DIVIDER_SHIFT) | ||
76 | | (pre_div << ESDHC_PREDIV_SHIFT)); | ||
77 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | ||
78 | mdelay(100); | ||
79 | out: | ||
80 | host->clock = clock; | ||
81 | } | ||
82 | |||
83 | #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ | ||
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index c8623de13af3..fcd0e1fcba44 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c | |||
@@ -18,23 +18,7 @@ | |||
18 | #include <linux/mmc/host.h> | 18 | #include <linux/mmc/host.h> |
19 | #include "sdhci-of.h" | 19 | #include "sdhci-of.h" |
20 | #include "sdhci.h" | 20 | #include "sdhci.h" |
21 | 21 | #include "sdhci-esdhc.h" | |
22 | /* | ||
23 | * Ops and quirks for the Freescale eSDHC controller. | ||
24 | */ | ||
25 | |||
26 | #define ESDHC_DMA_SYSCTL 0x40c | ||
27 | #define ESDHC_DMA_SNOOP 0x00000040 | ||
28 | |||
29 | #define ESDHC_SYSTEM_CONTROL 0x2c | ||
30 | #define ESDHC_CLOCK_MASK 0x0000fff0 | ||
31 | #define ESDHC_PREDIV_SHIFT 8 | ||
32 | #define ESDHC_DIVIDER_SHIFT 4 | ||
33 | #define ESDHC_CLOCK_PEREN 0x00000004 | ||
34 | #define ESDHC_CLOCK_HCKEN 0x00000002 | ||
35 | #define ESDHC_CLOCK_IPGEN 0x00000001 | ||
36 | |||
37 | #define ESDHC_HOST_CONTROL_RES 0x05 | ||
38 | 22 | ||
39 | static u16 esdhc_readw(struct sdhci_host *host, int reg) | 23 | static u16 esdhc_readw(struct sdhci_host *host, int reg) |
40 | { | 24 | { |
@@ -68,51 +52,20 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg) | |||
68 | sdhci_be32bs_writeb(host, val, reg); | 52 | sdhci_be32bs_writeb(host, val, reg); |
69 | } | 53 | } |
70 | 54 | ||
71 | static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock) | 55 | static int esdhc_of_enable_dma(struct sdhci_host *host) |
72 | { | ||
73 | int pre_div = 2; | ||
74 | int div = 1; | ||
75 | |||
76 | clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN | | ||
77 | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); | ||
78 | |||
79 | if (clock == 0) | ||
80 | goto out; | ||
81 | |||
82 | while (host->max_clk / pre_div / 16 > clock && pre_div < 256) | ||
83 | pre_div *= 2; | ||
84 | |||
85 | while (host->max_clk / pre_div / div > clock && div < 16) | ||
86 | div++; | ||
87 | |||
88 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", | ||
89 | clock, host->max_clk / pre_div / div); | ||
90 | |||
91 | pre_div >>= 1; | ||
92 | div--; | ||
93 | |||
94 | setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN | | ||
95 | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | | ||
96 | div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT); | ||
97 | mdelay(100); | ||
98 | out: | ||
99 | host->clock = clock; | ||
100 | } | ||
101 | |||
102 | static int esdhc_enable_dma(struct sdhci_host *host) | ||
103 | { | 56 | { |
104 | setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP); | 57 | setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP); |
105 | return 0; | 58 | return 0; |
106 | } | 59 | } |
107 | 60 | ||
108 | static unsigned int esdhc_get_max_clock(struct sdhci_host *host) | 61 | static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) |
109 | { | 62 | { |
110 | struct sdhci_of_host *of_host = sdhci_priv(host); | 63 | struct sdhci_of_host *of_host = sdhci_priv(host); |
111 | 64 | ||
112 | return of_host->clock; | 65 | return of_host->clock; |
113 | } | 66 | } |
114 | 67 | ||
115 | static unsigned int esdhc_get_min_clock(struct sdhci_host *host) | 68 | static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) |
116 | { | 69 | { |
117 | struct sdhci_of_host *of_host = sdhci_priv(host); | 70 | struct sdhci_of_host *of_host = sdhci_priv(host); |
118 | 71 | ||
@@ -120,14 +73,7 @@ static unsigned int esdhc_get_min_clock(struct sdhci_host *host) | |||
120 | } | 73 | } |
121 | 74 | ||
122 | struct sdhci_of_data sdhci_esdhc = { | 75 | struct sdhci_of_data sdhci_esdhc = { |
123 | .quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 | | 76 | .quirks = ESDHC_DEFAULT_QUIRKS, |
124 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | | ||
125 | SDHCI_QUIRK_NO_BUSY_IRQ | | ||
126 | SDHCI_QUIRK_NONSTANDARD_CLOCK | | ||
127 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | | ||
128 | SDHCI_QUIRK_PIO_NEEDS_DELAY | | ||
129 | SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET | | ||
130 | SDHCI_QUIRK_NO_CARD_NO_RESET, | ||
131 | .ops = { | 77 | .ops = { |
132 | .read_l = sdhci_be32bs_readl, | 78 | .read_l = sdhci_be32bs_readl, |
133 | .read_w = esdhc_readw, | 79 | .read_w = esdhc_readw, |
@@ -136,8 +82,8 @@ struct sdhci_of_data sdhci_esdhc = { | |||
136 | .write_w = esdhc_writew, | 82 | .write_w = esdhc_writew, |
137 | .write_b = esdhc_writeb, | 83 | .write_b = esdhc_writeb, |
138 | .set_clock = esdhc_set_clock, | 84 | .set_clock = esdhc_set_clock, |
139 | .enable_dma = esdhc_enable_dma, | 85 | .enable_dma = esdhc_of_enable_dma, |
140 | .get_max_clock = esdhc_get_max_clock, | 86 | .get_max_clock = esdhc_of_get_max_clock, |
141 | .get_min_clock = esdhc_get_min_clock, | 87 | .get_min_clock = esdhc_of_get_min_clock, |
142 | }, | 88 | }, |
143 | }; | 89 | }; |