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authorDan Williams <dan.j.williams@intel.com>2009-09-08 20:55:21 -0400
committerDan Williams <dan.j.williams@intel.com>2009-09-08 20:55:21 -0400
commitbbb20089a3275a19e475dbc21320c3742e3ca423 (patch)
tree216fdc1cbef450ca688135c5b8969169482d9a48 /drivers/mmc
parent3e48e656903e9fd8bc805c6a2c4264d7808d315b (diff)
parent657a77fa7284d8ae28dfa48f1dc5d919bf5b2843 (diff)
Merge branch 'dmaengine' into async-tx-next
Conflicts: crypto/async_tx/async_xor.c drivers/dma/ioat/dma_v2.h drivers/dma/ioat/pci.c drivers/md/raid5.c
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/card/block.c28
-rw-r--r--drivers/mmc/card/queue.c11
-rw-r--r--drivers/mmc/core/core.c107
-rw-r--r--drivers/mmc/host/Kconfig66
-rw-r--r--drivers/mmc/host/Makefile7
-rw-r--r--drivers/mmc/host/atmel-mci-regs.h33
-rw-r--r--drivers/mmc/host/atmel-mci.c21
-rw-r--r--drivers/mmc/host/cb710-mmc.c804
-rw-r--r--drivers/mmc/host/cb710-mmc.h104
-rw-r--r--drivers/mmc/host/mmc_spi.c23
-rw-r--r--drivers/mmc/host/mmci.c2
-rw-r--r--drivers/mmc/host/mxcmmc.c2
-rw-r--r--drivers/mmc/host/omap.c3
-rw-r--r--drivers/mmc/host/omap_hsmmc.c6
-rw-r--r--drivers/mmc/host/pxamci.c46
-rw-r--r--drivers/mmc/host/s3cmci.c7
-rw-r--r--drivers/mmc/host/sdhci-of.c3
-rw-r--r--drivers/mmc/host/sdhci-pci.c20
-rw-r--r--drivers/mmc/host/sdhci-pltfm.c168
-rw-r--r--drivers/mmc/host/sdhci-s3c.c428
-rw-r--r--drivers/mmc/host/sdhci.c108
-rw-r--r--drivers/mmc/host/sdhci.h8
-rw-r--r--drivers/mmc/host/tmio_mmc.c180
-rw-r--r--drivers/mmc/host/tmio_mmc.h77
-rw-r--r--drivers/mmc/host/via-sdmmc.c1362
25 files changed, 3391 insertions, 233 deletions
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index b25e9b6516ae..adc205c49fbf 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -147,7 +147,8 @@ struct mmc_blk_request {
147static u32 mmc_sd_num_wr_blocks(struct mmc_card *card) 147static u32 mmc_sd_num_wr_blocks(struct mmc_card *card)
148{ 148{
149 int err; 149 int err;
150 __be32 blocks; 150 u32 result;
151 __be32 *blocks;
151 152
152 struct mmc_request mrq; 153 struct mmc_request mrq;
153 struct mmc_command cmd; 154 struct mmc_command cmd;
@@ -199,14 +200,21 @@ static u32 mmc_sd_num_wr_blocks(struct mmc_card *card)
199 mrq.cmd = &cmd; 200 mrq.cmd = &cmd;
200 mrq.data = &data; 201 mrq.data = &data;
201 202
202 sg_init_one(&sg, &blocks, 4); 203 blocks = kmalloc(4, GFP_KERNEL);
204 if (!blocks)
205 return (u32)-1;
206
207 sg_init_one(&sg, blocks, 4);
203 208
204 mmc_wait_for_req(card->host, &mrq); 209 mmc_wait_for_req(card->host, &mrq);
205 210
211 result = ntohl(*blocks);
212 kfree(blocks);
213
206 if (cmd.error || data.error) 214 if (cmd.error || data.error)
207 return (u32)-1; 215 result = (u32)-1;
208 216
209 return ntohl(blocks); 217 return result;
210} 218}
211 219
212static u32 get_card_status(struct mmc_card *card, struct request *req) 220static u32 get_card_status(struct mmc_card *card, struct request *req)
@@ -243,7 +251,7 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
243 brq.mrq.cmd = &brq.cmd; 251 brq.mrq.cmd = &brq.cmd;
244 brq.mrq.data = &brq.data; 252 brq.mrq.data = &brq.data;
245 253
246 brq.cmd.arg = req->sector; 254 brq.cmd.arg = blk_rq_pos(req);
247 if (!mmc_card_blockaddr(card)) 255 if (!mmc_card_blockaddr(card))
248 brq.cmd.arg <<= 9; 256 brq.cmd.arg <<= 9;
249 brq.cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; 257 brq.cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC;
@@ -251,7 +259,7 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
251 brq.stop.opcode = MMC_STOP_TRANSMISSION; 259 brq.stop.opcode = MMC_STOP_TRANSMISSION;
252 brq.stop.arg = 0; 260 brq.stop.arg = 0;
253 brq.stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC; 261 brq.stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
254 brq.data.blocks = req->nr_sectors; 262 brq.data.blocks = blk_rq_sectors(req);
255 263
256 /* 264 /*
257 * The block layer doesn't support all sector count 265 * The block layer doesn't support all sector count
@@ -301,7 +309,7 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
301 * Adjust the sg list so it is the same size as the 309 * Adjust the sg list so it is the same size as the
302 * request. 310 * request.
303 */ 311 */
304 if (brq.data.blocks != req->nr_sectors) { 312 if (brq.data.blocks != blk_rq_sectors(req)) {
305 int i, data_size = brq.data.blocks << 9; 313 int i, data_size = brq.data.blocks << 9;
306 struct scatterlist *sg; 314 struct scatterlist *sg;
307 315
@@ -352,8 +360,8 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
352 printk(KERN_ERR "%s: error %d transferring data," 360 printk(KERN_ERR "%s: error %d transferring data,"
353 " sector %u, nr %u, card status %#x\n", 361 " sector %u, nr %u, card status %#x\n",
354 req->rq_disk->disk_name, brq.data.error, 362 req->rq_disk->disk_name, brq.data.error,
355 (unsigned)req->sector, 363 (unsigned)blk_rq_pos(req),
356 (unsigned)req->nr_sectors, status); 364 (unsigned)blk_rq_sectors(req), status);
357 } 365 }
358 366
359 if (brq.stop.error) { 367 if (brq.stop.error) {
@@ -521,7 +529,7 @@ static struct mmc_blk_data *mmc_blk_alloc(struct mmc_card *card)
521 529
522 sprintf(md->disk->disk_name, "mmcblk%d", devidx); 530 sprintf(md->disk->disk_name, "mmcblk%d", devidx);
523 531
524 blk_queue_hardsect_size(md->queue.queue, 512); 532 blk_queue_logical_block_size(md->queue.queue, 512);
525 533
526 if (!mmc_card_sd(card) && mmc_card_blockaddr(card)) { 534 if (!mmc_card_sd(card) && mmc_card_blockaddr(card)) {
527 /* 535 /*
diff --git a/drivers/mmc/card/queue.c b/drivers/mmc/card/queue.c
index 7a72e75d5c67..49e582356c65 100644
--- a/drivers/mmc/card/queue.c
+++ b/drivers/mmc/card/queue.c
@@ -55,7 +55,7 @@ static int mmc_queue_thread(void *d)
55 spin_lock_irq(q->queue_lock); 55 spin_lock_irq(q->queue_lock);
56 set_current_state(TASK_INTERRUPTIBLE); 56 set_current_state(TASK_INTERRUPTIBLE);
57 if (!blk_queue_plugged(q)) 57 if (!blk_queue_plugged(q))
58 req = elv_next_request(q); 58 req = blk_fetch_request(q);
59 mq->req = req; 59 mq->req = req;
60 spin_unlock_irq(q->queue_lock); 60 spin_unlock_irq(q->queue_lock);
61 61
@@ -88,16 +88,11 @@ static void mmc_request(struct request_queue *q)
88{ 88{
89 struct mmc_queue *mq = q->queuedata; 89 struct mmc_queue *mq = q->queuedata;
90 struct request *req; 90 struct request *req;
91 int ret;
92 91
93 if (!mq) { 92 if (!mq) {
94 printk(KERN_ERR "MMC: killing requests for dead queue\n"); 93 printk(KERN_ERR "MMC: killing requests for dead queue\n");
95 while ((req = elv_next_request(q)) != NULL) { 94 while ((req = blk_fetch_request(q)) != NULL)
96 do { 95 __blk_end_request_all(req, -EIO);
97 ret = __blk_end_request(req, -EIO,
98 blk_rq_cur_bytes(req));
99 } while (ret);
100 }
101 return; 96 return;
102 } 97 }
103 98
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 264911732756..d84c880fac84 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -708,7 +708,13 @@ static void mmc_power_up(struct mmc_host *host)
708 */ 708 */
709 mmc_delay(10); 709 mmc_delay(10);
710 710
711 host->ios.clock = host->f_min; 711 if (host->f_min > 400000) {
712 pr_warning("%s: Minimum clock frequency too high for "
713 "identification mode\n", mmc_hostname(host));
714 host->ios.clock = host->f_min;
715 } else
716 host->ios.clock = 400000;
717
712 host->ios.power_mode = MMC_POWER_ON; 718 host->ios.power_mode = MMC_POWER_ON;
713 mmc_set_ios(host); 719 mmc_set_ios(host);
714 720
@@ -855,61 +861,72 @@ void mmc_rescan(struct work_struct *work)
855 861
856 mmc_bus_get(host); 862 mmc_bus_get(host);
857 863
858 if (host->bus_ops == NULL) { 864 /* if there is a card registered, check whether it is still present */
859 /* 865 if ((host->bus_ops != NULL) && host->bus_ops->detect && !host->bus_dead)
860 * Only we can add a new handler, so it's safe to 866 host->bus_ops->detect(host);
861 * release the lock here. 867
862 */ 868 mmc_bus_put(host);
869
870
871 mmc_bus_get(host);
872
873 /* if there still is a card present, stop here */
874 if (host->bus_ops != NULL) {
863 mmc_bus_put(host); 875 mmc_bus_put(host);
876 goto out;
877 }
864 878
865 if (host->ops->get_cd && host->ops->get_cd(host) == 0) 879 /* detect a newly inserted card */
866 goto out;
867 880
868 mmc_claim_host(host); 881 /*
882 * Only we can add a new handler, so it's safe to
883 * release the lock here.
884 */
885 mmc_bus_put(host);
869 886
870 mmc_power_up(host); 887 if (host->ops->get_cd && host->ops->get_cd(host) == 0)
871 mmc_go_idle(host); 888 goto out;
872 889
873 mmc_send_if_cond(host, host->ocr_avail); 890 mmc_claim_host(host);
874 891
875 /* 892 mmc_power_up(host);
876 * First we search for SDIO... 893 mmc_go_idle(host);
877 */
878 err = mmc_send_io_op_cond(host, 0, &ocr);
879 if (!err) {
880 if (mmc_attach_sdio(host, ocr))
881 mmc_power_off(host);
882 goto out;
883 }
884 894
885 /* 895 mmc_send_if_cond(host, host->ocr_avail);
886 * ...then normal SD...
887 */
888 err = mmc_send_app_op_cond(host, 0, &ocr);
889 if (!err) {
890 if (mmc_attach_sd(host, ocr))
891 mmc_power_off(host);
892 goto out;
893 }
894 896
895 /* 897 /*
896 * ...and finally MMC. 898 * First we search for SDIO...
897 */ 899 */
898 err = mmc_send_op_cond(host, 0, &ocr); 900 err = mmc_send_io_op_cond(host, 0, &ocr);
899 if (!err) { 901 if (!err) {
900 if (mmc_attach_mmc(host, ocr)) 902 if (mmc_attach_sdio(host, ocr))
901 mmc_power_off(host); 903 mmc_power_off(host);
902 goto out; 904 goto out;
903 } 905 }
904 906
905 mmc_release_host(host); 907 /*
906 mmc_power_off(host); 908 * ...then normal SD...
907 } else { 909 */
908 if (host->bus_ops->detect && !host->bus_dead) 910 err = mmc_send_app_op_cond(host, 0, &ocr);
909 host->bus_ops->detect(host); 911 if (!err) {
912 if (mmc_attach_sd(host, ocr))
913 mmc_power_off(host);
914 goto out;
915 }
910 916
911 mmc_bus_put(host); 917 /*
918 * ...and finally MMC.
919 */
920 err = mmc_send_op_cond(host, 0, &ocr);
921 if (!err) {
922 if (mmc_attach_mmc(host, ocr))
923 mmc_power_off(host);
924 goto out;
912 } 925 }
926
927 mmc_release_host(host);
928 mmc_power_off(host);
929
913out: 930out:
914 if (host->caps & MMC_CAP_NEEDS_POLL) 931 if (host->caps & MMC_CAP_NEEDS_POLL)
915 mmc_schedule_delayed_work(&host->detect, HZ); 932 mmc_schedule_delayed_work(&host->detect, HZ);
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index b4cf691f3f64..891ef18bd77b 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -83,6 +83,42 @@ config MMC_SDHCI_OF
83 83
84 If unsure, say N. 84 If unsure, say N.
85 85
86config MMC_SDHCI_PLTFM
87 tristate "SDHCI support on the platform specific bus"
88 depends on MMC_SDHCI
89 help
90 This selects the platform specific bus support for Secure Digital Host
91 Controller Interface.
92
93 If you have a controller with this interface, say Y or M here.
94
95 If unsure, say N.
96
97config MMC_SDHCI_S3C
98 tristate "SDHCI support on Samsung S3C SoC"
99 depends on MMC_SDHCI && (PLAT_S3C24XX || PLAT_S3C64XX)
100 help
101 This selects the Secure Digital Host Controller Interface (SDHCI)
102 often referrered to as the HSMMC block in some of the Samsung S3C
103 range of SoC.
104
105 Note, due to the problems with DMA, the DMA support is only
106 available with CONFIG_EXPERIMENTAL is selected.
107
108 If you have a controller with this interface, say Y or M here.
109
110 If unsure, say N.
111
112config MMC_SDHCI_S3C_DMA
113 bool "DMA support on S3C SDHCI"
114 depends on MMC_SDHCI_S3C && EXPERIMENTAL
115 help
116 Enable DMA support on the Samsung S3C SDHCI glue. The DMA
117 has proved to be problematic if the controller encounters
118 certain errors, and thus should be treated with care.
119
120 YMMV.
121
86config MMC_OMAP 122config MMC_OMAP
87 tristate "TI OMAP Multimedia Card Interface support" 123 tristate "TI OMAP Multimedia Card Interface support"
88 depends on ARCH_OMAP 124 depends on ARCH_OMAP
@@ -155,7 +191,7 @@ config MMC_ATMELMCI_DMA
155 191
156config MMC_IMX 192config MMC_IMX
157 tristate "Motorola i.MX Multimedia Card Interface support" 193 tristate "Motorola i.MX Multimedia Card Interface support"
158 depends on ARCH_IMX 194 depends on ARCH_MX1
159 help 195 help
160 This selects the Motorola i.MX Multimedia card Interface. 196 This selects the Motorola i.MX Multimedia card Interface.
161 If you have a i.MX platform with a Multimedia Card slot, 197 If you have a i.MX platform with a Multimedia Card slot,
@@ -237,7 +273,31 @@ config MMC_SDRICOH_CS
237 273
238config MMC_TMIO 274config MMC_TMIO
239 tristate "Toshiba Mobile IO Controller (TMIO) MMC/SD function support" 275 tristate "Toshiba Mobile IO Controller (TMIO) MMC/SD function support"
240 depends on MFD_TMIO 276 depends on MFD_TMIO || MFD_ASIC3
241 help 277 help
242 This provides support for the SD/MMC cell found in TC6393XB, 278 This provides support for the SD/MMC cell found in TC6393XB,
243 T7L66XB and also ipaq ASIC3 279 T7L66XB and also HTC ASIC3
280
281config MMC_CB710
282 tristate "ENE CB710 MMC/SD Interface support"
283 depends on PCI
284 select CB710_CORE
285 help
286 This option enables support for MMC/SD part of ENE CB710/720 Flash
287 memory card reader found in some laptops (ie. some versions of
288 HP Compaq nx9500).
289
290 This driver can also be built as a module. If so, the module
291 will be called cb710-mmc.
292
293config MMC_VIA_SDMMC
294 tristate "VIA SD/MMC Card Reader Driver"
295 depends on PCI
296 help
297 This selects the VIA SD/MMC Card Reader driver, say Y or M here.
298 VIA provides one multi-functional card reader which integrated into
299 some motherboards manufactured by VIA. This card reader supports
300 SD/MMC/SDHC.
301 If you have a controller with this interface, say Y or M here.
302
303 If unsure, say N.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 970a997620e1..cf153f628457 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -14,6 +14,8 @@ obj-$(CONFIG_MMC_SDHCI) += sdhci.o
14obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o 14obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
15obj-$(CONFIG_MMC_RICOH_MMC) += ricoh_mmc.o 15obj-$(CONFIG_MMC_RICOH_MMC) += ricoh_mmc.o
16obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o 16obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o
17obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
18obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
17obj-$(CONFIG_MMC_WBSD) += wbsd.o 19obj-$(CONFIG_MMC_WBSD) += wbsd.o
18obj-$(CONFIG_MMC_AU1X) += au1xmmc.o 20obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
19obj-$(CONFIG_MMC_OMAP) += omap.o 21obj-$(CONFIG_MMC_OMAP) += omap.o
@@ -29,4 +31,9 @@ endif
29obj-$(CONFIG_MMC_S3C) += s3cmci.o 31obj-$(CONFIG_MMC_S3C) += s3cmci.o
30obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o 32obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o
31obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o 33obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o
34obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
35obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o
32 36
37ifeq ($(CONFIG_CB710_DEBUG),y)
38 CFLAGS-cb710-mmc += -DDEBUG
39endif
diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
index b58364ed6bba..fc8a0fe7c5c5 100644
--- a/drivers/mmc/host/atmel-mci-regs.h
+++ b/drivers/mmc/host/atmel-mci-regs.h
@@ -7,6 +7,12 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10
11/*
12 * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
13 * Registers and bitfields marked with [2] are only available in MCI2
14 */
15
10#ifndef __DRIVERS_MMC_ATMEL_MCI_H__ 16#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
11#define __DRIVERS_MMC_ATMEL_MCI_H__ 17#define __DRIVERS_MMC_ATMEL_MCI_H__
12 18
@@ -14,11 +20,17 @@
14#define MCI_CR 0x0000 /* Control */ 20#define MCI_CR 0x0000 /* Control */
15# define MCI_CR_MCIEN ( 1 << 0) /* MCI Enable */ 21# define MCI_CR_MCIEN ( 1 << 0) /* MCI Enable */
16# define MCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */ 22# define MCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */
23# define MCI_CR_PWSEN ( 1 << 2) /* Power Save Enable */
24# define MCI_CR_PWSDIS ( 1 << 3) /* Power Save Disable */
17# define MCI_CR_SWRST ( 1 << 7) /* Software Reset */ 25# define MCI_CR_SWRST ( 1 << 7) /* Software Reset */
18#define MCI_MR 0x0004 /* Mode */ 26#define MCI_MR 0x0004 /* Mode */
19# define MCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */ 27# define MCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
28# define MCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
20# define MCI_MR_RDPROOF ( 1 << 11) /* Read Proof */ 29# define MCI_MR_RDPROOF ( 1 << 11) /* Read Proof */
21# define MCI_MR_WRPROOF ( 1 << 12) /* Write Proof */ 30# define MCI_MR_WRPROOF ( 1 << 12) /* Write Proof */
31# define MCI_MR_PDCFBYTE ( 1 << 13) /* Force Byte Transfer */
32# define MCI_MR_PDCPADV ( 1 << 14) /* Padding Value */
33# define MCI_MR_PDCMODE ( 1 << 15) /* PDC-oriented Mode */
22#define MCI_DTOR 0x0008 /* Data Timeout */ 34#define MCI_DTOR 0x0008 /* Data Timeout */
23# define MCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */ 35# define MCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
24# define MCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */ 36# define MCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
@@ -28,6 +40,7 @@
28# define MCI_SDCSEL_MASK ( 3 << 0) 40# define MCI_SDCSEL_MASK ( 3 << 0)
29# define MCI_SDCBUS_1BIT ( 0 << 6) /* 1-bit data bus */ 41# define MCI_SDCBUS_1BIT ( 0 << 6) /* 1-bit data bus */
30# define MCI_SDCBUS_4BIT ( 2 << 6) /* 4-bit data bus */ 42# define MCI_SDCBUS_4BIT ( 2 << 6) /* 4-bit data bus */
43# define MCI_SDCBUS_8BIT ( 3 << 6) /* 8-bit data bus[2] */
31# define MCI_SDCBUS_MASK ( 3 << 6) 44# define MCI_SDCBUS_MASK ( 3 << 6)
32#define MCI_ARGR 0x0010 /* Command Argument */ 45#define MCI_ARGR 0x0010 /* Command Argument */
33#define MCI_CMDR 0x0014 /* Command */ 46#define MCI_CMDR 0x0014 /* Command */
@@ -56,6 +69,9 @@
56#define MCI_BLKR 0x0018 /* Block */ 69#define MCI_BLKR 0x0018 /* Block */
57# define MCI_BCNT(x) ((x) << 0) /* Data Block Count */ 70# define MCI_BCNT(x) ((x) << 0) /* Data Block Count */
58# define MCI_BLKLEN(x) ((x) << 16) /* Data Block Length */ 71# define MCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
72#define MCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
73# define MCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
74# define MCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
59#define MCI_RSPR 0x0020 /* Response 0 */ 75#define MCI_RSPR 0x0020 /* Response 0 */
60#define MCI_RSPR1 0x0024 /* Response 1 */ 76#define MCI_RSPR1 0x0024 /* Response 1 */
61#define MCI_RSPR2 0x0028 /* Response 2 */ 77#define MCI_RSPR2 0x0028 /* Response 2 */
@@ -83,7 +99,24 @@
83# define MCI_DTOE ( 1 << 22) /* Data Time-Out Error */ 99# define MCI_DTOE ( 1 << 22) /* Data Time-Out Error */
84# define MCI_OVRE ( 1 << 30) /* RX Overrun Error */ 100# define MCI_OVRE ( 1 << 30) /* RX Overrun Error */
85# define MCI_UNRE ( 1 << 31) /* TX Underrun Error */ 101# define MCI_UNRE ( 1 << 31) /* TX Underrun Error */
102#define MCI_DMA 0x0050 /* DMA Configuration[2] */
103# define MCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
104# define MCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
105# define MCI_DMAEN ( 1 << 8) /* DMA Hardware Handshaking Enable */
106#define MCI_CFG 0x0054 /* Configuration[2] */
107# define MCI_CFG_FIFOMODE_1DATA ( 1 << 0) /* MCI Internal FIFO control mode */
108# define MCI_CFG_FERRCTRL_COR ( 1 << 4) /* Flow Error flag reset control mode */
109# define MCI_CFG_HSMODE ( 1 << 8) /* High Speed Mode */
110# define MCI_CFG_LSYNC ( 1 << 12) /* Synchronize on the last block */
111#define MCI_WPMR 0x00e4 /* Write Protection Mode[2] */
112# define MCI_WP_EN ( 1 << 0) /* WP Enable */
113# define MCI_WP_KEY (0x4d4349 << 8) /* WP Key */
114#define MCI_WPSR 0x00e8 /* Write Protection Status[2] */
115# define MCI_GET_WP_VS(x) ((x) & 0x0f)
116# define MCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
117#define MCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
86 118
119/* This is not including the FIFO Aperture on MCI2 */
87#define MCI_REGS_SIZE 0x100 120#define MCI_REGS_SIZE 0x100
88 121
89/* Register access macros */ 122/* Register access macros */
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index cf6a100bb38f..5e10d3663ab5 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -177,6 +177,7 @@ struct atmel_mci {
177 * available. 177 * available.
178 * @wp_pin: GPIO pin used for card write protect sending, or negative 178 * @wp_pin: GPIO pin used for card write protect sending, or negative
179 * if not available. 179 * if not available.
180 * @detect_is_active_high: The state of the detect pin when it is active.
180 * @detect_timer: Timer used for debouncing @detect_pin interrupts. 181 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
181 */ 182 */
182struct atmel_mci_slot { 183struct atmel_mci_slot {
@@ -196,6 +197,7 @@ struct atmel_mci_slot {
196 197
197 int detect_pin; 198 int detect_pin;
198 int wp_pin; 199 int wp_pin;
200 bool detect_is_active_high;
199 201
200 struct timer_list detect_timer; 202 struct timer_list detect_timer;
201}; 203};
@@ -574,6 +576,7 @@ atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
574 struct scatterlist *sg; 576 struct scatterlist *sg;
575 unsigned int i; 577 unsigned int i;
576 enum dma_data_direction direction; 578 enum dma_data_direction direction;
579 unsigned int sglen;
577 580
578 /* 581 /*
579 * We don't do DMA on "complex" transfers, i.e. with 582 * We don't do DMA on "complex" transfers, i.e. with
@@ -603,11 +606,14 @@ atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
603 else 606 else
604 direction = DMA_TO_DEVICE; 607 direction = DMA_TO_DEVICE;
605 608
609 sglen = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, direction);
610 if (sglen != data->sg_len)
611 goto unmap_exit;
606 desc = chan->device->device_prep_slave_sg(chan, 612 desc = chan->device->device_prep_slave_sg(chan,
607 data->sg, data->sg_len, direction, 613 data->sg, data->sg_len, direction,
608 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 614 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
609 if (!desc) 615 if (!desc)
610 return -ENOMEM; 616 goto unmap_exit;
611 617
612 host->dma.data_desc = desc; 618 host->dma.data_desc = desc;
613 desc->callback = atmci_dma_complete; 619 desc->callback = atmci_dma_complete;
@@ -618,6 +624,9 @@ atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
618 chan->device->device_issue_pending(chan); 624 chan->device->device_issue_pending(chan);
619 625
620 return 0; 626 return 0;
627unmap_exit:
628 dma_unmap_sg(&host->pdev->dev, data->sg, sglen, direction);
629 return -ENOMEM;
621} 630}
622 631
623#else /* CONFIG_MMC_ATMELMCI_DMA */ 632#else /* CONFIG_MMC_ATMELMCI_DMA */
@@ -924,7 +933,8 @@ static int atmci_get_cd(struct mmc_host *mmc)
924 struct atmel_mci_slot *slot = mmc_priv(mmc); 933 struct atmel_mci_slot *slot = mmc_priv(mmc);
925 934
926 if (gpio_is_valid(slot->detect_pin)) { 935 if (gpio_is_valid(slot->detect_pin)) {
927 present = !gpio_get_value(slot->detect_pin); 936 present = !(gpio_get_value(slot->detect_pin) ^
937 slot->detect_is_active_high);
928 dev_dbg(&mmc->class_dev, "card is %spresent\n", 938 dev_dbg(&mmc->class_dev, "card is %spresent\n",
929 present ? "" : "not "); 939 present ? "" : "not ");
930 } 940 }
@@ -1028,7 +1038,8 @@ static void atmci_detect_change(unsigned long data)
1028 return; 1038 return;
1029 1039
1030 enable_irq(gpio_to_irq(slot->detect_pin)); 1040 enable_irq(gpio_to_irq(slot->detect_pin));
1031 present = !gpio_get_value(slot->detect_pin); 1041 present = !(gpio_get_value(slot->detect_pin) ^
1042 slot->detect_is_active_high);
1032 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); 1043 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1033 1044
1034 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", 1045 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
@@ -1456,6 +1467,7 @@ static int __init atmci_init_slot(struct atmel_mci *host,
1456 slot->host = host; 1467 slot->host = host;
1457 slot->detect_pin = slot_data->detect_pin; 1468 slot->detect_pin = slot_data->detect_pin;
1458 slot->wp_pin = slot_data->wp_pin; 1469 slot->wp_pin = slot_data->wp_pin;
1470 slot->detect_is_active_high = slot_data->detect_is_active_high;
1459 slot->sdc_reg = sdc_reg; 1471 slot->sdc_reg = sdc_reg;
1460 1472
1461 mmc->ops = &atmci_ops; 1473 mmc->ops = &atmci_ops;
@@ -1477,7 +1489,8 @@ static int __init atmci_init_slot(struct atmel_mci *host,
1477 if (gpio_request(slot->detect_pin, "mmc_detect")) { 1489 if (gpio_request(slot->detect_pin, "mmc_detect")) {
1478 dev_dbg(&mmc->class_dev, "no detect pin available\n"); 1490 dev_dbg(&mmc->class_dev, "no detect pin available\n");
1479 slot->detect_pin = -EBUSY; 1491 slot->detect_pin = -EBUSY;
1480 } else if (gpio_get_value(slot->detect_pin)) { 1492 } else if (gpio_get_value(slot->detect_pin) ^
1493 slot->detect_is_active_high) {
1481 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 1494 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1482 } 1495 }
1483 } 1496 }
diff --git a/drivers/mmc/host/cb710-mmc.c b/drivers/mmc/host/cb710-mmc.c
new file mode 100644
index 000000000000..11efefb1af51
--- /dev/null
+++ b/drivers/mmc/host/cb710-mmc.c
@@ -0,0 +1,804 @@
1/*
2 * cb710/mmc.c
3 *
4 * Copyright by Michał Mirosław, 2008-2009
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/slab.h>
13#include <linux/pci.h>
14#include <linux/delay.h>
15#include "cb710-mmc.h"
16
17static const u8 cb710_clock_divider_log2[8] = {
18/* 1, 2, 4, 8, 16, 32, 128, 512 */
19 0, 1, 2, 3, 4, 5, 7, 9
20};
21#define CB710_MAX_DIVIDER_IDX \
22 (ARRAY_SIZE(cb710_clock_divider_log2) - 1)
23
24static const u8 cb710_src_freq_mhz[16] = {
25 33, 10, 20, 25, 30, 35, 40, 45,
26 50, 55, 60, 65, 70, 75, 80, 85
27};
28
29static void cb710_mmc_set_clock(struct mmc_host *mmc, int hz)
30{
31 struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
32 struct pci_dev *pdev = cb710_slot_to_chip(slot)->pdev;
33 u32 src_freq_idx;
34 u32 divider_idx;
35 int src_hz;
36
37 /* this is magic, unverifiable for me, unless I get
38 * MMC card with cables connected to bus signals */
39 pci_read_config_dword(pdev, 0x48, &src_freq_idx);
40 src_freq_idx = (src_freq_idx >> 16) & 0xF;
41 src_hz = cb710_src_freq_mhz[src_freq_idx] * 1000000;
42
43 for (divider_idx = 0; divider_idx < CB710_MAX_DIVIDER_IDX; ++divider_idx) {
44 if (hz >= src_hz >> cb710_clock_divider_log2[divider_idx])
45 break;
46 }
47
48 if (src_freq_idx)
49 divider_idx |= 0x8;
50
51 cb710_pci_update_config_reg(pdev, 0x40, ~0xF0000000, divider_idx << 28);
52
53 dev_dbg(cb710_slot_dev(slot),
54 "clock set to %d Hz, wanted %d Hz; flag = %d\n",
55 src_hz >> cb710_clock_divider_log2[divider_idx & 7],
56 hz, (divider_idx & 8) != 0);
57}
58
59static void __cb710_mmc_enable_irq(struct cb710_slot *slot,
60 unsigned short enable, unsigned short mask)
61{
62 /* clear global IE
63 * - it gets set later if any interrupt sources are enabled */
64 mask |= CB710_MMC_IE_IRQ_ENABLE;
65
66 /* look like interrupt is fired whenever
67 * WORD[0x0C] & WORD[0x10] != 0;
68 * -> bit 15 port 0x0C seems to be global interrupt enable
69 */
70
71 enable = (cb710_read_port_16(slot, CB710_MMC_IRQ_ENABLE_PORT)
72 & ~mask) | enable;
73
74 if (enable)
75 enable |= CB710_MMC_IE_IRQ_ENABLE;
76
77 cb710_write_port_16(slot, CB710_MMC_IRQ_ENABLE_PORT, enable);
78}
79
80static void cb710_mmc_enable_irq(struct cb710_slot *slot,
81 unsigned short enable, unsigned short mask)
82{
83 struct cb710_mmc_reader *reader = mmc_priv(cb710_slot_to_mmc(slot));
84 unsigned long flags;
85
86 spin_lock_irqsave(&reader->irq_lock, flags);
87 /* this is the only thing irq_lock protects */
88 __cb710_mmc_enable_irq(slot, enable, mask);
89 spin_unlock_irqrestore(&reader->irq_lock, flags);
90}
91
92static void cb710_mmc_reset_events(struct cb710_slot *slot)
93{
94 cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, 0xFF);
95 cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, 0xFF);
96 cb710_write_port_8(slot, CB710_MMC_STATUS2_PORT, 0xFF);
97}
98
99static int cb710_mmc_is_card_inserted(struct cb710_slot *slot)
100{
101 return cb710_read_port_8(slot, CB710_MMC_STATUS3_PORT)
102 & CB710_MMC_S3_CARD_DETECTED;
103}
104
105static void cb710_mmc_enable_4bit_data(struct cb710_slot *slot, int enable)
106{
107 dev_dbg(cb710_slot_dev(slot), "configuring %d-data-line%s mode\n",
108 enable ? 4 : 1, enable ? "s" : "");
109 if (enable)
110 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT,
111 CB710_MMC_C1_4BIT_DATA_BUS, 0);
112 else
113 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT,
114 0, CB710_MMC_C1_4BIT_DATA_BUS);
115}
116
117static int cb710_check_event(struct cb710_slot *slot, u8 what)
118{
119 u16 status;
120
121 status = cb710_read_port_16(slot, CB710_MMC_STATUS_PORT);
122
123 if (status & CB710_MMC_S0_FIFO_UNDERFLOW) {
124 /* it is just a guess, so log it */
125 dev_dbg(cb710_slot_dev(slot),
126 "CHECK : ignoring bit 6 in status %04X\n", status);
127 cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT,
128 CB710_MMC_S0_FIFO_UNDERFLOW);
129 status &= ~CB710_MMC_S0_FIFO_UNDERFLOW;
130 }
131
132 if (status & CB710_MMC_STATUS_ERROR_EVENTS) {
133 dev_dbg(cb710_slot_dev(slot),
134 "CHECK : returning EIO on status %04X\n", status);
135 cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, status & 0xFF);
136 cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT,
137 CB710_MMC_S1_RESET);
138 return -EIO;
139 }
140
141 /* 'what' is a bit in MMC_STATUS1 */
142 if ((status >> 8) & what) {
143 cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, what);
144 return 1;
145 }
146
147 return 0;
148}
149
150static int cb710_wait_for_event(struct cb710_slot *slot, u8 what)
151{
152 int err = 0;
153 unsigned limit = 2000000; /* FIXME: real timeout */
154
155#ifdef CONFIG_CB710_DEBUG
156 u32 e, x;
157 e = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
158#endif
159
160 while (!(err = cb710_check_event(slot, what))) {
161 if (!--limit) {
162 cb710_dump_regs(cb710_slot_to_chip(slot),
163 CB710_DUMP_REGS_MMC);
164 err = -ETIMEDOUT;
165 break;
166 }
167 udelay(1);
168 }
169
170#ifdef CONFIG_CB710_DEBUG
171 x = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
172
173 limit = 2000000 - limit;
174 if (limit > 100)
175 dev_dbg(cb710_slot_dev(slot),
176 "WAIT10: waited %d loops, what %d, entry val %08X, exit val %08X\n",
177 limit, what, e, x);
178#endif
179 return err < 0 ? err : 0;
180}
181
182
183static int cb710_wait_while_busy(struct cb710_slot *slot, uint8_t mask)
184{
185 unsigned limit = 500000; /* FIXME: real timeout */
186 int err = 0;
187
188#ifdef CONFIG_CB710_DEBUG
189 u32 e, x;
190 e = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
191#endif
192
193 while (cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) & mask) {
194 if (!--limit) {
195 cb710_dump_regs(cb710_slot_to_chip(slot),
196 CB710_DUMP_REGS_MMC);
197 err = -ETIMEDOUT;
198 break;
199 }
200 udelay(1);
201 }
202
203#ifdef CONFIG_CB710_DEBUG
204 x = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
205
206 limit = 500000 - limit;
207 if (limit > 100)
208 dev_dbg(cb710_slot_dev(slot),
209 "WAIT12: waited %d loops, mask %02X, entry val %08X, exit val %08X\n",
210 limit, mask, e, x);
211#endif
212 return 0;
213}
214
215static void cb710_mmc_set_transfer_size(struct cb710_slot *slot,
216 size_t count, size_t blocksize)
217{
218 cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
219 cb710_write_port_32(slot, CB710_MMC_TRANSFER_SIZE_PORT,
220 ((count - 1) << 16)|(blocksize - 1));
221
222 dev_vdbg(cb710_slot_dev(slot), "set up for %zu block%s of %zu bytes\n",
223 count, count == 1 ? "" : "s", blocksize);
224}
225
226static void cb710_mmc_fifo_hack(struct cb710_slot *slot)
227{
228 /* without this, received data is prepended with 8-bytes of zeroes */
229 u32 r1, r2;
230 int ok = 0;
231
232 r1 = cb710_read_port_32(slot, CB710_MMC_DATA_PORT);
233 r2 = cb710_read_port_32(slot, CB710_MMC_DATA_PORT);
234 if (cb710_read_port_8(slot, CB710_MMC_STATUS0_PORT)
235 & CB710_MMC_S0_FIFO_UNDERFLOW) {
236 cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT,
237 CB710_MMC_S0_FIFO_UNDERFLOW);
238 ok = 1;
239 }
240
241 dev_dbg(cb710_slot_dev(slot),
242 "FIFO-read-hack: expected STATUS0 bit was %s\n",
243 ok ? "set." : "NOT SET!");
244 dev_dbg(cb710_slot_dev(slot),
245 "FIFO-read-hack: dwords ignored: %08X %08X - %s\n",
246 r1, r2, (r1|r2) ? "BAD (NOT ZERO)!" : "ok");
247}
248
249static int cb710_mmc_receive_pio(struct cb710_slot *slot,
250 struct sg_mapping_iter *miter, size_t dw_count)
251{
252 if (!(cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) & CB710_MMC_S2_FIFO_READY)) {
253 int err = cb710_wait_for_event(slot,
254 CB710_MMC_S1_PIO_TRANSFER_DONE);
255 if (err)
256 return err;
257 }
258
259 cb710_sg_dwiter_write_from_io(miter,
260 slot->iobase + CB710_MMC_DATA_PORT, dw_count);
261
262 return 0;
263}
264
265static bool cb710_is_transfer_size_supported(struct mmc_data *data)
266{
267 return !(data->blksz & 15 && (data->blocks != 1 || data->blksz != 8));
268}
269
270static int cb710_mmc_receive(struct cb710_slot *slot, struct mmc_data *data)
271{
272 struct sg_mapping_iter miter;
273 size_t len, blocks = data->blocks;
274 int err = 0;
275
276 /* TODO: I don't know how/if the hardware handles non-16B-boundary blocks
277 * except single 8B block */
278 if (unlikely(data->blksz & 15 && (data->blocks != 1 || data->blksz != 8)))
279 return -EINVAL;
280
281 sg_miter_start(&miter, data->sg, data->sg_len, 0);
282
283 cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
284 15, CB710_MMC_C2_READ_PIO_SIZE_MASK);
285
286 cb710_mmc_fifo_hack(slot);
287
288 while (blocks-- > 0) {
289 len = data->blksz;
290
291 while (len >= 16) {
292 err = cb710_mmc_receive_pio(slot, &miter, 4);
293 if (err)
294 goto out;
295 len -= 16;
296 }
297
298 if (!len)
299 continue;
300
301 cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
302 len - 1, CB710_MMC_C2_READ_PIO_SIZE_MASK);
303
304 len = (len >= 8) ? 4 : 2;
305 err = cb710_mmc_receive_pio(slot, &miter, len);
306 if (err)
307 goto out;
308 }
309out:
310 cb710_sg_miter_stop_writing(&miter);
311 return err;
312}
313
314static int cb710_mmc_send(struct cb710_slot *slot, struct mmc_data *data)
315{
316 struct sg_mapping_iter miter;
317 size_t len, blocks = data->blocks;
318 int err = 0;
319
320 /* TODO: I don't know how/if the hardware handles multiple
321 * non-16B-boundary blocks */
322 if (unlikely(data->blocks > 1 && data->blksz & 15))
323 return -EINVAL;
324
325 sg_miter_start(&miter, data->sg, data->sg_len, 0);
326
327 cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
328 0, CB710_MMC_C2_READ_PIO_SIZE_MASK);
329
330 while (blocks-- > 0) {
331 len = (data->blksz + 15) >> 4;
332 do {
333 if (!(cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT)
334 & CB710_MMC_S2_FIFO_EMPTY)) {
335 err = cb710_wait_for_event(slot,
336 CB710_MMC_S1_PIO_TRANSFER_DONE);
337 if (err)
338 goto out;
339 }
340 cb710_sg_dwiter_read_to_io(&miter,
341 slot->iobase + CB710_MMC_DATA_PORT, 4);
342 } while (--len);
343 }
344out:
345 sg_miter_stop(&miter);
346 return err;
347}
348
349static u16 cb710_encode_cmd_flags(struct cb710_mmc_reader *reader,
350 struct mmc_command *cmd)
351{
352 unsigned int flags = cmd->flags;
353 u16 cb_flags = 0;
354
355 /* Windows driver returned 0 for commands for which no response
356 * is expected. It happened that there were only two such commands
357 * used: MMC_GO_IDLE_STATE and MMC_GO_INACTIVE_STATE so it might
358 * as well be a bug in that driver.
359 *
360 * Original driver set bit 14 for MMC/SD application
361 * commands. There's no difference 'on the wire' and
362 * it apparently works without it anyway.
363 */
364
365 switch (flags & MMC_CMD_MASK) {
366 case MMC_CMD_AC: cb_flags = CB710_MMC_CMD_AC; break;
367 case MMC_CMD_ADTC: cb_flags = CB710_MMC_CMD_ADTC; break;
368 case MMC_CMD_BC: cb_flags = CB710_MMC_CMD_BC; break;
369 case MMC_CMD_BCR: cb_flags = CB710_MMC_CMD_BCR; break;
370 }
371
372 if (flags & MMC_RSP_BUSY)
373 cb_flags |= CB710_MMC_RSP_BUSY;
374
375 cb_flags |= cmd->opcode << CB710_MMC_CMD_CODE_SHIFT;
376
377 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
378 cb_flags |= CB710_MMC_DATA_READ;
379
380 if (flags & MMC_RSP_PRESENT) {
381 /* Windows driver set 01 at bits 4,3 except for
382 * MMC_SET_BLOCKLEN where it set 10. Maybe the
383 * hardware can do something special about this
384 * command? The original driver looks buggy/incomplete
385 * anyway so we ignore this for now.
386 *
387 * I assume that 00 here means no response is expected.
388 */
389 cb_flags |= CB710_MMC_RSP_PRESENT;
390
391 if (flags & MMC_RSP_136)
392 cb_flags |= CB710_MMC_RSP_136;
393 if (!(flags & MMC_RSP_CRC))
394 cb_flags |= CB710_MMC_RSP_NO_CRC;
395 }
396
397 return cb_flags;
398}
399
400static void cb710_receive_response(struct cb710_slot *slot,
401 struct mmc_command *cmd)
402{
403 unsigned rsp_opcode, wanted_opcode;
404
405 /* Looks like final byte with CRC is always stripped (same as SDHCI) */
406 if (cmd->flags & MMC_RSP_136) {
407 u32 resp[4];
408
409 resp[0] = cb710_read_port_32(slot, CB710_MMC_RESPONSE3_PORT);
410 resp[1] = cb710_read_port_32(slot, CB710_MMC_RESPONSE2_PORT);
411 resp[2] = cb710_read_port_32(slot, CB710_MMC_RESPONSE1_PORT);
412 resp[3] = cb710_read_port_32(slot, CB710_MMC_RESPONSE0_PORT);
413 rsp_opcode = resp[0] >> 24;
414
415 cmd->resp[0] = (resp[0] << 8)|(resp[1] >> 24);
416 cmd->resp[1] = (resp[1] << 8)|(resp[2] >> 24);
417 cmd->resp[2] = (resp[2] << 8)|(resp[3] >> 24);
418 cmd->resp[3] = (resp[3] << 8);
419 } else {
420 rsp_opcode = cb710_read_port_32(slot, CB710_MMC_RESPONSE1_PORT) & 0x3F;
421 cmd->resp[0] = cb710_read_port_32(slot, CB710_MMC_RESPONSE0_PORT);
422 }
423
424 wanted_opcode = (cmd->flags & MMC_RSP_OPCODE) ? cmd->opcode : 0x3F;
425 if (rsp_opcode != wanted_opcode)
426 cmd->error = -EILSEQ;
427}
428
429static int cb710_mmc_transfer_data(struct cb710_slot *slot,
430 struct mmc_data *data)
431{
432 int error, to;
433
434 if (data->flags & MMC_DATA_READ)
435 error = cb710_mmc_receive(slot, data);
436 else
437 error = cb710_mmc_send(slot, data);
438
439 to = cb710_wait_for_event(slot, CB710_MMC_S1_DATA_TRANSFER_DONE);
440 if (!error)
441 error = to;
442
443 if (!error)
444 data->bytes_xfered = data->blksz * data->blocks;
445 return error;
446}
447
448static int cb710_mmc_command(struct mmc_host *mmc, struct mmc_command *cmd)
449{
450 struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
451 struct cb710_mmc_reader *reader = mmc_priv(mmc);
452 struct mmc_data *data = cmd->data;
453
454 u16 cb_cmd = cb710_encode_cmd_flags(reader, cmd);
455 dev_dbg(cb710_slot_dev(slot), "cmd request: 0x%04X\n", cb_cmd);
456
457 if (data) {
458 if (!cb710_is_transfer_size_supported(data)) {
459 data->error = -EINVAL;
460 return -1;
461 }
462 cb710_mmc_set_transfer_size(slot, data->blocks, data->blksz);
463 }
464
465 cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20|CB710_MMC_S2_BUSY_10);
466 cb710_write_port_16(slot, CB710_MMC_CMD_TYPE_PORT, cb_cmd);
467 cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
468 cb710_write_port_32(slot, CB710_MMC_CMD_PARAM_PORT, cmd->arg);
469 cb710_mmc_reset_events(slot);
470 cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
471 cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x01, 0);
472
473 cmd->error = cb710_wait_for_event(slot, CB710_MMC_S1_COMMAND_SENT);
474 if (cmd->error)
475 return -1;
476
477 if (cmd->flags & MMC_RSP_PRESENT) {
478 cb710_receive_response(slot, cmd);
479 if (cmd->error)
480 return -1;
481 }
482
483 if (data)
484 data->error = cb710_mmc_transfer_data(slot, data);
485 return 0;
486}
487
488static void cb710_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
489{
490 struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
491 struct cb710_mmc_reader *reader = mmc_priv(mmc);
492
493 WARN_ON(reader->mrq != NULL);
494
495 reader->mrq = mrq;
496 cb710_mmc_enable_irq(slot, CB710_MMC_IE_TEST_MASK, 0);
497
498 if (cb710_mmc_is_card_inserted(slot)) {
499 if (!cb710_mmc_command(mmc, mrq->cmd) && mrq->stop)
500 cb710_mmc_command(mmc, mrq->stop);
501 mdelay(1);
502 } else {
503 mrq->cmd->error = -ENOMEDIUM;
504 }
505
506 tasklet_schedule(&reader->finish_req_tasklet);
507}
508
509static int cb710_mmc_powerup(struct cb710_slot *slot)
510{
511#ifdef CONFIG_CB710_DEBUG
512 struct cb710_chip *chip = cb710_slot_to_chip(slot);
513#endif
514 int err;
515
516 /* a lot of magic; see comment in cb710_mmc_set_clock() */
517 dev_dbg(cb710_slot_dev(slot), "bus powerup\n");
518 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
519 err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
520 if (unlikely(err))
521 return err;
522 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x80, 0);
523 cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0x80, 0);
524 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
525 mdelay(1);
526 dev_dbg(cb710_slot_dev(slot), "after delay 1\n");
527 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
528 err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
529 if (unlikely(err))
530 return err;
531 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x09, 0);
532 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
533 mdelay(1);
534 dev_dbg(cb710_slot_dev(slot), "after delay 2\n");
535 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
536 err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
537 if (unlikely(err))
538 return err;
539 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0, 0x08);
540 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
541 mdelay(2);
542 dev_dbg(cb710_slot_dev(slot), "after delay 3\n");
543 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
544 cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x06, 0);
545 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x70, 0);
546 cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT, 0x80, 0);
547 cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0x03, 0);
548 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
549 err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
550 if (unlikely(err))
551 return err;
552 /* This port behaves weird: quick byte reads of 0x08,0x09 return
553 * 0xFF,0x00 after writing 0xFFFF to 0x08; it works correctly when
554 * read/written from userspace... What am I missing here?
555 * (it doesn't depend on write-to-read delay) */
556 cb710_write_port_16(slot, CB710_MMC_CONFIGB_PORT, 0xFFFF);
557 cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x06, 0);
558 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
559 dev_dbg(cb710_slot_dev(slot), "bus powerup finished\n");
560
561 return cb710_check_event(slot, 0);
562}
563
564static void cb710_mmc_powerdown(struct cb710_slot *slot)
565{
566 cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0, 0x81);
567 cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0, 0x80);
568}
569
570static void cb710_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
571{
572 struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
573 struct cb710_mmc_reader *reader = mmc_priv(mmc);
574 int err;
575
576 cb710_mmc_set_clock(mmc, ios->clock);
577
578 if (!cb710_mmc_is_card_inserted(slot)) {
579 dev_dbg(cb710_slot_dev(slot),
580 "no card inserted - ignoring bus powerup request\n");
581 ios->power_mode = MMC_POWER_OFF;
582 }
583
584 if (ios->power_mode != reader->last_power_mode)
585 switch (ios->power_mode) {
586 case MMC_POWER_ON:
587 err = cb710_mmc_powerup(slot);
588 if (err) {
589 dev_warn(cb710_slot_dev(slot),
590 "powerup failed (%d)- retrying\n", err);
591 cb710_mmc_powerdown(slot);
592 udelay(1);
593 err = cb710_mmc_powerup(slot);
594 if (err)
595 dev_warn(cb710_slot_dev(slot),
596 "powerup retry failed (%d) - expect errors\n",
597 err);
598 }
599 reader->last_power_mode = MMC_POWER_ON;
600 break;
601 case MMC_POWER_OFF:
602 cb710_mmc_powerdown(slot);
603 reader->last_power_mode = MMC_POWER_OFF;
604 break;
605 case MMC_POWER_UP:
606 default:
607 /* ignore */;
608 }
609
610 cb710_mmc_enable_4bit_data(slot, ios->bus_width != MMC_BUS_WIDTH_1);
611
612 cb710_mmc_enable_irq(slot, CB710_MMC_IE_TEST_MASK, 0);
613}
614
615static int cb710_mmc_get_ro(struct mmc_host *mmc)
616{
617 struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
618
619 return cb710_read_port_8(slot, CB710_MMC_STATUS3_PORT)
620 & CB710_MMC_S3_WRITE_PROTECTED;
621}
622
623static int cb710_mmc_irq_handler(struct cb710_slot *slot)
624{
625 struct mmc_host *mmc = cb710_slot_to_mmc(slot);
626 struct cb710_mmc_reader *reader = mmc_priv(mmc);
627 u32 status, config1, config2, irqen;
628
629 status = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
630 irqen = cb710_read_port_32(slot, CB710_MMC_IRQ_ENABLE_PORT);
631 config2 = cb710_read_port_32(slot, CB710_MMC_CONFIGB_PORT);
632 config1 = cb710_read_port_32(slot, CB710_MMC_CONFIG_PORT);
633
634 dev_dbg(cb710_slot_dev(slot), "interrupt; status: %08X, "
635 "ie: %08X, c2: %08X, c1: %08X\n",
636 status, irqen, config2, config1);
637
638 if (status & (CB710_MMC_S1_CARD_CHANGED << 8)) {
639 /* ack the event */
640 cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT,
641 CB710_MMC_S1_CARD_CHANGED);
642 if ((irqen & CB710_MMC_IE_CISTATUS_MASK)
643 == CB710_MMC_IE_CISTATUS_MASK)
644 mmc_detect_change(mmc, HZ/5);
645 } else {
646 dev_dbg(cb710_slot_dev(slot), "unknown interrupt (test)\n");
647 spin_lock(&reader->irq_lock);
648 __cb710_mmc_enable_irq(slot, 0, CB710_MMC_IE_TEST_MASK);
649 spin_unlock(&reader->irq_lock);
650 }
651
652 return 1;
653}
654
655static void cb710_mmc_finish_request_tasklet(unsigned long data)
656{
657 struct mmc_host *mmc = (void *)data;
658 struct cb710_mmc_reader *reader = mmc_priv(mmc);
659 struct mmc_request *mrq = reader->mrq;
660
661 reader->mrq = NULL;
662 mmc_request_done(mmc, mrq);
663}
664
665static const struct mmc_host_ops cb710_mmc_host = {
666 .request = cb710_mmc_request,
667 .set_ios = cb710_mmc_set_ios,
668 .get_ro = cb710_mmc_get_ro
669};
670
671#ifdef CONFIG_PM
672
673static int cb710_mmc_suspend(struct platform_device *pdev, pm_message_t state)
674{
675 struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
676 struct mmc_host *mmc = cb710_slot_to_mmc(slot);
677 int err;
678
679 err = mmc_suspend_host(mmc, state);
680 if (err)
681 return err;
682
683 cb710_mmc_enable_irq(slot, 0, ~0);
684 return 0;
685}
686
687static int cb710_mmc_resume(struct platform_device *pdev)
688{
689 struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
690 struct mmc_host *mmc = cb710_slot_to_mmc(slot);
691
692 cb710_mmc_enable_irq(slot, 0, ~0);
693
694 return mmc_resume_host(mmc);
695}
696
697#endif /* CONFIG_PM */
698
699static int __devinit cb710_mmc_init(struct platform_device *pdev)
700{
701 struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
702 struct cb710_chip *chip = cb710_slot_to_chip(slot);
703 struct mmc_host *mmc;
704 struct cb710_mmc_reader *reader;
705 int err;
706 u32 val;
707
708 mmc = mmc_alloc_host(sizeof(*reader), cb710_slot_dev(slot));
709 if (!mmc)
710 return -ENOMEM;
711
712 dev_set_drvdata(&pdev->dev, mmc);
713
714 /* harmless (maybe) magic */
715 pci_read_config_dword(chip->pdev, 0x48, &val);
716 val = cb710_src_freq_mhz[(val >> 16) & 0xF];
717 dev_dbg(cb710_slot_dev(slot), "source frequency: %dMHz\n", val);
718 val *= 1000000;
719
720 mmc->ops = &cb710_mmc_host;
721 mmc->f_max = val;
722 mmc->f_min = val >> cb710_clock_divider_log2[CB710_MAX_DIVIDER_IDX];
723 mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
724 mmc->caps = MMC_CAP_4_BIT_DATA;
725
726 reader = mmc_priv(mmc);
727
728 tasklet_init(&reader->finish_req_tasklet,
729 cb710_mmc_finish_request_tasklet, (unsigned long)mmc);
730 spin_lock_init(&reader->irq_lock);
731 cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
732
733 cb710_mmc_enable_irq(slot, 0, ~0);
734 cb710_set_irq_handler(slot, cb710_mmc_irq_handler);
735
736 err = mmc_add_host(mmc);
737 if (unlikely(err))
738 goto err_free_mmc;
739
740 dev_dbg(cb710_slot_dev(slot), "mmc_hostname is %s\n",
741 mmc_hostname(mmc));
742
743 cb710_mmc_enable_irq(slot, CB710_MMC_IE_CARD_INSERTION_STATUS, 0);
744
745 return 0;
746
747err_free_mmc:
748 dev_dbg(cb710_slot_dev(slot), "mmc_add_host() failed: %d\n", err);
749
750 mmc_free_host(mmc);
751 return err;
752}
753
754static int __devexit cb710_mmc_exit(struct platform_device *pdev)
755{
756 struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
757 struct mmc_host *mmc = cb710_slot_to_mmc(slot);
758 struct cb710_mmc_reader *reader = mmc_priv(mmc);
759
760 cb710_mmc_enable_irq(slot, 0, CB710_MMC_IE_CARD_INSERTION_STATUS);
761
762 mmc_remove_host(mmc);
763
764 /* IRQs should be disabled now, but let's stay on the safe side */
765 cb710_mmc_enable_irq(slot, 0, ~0);
766 cb710_set_irq_handler(slot, NULL);
767
768 /* clear config ports - just in case */
769 cb710_write_port_32(slot, CB710_MMC_CONFIG_PORT, 0);
770 cb710_write_port_16(slot, CB710_MMC_CONFIGB_PORT, 0);
771
772 tasklet_kill(&reader->finish_req_tasklet);
773
774 mmc_free_host(mmc);
775 return 0;
776}
777
778static struct platform_driver cb710_mmc_driver = {
779 .driver.name = "cb710-mmc",
780 .probe = cb710_mmc_init,
781 .remove = __devexit_p(cb710_mmc_exit),
782#ifdef CONFIG_PM
783 .suspend = cb710_mmc_suspend,
784 .resume = cb710_mmc_resume,
785#endif
786};
787
788static int __init cb710_mmc_init_module(void)
789{
790 return platform_driver_register(&cb710_mmc_driver);
791}
792
793static void __exit cb710_mmc_cleanup_module(void)
794{
795 platform_driver_unregister(&cb710_mmc_driver);
796}
797
798module_init(cb710_mmc_init_module);
799module_exit(cb710_mmc_cleanup_module);
800
801MODULE_AUTHOR("Michał Mirosław <mirq-linux@rere.qmqm.pl>");
802MODULE_DESCRIPTION("ENE CB710 memory card reader driver - MMC/SD part");
803MODULE_LICENSE("GPL");
804MODULE_ALIAS("platform:cb710-mmc");
diff --git a/drivers/mmc/host/cb710-mmc.h b/drivers/mmc/host/cb710-mmc.h
new file mode 100644
index 000000000000..e845c776bdd7
--- /dev/null
+++ b/drivers/mmc/host/cb710-mmc.h
@@ -0,0 +1,104 @@
1/*
2 * cb710/cb710-mmc.h
3 *
4 * Copyright by Michał Mirosław, 2008-2009
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef LINUX_CB710_MMC_H
11#define LINUX_CB710_MMC_H
12
13#include <linux/cb710.h>
14
15/* per-MMC-reader structure */
16struct cb710_mmc_reader {
17 struct tasklet_struct finish_req_tasklet;
18 struct mmc_request *mrq;
19 spinlock_t irq_lock;
20 unsigned char last_power_mode;
21};
22
23/* some device struct walking */
24
25static inline struct mmc_host *cb710_slot_to_mmc(struct cb710_slot *slot)
26{
27 return dev_get_drvdata(&slot->pdev.dev);
28}
29
30static inline struct cb710_slot *cb710_mmc_to_slot(struct mmc_host *mmc)
31{
32 struct platform_device *pdev = container_of(mmc_dev(mmc),
33 struct platform_device, dev);
34 return cb710_pdev_to_slot(pdev);
35}
36
37/* registers (this might be all wrong ;) */
38
39#define CB710_MMC_DATA_PORT 0x00
40
41#define CB710_MMC_CONFIG_PORT 0x04
42#define CB710_MMC_CONFIG0_PORT 0x04
43#define CB710_MMC_CONFIG1_PORT 0x05
44#define CB710_MMC_C1_4BIT_DATA_BUS 0x40
45#define CB710_MMC_CONFIG2_PORT 0x06
46#define CB710_MMC_C2_READ_PIO_SIZE_MASK 0x0F /* N-1 */
47#define CB710_MMC_CONFIG3_PORT 0x07
48
49#define CB710_MMC_CONFIGB_PORT 0x08
50
51#define CB710_MMC_IRQ_ENABLE_PORT 0x0C
52#define CB710_MMC_IE_TEST_MASK 0x00BF
53#define CB710_MMC_IE_CARD_INSERTION_STATUS 0x1000
54#define CB710_MMC_IE_IRQ_ENABLE 0x8000
55#define CB710_MMC_IE_CISTATUS_MASK \
56 (CB710_MMC_IE_CARD_INSERTION_STATUS|CB710_MMC_IE_IRQ_ENABLE)
57
58#define CB710_MMC_STATUS_PORT 0x10
59#define CB710_MMC_STATUS_ERROR_EVENTS 0x60FF
60#define CB710_MMC_STATUS0_PORT 0x10
61#define CB710_MMC_S0_FIFO_UNDERFLOW 0x40
62#define CB710_MMC_STATUS1_PORT 0x11
63#define CB710_MMC_S1_COMMAND_SENT 0x01
64#define CB710_MMC_S1_DATA_TRANSFER_DONE 0x02
65#define CB710_MMC_S1_PIO_TRANSFER_DONE 0x04
66#define CB710_MMC_S1_CARD_CHANGED 0x10
67#define CB710_MMC_S1_RESET 0x20
68#define CB710_MMC_STATUS2_PORT 0x12
69#define CB710_MMC_S2_FIFO_READY 0x01
70#define CB710_MMC_S2_FIFO_EMPTY 0x02
71#define CB710_MMC_S2_BUSY_10 0x10
72#define CB710_MMC_S2_BUSY_20 0x20
73#define CB710_MMC_STATUS3_PORT 0x13
74#define CB710_MMC_S3_CARD_DETECTED 0x02
75#define CB710_MMC_S3_WRITE_PROTECTED 0x04
76
77#define CB710_MMC_CMD_TYPE_PORT 0x14
78#define CB710_MMC_RSP_TYPE_MASK 0x0007
79#define CB710_MMC_RSP_R1 (0)
80#define CB710_MMC_RSP_136 (5)
81#define CB710_MMC_RSP_NO_CRC (2)
82#define CB710_MMC_RSP_PRESENT_MASK 0x0018
83#define CB710_MMC_RSP_NONE (0 << 3)
84#define CB710_MMC_RSP_PRESENT (1 << 3)
85#define CB710_MMC_RSP_PRESENT_X (2 << 3)
86#define CB710_MMC_CMD_TYPE_MASK 0x0060
87#define CB710_MMC_CMD_BC (0 << 5)
88#define CB710_MMC_CMD_BCR (1 << 5)
89#define CB710_MMC_CMD_AC (2 << 5)
90#define CB710_MMC_CMD_ADTC (3 << 5)
91#define CB710_MMC_DATA_READ 0x0080
92#define CB710_MMC_CMD_CODE_MASK 0x3F00
93#define CB710_MMC_CMD_CODE_SHIFT 8
94#define CB710_MMC_IS_APP_CMD 0x4000
95#define CB710_MMC_RSP_BUSY 0x8000
96
97#define CB710_MMC_CMD_PARAM_PORT 0x18
98#define CB710_MMC_TRANSFER_SIZE_PORT 0x1C
99#define CB710_MMC_RESPONSE0_PORT 0x20
100#define CB710_MMC_RESPONSE1_PORT 0x24
101#define CB710_MMC_RESPONSE2_PORT 0x28
102#define CB710_MMC_RESPONSE3_PORT 0x2C
103
104#endif /* LINUX_CB710_MMC_H */
diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c
index f48349d18c92..240608cc7ae9 100644
--- a/drivers/mmc/host/mmc_spi.c
+++ b/drivers/mmc/host/mmc_spi.c
@@ -97,6 +97,14 @@
97 */ 97 */
98#define r1b_timeout (HZ * 3) 98#define r1b_timeout (HZ * 3)
99 99
100/* One of the critical speed parameters is the amount of data which may
101 * be transfered in one command. If this value is too low, the SD card
102 * controller has to do multiple partial block writes (argggh!). With
103 * today (2008) SD cards there is little speed gain if we transfer more
104 * than 64 KBytes at a time. So use this value until there is any indication
105 * that we should do more here.
106 */
107#define MMC_SPI_BLOCKSATONCE 128
100 108
101/****************************************************************************/ 109/****************************************************************************/
102 110
@@ -327,15 +335,16 @@ checkstatus:
327 335
328 /* Status byte: the entire seven-bit R1 response. */ 336 /* Status byte: the entire seven-bit R1 response. */
329 if (cmd->resp[0] != 0) { 337 if (cmd->resp[0] != 0) {
330 if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS 338 if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS)
331 | R1_SPI_ILLEGAL_COMMAND)
332 & cmd->resp[0]) 339 & cmd->resp[0])
333 value = -EINVAL; 340 value = -EFAULT; /* Bad address */
341 else if (R1_SPI_ILLEGAL_COMMAND & cmd->resp[0])
342 value = -ENOSYS; /* Function not implemented */
334 else if (R1_SPI_COM_CRC & cmd->resp[0]) 343 else if (R1_SPI_COM_CRC & cmd->resp[0])
335 value = -EILSEQ; 344 value = -EILSEQ; /* Illegal byte sequence */
336 else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET) 345 else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET)
337 & cmd->resp[0]) 346 & cmd->resp[0])
338 value = -EIO; 347 value = -EIO; /* I/O error */
339 /* else R1_SPI_IDLE, "it's resetting" */ 348 /* else R1_SPI_IDLE, "it's resetting" */
340 } 349 }
341 350
@@ -1366,6 +1375,10 @@ static int mmc_spi_probe(struct spi_device *spi)
1366 1375
1367 mmc->ops = &mmc_spi_ops; 1376 mmc->ops = &mmc_spi_ops;
1368 mmc->max_blk_size = MMC_SPI_BLOCKSIZE; 1377 mmc->max_blk_size = MMC_SPI_BLOCKSIZE;
1378 mmc->max_hw_segs = MMC_SPI_BLOCKSATONCE;
1379 mmc->max_phys_segs = MMC_SPI_BLOCKSATONCE;
1380 mmc->max_req_size = MMC_SPI_BLOCKSATONCE * MMC_SPI_BLOCKSIZE;
1381 mmc->max_blk_count = MMC_SPI_BLOCKSATONCE;
1369 1382
1370 mmc->caps = MMC_CAP_SPI; 1383 mmc->caps = MMC_CAP_SPI;
1371 1384
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 7d4febdab286..e1aa8471ab1c 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -546,7 +546,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
546 host->mclk = clk_get_rate(host->clk); 546 host->mclk = clk_get_rate(host->clk);
547 DBG(host, "eventual mclk rate: %u Hz\n", host->mclk); 547 DBG(host, "eventual mclk rate: %u Hz\n", host->mclk);
548 } 548 }
549 host->base = ioremap(dev->res.start, SZ_4K); 549 host->base = ioremap(dev->res.start, resource_size(&dev->res));
550 if (!host->base) { 550 if (!host->base) {
551 ret = -ENOMEM; 551 ret = -ENOMEM;
552 goto clk_disable; 552 goto clk_disable;
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index f4cbe473670e..bc14bb1b0579 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -746,8 +746,6 @@ static int mxcmci_probe(struct platform_device *pdev)
746 } 746 }
747 747
748 mmc->f_min = clk_get_rate(host->clk) >> 16; 748 mmc->f_min = clk_get_rate(host->clk) >> 16;
749 if (mmc->f_min < 400000)
750 mmc->f_min = 400000;
751 mmc->f_max = clk_get_rate(host->clk) >> 1; 749 mmc->f_max = clk_get_rate(host->clk) >> 1;
752 750
753 /* recommended in data sheet */ 751 /* recommended in data sheet */
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index dceb5ee3bda0..e7a331de5733 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -1593,7 +1593,6 @@ static int mmc_omap_resume(struct platform_device *pdev)
1593#endif 1593#endif
1594 1594
1595static struct platform_driver mmc_omap_driver = { 1595static struct platform_driver mmc_omap_driver = {
1596 .probe = mmc_omap_probe,
1597 .remove = mmc_omap_remove, 1596 .remove = mmc_omap_remove,
1598 .suspend = mmc_omap_suspend, 1597 .suspend = mmc_omap_suspend,
1599 .resume = mmc_omap_resume, 1598 .resume = mmc_omap_resume,
@@ -1605,7 +1604,7 @@ static struct platform_driver mmc_omap_driver = {
1605 1604
1606static int __init mmc_omap_init(void) 1605static int __init mmc_omap_init(void)
1607{ 1606{
1608 return platform_driver_register(&mmc_omap_driver); 1607 return platform_driver_probe(&mmc_omap_driver, mmc_omap_probe);
1609} 1608}
1610 1609
1611static void __exit mmc_omap_exit(void) 1610static void __exit mmc_omap_exit(void)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index c40cb96255a2..1cf9cfb3b64f 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1073,7 +1073,6 @@ static int __init omap_mmc_probe(struct platform_device *pdev)
1073 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1073 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1074 mmc->max_seg_size = mmc->max_req_size; 1074 mmc->max_seg_size = mmc->max_req_size;
1075 1075
1076 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1077 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED; 1076 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1078 1077
1079 if (pdata->slots[host->slot_id].wires >= 8) 1078 if (pdata->slots[host->slot_id].wires >= 8)
@@ -1110,13 +1109,14 @@ static int __init omap_mmc_probe(struct platform_device *pdev)
1110 goto err_irq; 1109 goto err_irq;
1111 } 1110 }
1112 1111
1112 /* initialize power supplies, gpios, etc */
1113 if (pdata->init != NULL) { 1113 if (pdata->init != NULL) {
1114 if (pdata->init(&pdev->dev) != 0) { 1114 if (pdata->init(&pdev->dev) != 0) {
1115 dev_dbg(mmc_dev(host->mmc), 1115 dev_dbg(mmc_dev(host->mmc), "late init error\n");
1116 "Unable to configure MMC IRQs\n");
1117 goto err_irq_cd_init; 1116 goto err_irq_cd_init;
1118 } 1117 }
1119 } 1118 }
1119 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1120 1120
1121 /* Request IRQ for card detect */ 1121 /* Request IRQ for card detect */
1122 if ((mmc_slot(host).card_detect_irq)) { 1122 if ((mmc_slot(host).card_detect_irq)) {
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 430095725f9f..d7d7109ef47e 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -27,6 +27,7 @@
27#include <linux/err.h> 27#include <linux/err.h>
28#include <linux/mmc/host.h> 28#include <linux/mmc/host.h>
29#include <linux/io.h> 29#include <linux/io.h>
30#include <linux/regulator/consumer.h>
30 31
31#include <asm/sizes.h> 32#include <asm/sizes.h>
32 33
@@ -67,8 +68,42 @@ struct pxamci_host {
67 unsigned int dma_dir; 68 unsigned int dma_dir;
68 unsigned int dma_drcmrrx; 69 unsigned int dma_drcmrrx;
69 unsigned int dma_drcmrtx; 70 unsigned int dma_drcmrtx;
71
72 struct regulator *vcc;
70}; 73};
71 74
75static inline void pxamci_init_ocr(struct pxamci_host *host)
76{
77#ifdef CONFIG_REGULATOR
78 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
79
80 if (IS_ERR(host->vcc))
81 host->vcc = NULL;
82 else {
83 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
84 if (host->pdata && host->pdata->ocr_mask)
85 dev_warn(mmc_dev(host->mmc),
86 "ocr_mask/setpower will not be used\n");
87 }
88#endif
89 if (host->vcc == NULL) {
90 /* fall-back to platform data */
91 host->mmc->ocr_avail = host->pdata ?
92 host->pdata->ocr_mask :
93 MMC_VDD_32_33 | MMC_VDD_33_34;
94 }
95}
96
97static inline void pxamci_set_power(struct pxamci_host *host, unsigned int vdd)
98{
99#ifdef CONFIG_REGULATOR
100 if (host->vcc)
101 mmc_regulator_set_ocr(host->vcc, vdd);
102#endif
103 if (!host->vcc && host->pdata && host->pdata->setpower)
104 host->pdata->setpower(mmc_dev(host->mmc), vdd);
105}
106
72static void pxamci_stop_clock(struct pxamci_host *host) 107static void pxamci_stop_clock(struct pxamci_host *host)
73{ 108{
74 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { 109 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
@@ -438,8 +473,7 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
438 if (host->power_mode != ios->power_mode) { 473 if (host->power_mode != ios->power_mode) {
439 host->power_mode = ios->power_mode; 474 host->power_mode = ios->power_mode;
440 475
441 if (host->pdata && host->pdata->setpower) 476 pxamci_set_power(host, ios->vdd);
442 host->pdata->setpower(mmc_dev(mmc), ios->vdd);
443 477
444 if (ios->power_mode == MMC_POWER_ON) 478 if (ios->power_mode == MMC_POWER_ON)
445 host->cmdat |= CMDAT_INIT; 479 host->cmdat |= CMDAT_INIT;
@@ -562,9 +596,8 @@ static int pxamci_probe(struct platform_device *pdev)
562 mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000 596 mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000
563 : host->clkrate; 597 : host->clkrate;
564 598
565 mmc->ocr_avail = host->pdata ? 599 pxamci_init_ocr(host);
566 host->pdata->ocr_mask : 600
567 MMC_VDD_32_33|MMC_VDD_33_34;
568 mmc->caps = 0; 601 mmc->caps = 0;
569 host->cmdat = 0; 602 host->cmdat = 0;
570 if (!cpu_is_pxa25x()) { 603 if (!cpu_is_pxa25x()) {
@@ -661,6 +694,9 @@ static int pxamci_remove(struct platform_device *pdev)
661 if (mmc) { 694 if (mmc) {
662 struct pxamci_host *host = mmc_priv(mmc); 695 struct pxamci_host *host = mmc_priv(mmc);
663 696
697 if (host->vcc)
698 regulator_put(host->vcc);
699
664 if (host->pdata && host->pdata->exit) 700 if (host->pdata && host->pdata->exit)
665 host->pdata->exit(&pdev->dev, mmc); 701 host->pdata->exit(&pdev->dev, mmc);
666 702
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 2db166b7096f..8c08cd7efa7f 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -17,6 +17,7 @@
17#include <linux/mmc/host.h> 17#include <linux/mmc/host.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/cpufreq.h> 19#include <linux/cpufreq.h>
20#include <linux/gpio.h>
20#include <linux/irq.h> 21#include <linux/irq.h>
21#include <linux/io.h> 22#include <linux/io.h>
22 23
@@ -789,11 +790,11 @@ static void s3cmci_dma_setup(struct s3cmci_host *host,
789 790
790 last_source = source; 791 last_source = source;
791 792
792 s3c2410_dma_devconfig(host->dma, source, 3, 793 s3c2410_dma_devconfig(host->dma, source,
793 host->mem->start + host->sdidata); 794 host->mem->start + host->sdidata);
794 795
795 if (!setup_ok) { 796 if (!setup_ok) {
796 s3c2410_dma_config(host->dma, 4, 0); 797 s3c2410_dma_config(host->dma, 4);
797 s3c2410_dma_set_buffdone_fn(host->dma, 798 s3c2410_dma_set_buffdone_fn(host->dma,
798 s3cmci_dma_done_callback); 799 s3cmci_dma_done_callback);
799 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART); 800 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
@@ -1121,7 +1122,7 @@ static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1121 case MMC_POWER_OFF: 1122 case MMC_POWER_OFF:
1122 default: 1123 default:
1123 s3c2410_gpio_setpin(S3C2410_GPE5, 0); 1124 s3c2410_gpio_setpin(S3C2410_GPE5, 0);
1124 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_OUTP); 1125 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPIO_OUTPUT);
1125 1126
1126 if (host->is2440) 1127 if (host->is2440)
1127 mci_con |= S3C2440_SDICON_SDRESET; 1128 mci_con |= S3C2440_SDICON_SDRESET;
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
index 128c614d11aa..d79fa55c3b89 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of.c
@@ -250,6 +250,9 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,
250 host->ops = &sdhci_of_data->ops; 250 host->ops = &sdhci_of_data->ops;
251 } 251 }
252 252
253 if (of_get_property(np, "sdhci,1-bit-only", NULL))
254 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
255
253 clk = of_get_property(np, "clock-frequency", &size); 256 clk = of_get_property(np, "clock-frequency", &size);
254 if (clk && size == sizeof(*clk) && *clk) 257 if (clk && size == sizeof(*clk) && *clk)
255 of_host->clock = *clk; 258 of_host->clock = *clk;
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index 65be27995d5c..2f15cc17d887 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -284,6 +284,18 @@ static const struct sdhci_pci_fixes sdhci_jmicron = {
284 .resume = jmicron_resume, 284 .resume = jmicron_resume,
285}; 285};
286 286
287static int via_probe(struct sdhci_pci_chip *chip)
288{
289 if (chip->pdev->revision == 0x10)
290 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
291
292 return 0;
293}
294
295static const struct sdhci_pci_fixes sdhci_via = {
296 .probe = via_probe,
297};
298
287static const struct pci_device_id pci_ids[] __devinitdata = { 299static const struct pci_device_id pci_ids[] __devinitdata = {
288 { 300 {
289 .vendor = PCI_VENDOR_ID_RICOH, 301 .vendor = PCI_VENDOR_ID_RICOH,
@@ -349,6 +361,14 @@ static const struct pci_device_id pci_ids[] __devinitdata = {
349 .driver_data = (kernel_ulong_t)&sdhci_jmicron, 361 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
350 }, 362 },
351 363
364 {
365 .vendor = PCI_VENDOR_ID_VIA,
366 .device = 0x95d0,
367 .subvendor = PCI_ANY_ID,
368 .subdevice = PCI_ANY_ID,
369 .driver_data = (kernel_ulong_t)&sdhci_via,
370 },
371
352 { /* Generic SD host controller */ 372 { /* Generic SD host controller */
353 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 373 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
354 }, 374 },
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
new file mode 100644
index 000000000000..297f40ae6ad5
--- /dev/null
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -0,0 +1,168 @@
1/*
2 * sdhci-pltfm.c Support for SDHCI platform devices
3 * Copyright (c) 2009 Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* Supports:
20 * SDHCI platform devices
21 *
22 * Inspired by sdhci-pci.c, by Pierre Ossman
23 */
24
25#include <linux/delay.h>
26#include <linux/highmem.h>
27#include <linux/platform_device.h>
28
29#include <linux/mmc/host.h>
30
31#include <linux/io.h>
32
33#include "sdhci.h"
34
35/*****************************************************************************\
36 * *
37 * SDHCI core callbacks *
38 * *
39\*****************************************************************************/
40
41static struct sdhci_ops sdhci_pltfm_ops = {
42};
43
44/*****************************************************************************\
45 * *
46 * Device probing/removal *
47 * *
48\*****************************************************************************/
49
50static int __devinit sdhci_pltfm_probe(struct platform_device *pdev)
51{
52 struct sdhci_host *host;
53 struct resource *iomem;
54 int ret;
55
56 BUG_ON(pdev == NULL);
57
58 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
59 if (!iomem) {
60 ret = -ENOMEM;
61 goto err;
62 }
63
64 if (resource_size(iomem) != 0x100)
65 dev_err(&pdev->dev, "Invalid iomem size. You may "
66 "experience problems.\n");
67
68 if (pdev->dev.parent)
69 host = sdhci_alloc_host(pdev->dev.parent, 0);
70 else
71 host = sdhci_alloc_host(&pdev->dev, 0);
72
73 if (IS_ERR(host)) {
74 ret = PTR_ERR(host);
75 goto err;
76 }
77
78 host->hw_name = "platform";
79 host->ops = &sdhci_pltfm_ops;
80 host->irq = platform_get_irq(pdev, 0);
81
82 if (!request_mem_region(iomem->start, resource_size(iomem),
83 mmc_hostname(host->mmc))) {
84 dev_err(&pdev->dev, "cannot request region\n");
85 ret = -EBUSY;
86 goto err_request;
87 }
88
89 host->ioaddr = ioremap(iomem->start, resource_size(iomem));
90 if (!host->ioaddr) {
91 dev_err(&pdev->dev, "failed to remap registers\n");
92 ret = -ENOMEM;
93 goto err_remap;
94 }
95
96 ret = sdhci_add_host(host);
97 if (ret)
98 goto err_add_host;
99
100 platform_set_drvdata(pdev, host);
101
102 return 0;
103
104err_add_host:
105 iounmap(host->ioaddr);
106err_remap:
107 release_mem_region(iomem->start, resource_size(iomem));
108err_request:
109 sdhci_free_host(host);
110err:
111 printk(KERN_ERR"Probing of sdhci-pltfm failed: %d\n", ret);
112 return ret;
113}
114
115static int __devexit sdhci_pltfm_remove(struct platform_device *pdev)
116{
117 struct sdhci_host *host = platform_get_drvdata(pdev);
118 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
119 int dead;
120 u32 scratch;
121
122 dead = 0;
123 scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
124 if (scratch == (u32)-1)
125 dead = 1;
126
127 sdhci_remove_host(host, dead);
128 iounmap(host->ioaddr);
129 release_mem_region(iomem->start, resource_size(iomem));
130 sdhci_free_host(host);
131 platform_set_drvdata(pdev, NULL);
132
133 return 0;
134}
135
136static struct platform_driver sdhci_pltfm_driver = {
137 .driver = {
138 .name = "sdhci",
139 .owner = THIS_MODULE,
140 },
141 .probe = sdhci_pltfm_probe,
142 .remove = __devexit_p(sdhci_pltfm_remove),
143};
144
145/*****************************************************************************\
146 * *
147 * Driver init/exit *
148 * *
149\*****************************************************************************/
150
151static int __init sdhci_drv_init(void)
152{
153 return platform_driver_register(&sdhci_pltfm_driver);
154}
155
156static void __exit sdhci_drv_exit(void)
157{
158 platform_driver_unregister(&sdhci_pltfm_driver);
159}
160
161module_init(sdhci_drv_init);
162module_exit(sdhci_drv_exit);
163
164MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver");
165MODULE_AUTHOR("Mocean Laboratories <info@mocean-labs.com>");
166MODULE_LICENSE("GPL v2");
167MODULE_ALIAS("platform:sdhci");
168
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
new file mode 100644
index 000000000000..50997d2a63e7
--- /dev/null
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -0,0 +1,428 @@
1/* linux/drivers/mmc/host/sdhci-s3c.c
2 *
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * SDHCI (HSMMC) support for Samsung SoC
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/delay.h>
16#include <linux/dma-mapping.h>
17#include <linux/platform_device.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <linux/mmc/host.h>
22
23#include <plat/sdhci.h>
24#include <plat/regs-sdhci.h>
25
26#include "sdhci.h"
27
28#define MAX_BUS_CLK (4)
29
30/**
31 * struct sdhci_s3c - S3C SDHCI instance
32 * @host: The SDHCI host created
33 * @pdev: The platform device we where created from.
34 * @ioarea: The resource created when we claimed the IO area.
35 * @pdata: The platform data for this controller.
36 * @cur_clk: The index of the current bus clock.
37 * @clk_io: The clock for the internal bus interface.
38 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
39 */
40struct sdhci_s3c {
41 struct sdhci_host *host;
42 struct platform_device *pdev;
43 struct resource *ioarea;
44 struct s3c_sdhci_platdata *pdata;
45 unsigned int cur_clk;
46
47 struct clk *clk_io;
48 struct clk *clk_bus[MAX_BUS_CLK];
49};
50
51static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
52{
53 return sdhci_priv(host);
54}
55
56/**
57 * get_curclk - convert ctrl2 register to clock source number
58 * @ctrl2: Control2 register value.
59 */
60static u32 get_curclk(u32 ctrl2)
61{
62 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
63 ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
64
65 return ctrl2;
66}
67
68static void sdhci_s3c_check_sclk(struct sdhci_host *host)
69{
70 struct sdhci_s3c *ourhost = to_s3c(host);
71 u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
72
73 if (get_curclk(tmp) != ourhost->cur_clk) {
74 dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
75
76 tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
77 tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
78 writel(tmp, host->ioaddr + 0x80);
79 }
80}
81
82/**
83 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
84 * @host: The SDHCI host instance.
85 *
86 * Callback to return the maximum clock rate acheivable by the controller.
87*/
88static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
89{
90 struct sdhci_s3c *ourhost = to_s3c(host);
91 struct clk *busclk;
92 unsigned int rate, max;
93 int clk;
94
95 /* note, a reset will reset the clock source */
96
97 sdhci_s3c_check_sclk(host);
98
99 for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
100 busclk = ourhost->clk_bus[clk];
101 if (!busclk)
102 continue;
103
104 rate = clk_get_rate(busclk);
105 if (rate > max)
106 max = rate;
107 }
108
109 return max;
110}
111
112static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host)
113{
114 return sdhci_s3c_get_max_clk(host) / 1000000;
115}
116
117/**
118 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
119 * @ourhost: Our SDHCI instance.
120 * @src: The source clock index.
121 * @wanted: The clock frequency wanted.
122 */
123static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
124 unsigned int src,
125 unsigned int wanted)
126{
127 unsigned long rate;
128 struct clk *clksrc = ourhost->clk_bus[src];
129 int div;
130
131 if (!clksrc)
132 return UINT_MAX;
133
134 rate = clk_get_rate(clksrc);
135
136 for (div = 1; div < 256; div *= 2) {
137 if ((rate / div) <= wanted)
138 break;
139 }
140
141 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
142 src, rate, wanted, rate / div);
143
144 return (wanted - (rate / div));
145}
146
147/**
148 * sdhci_s3c_set_clock - callback on clock change
149 * @host: The SDHCI host being changed
150 * @clock: The clock rate being requested.
151 *
152 * When the card's clock is going to be changed, look at the new frequency
153 * and find the best clock source to go with it.
154*/
155static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
156{
157 struct sdhci_s3c *ourhost = to_s3c(host);
158 unsigned int best = UINT_MAX;
159 unsigned int delta;
160 int best_src = 0;
161 int src;
162 u32 ctrl;
163
164 /* don't bother if the clock is going off. */
165 if (clock == 0)
166 return;
167
168 for (src = 0; src < MAX_BUS_CLK; src++) {
169 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
170 if (delta < best) {
171 best = delta;
172 best_src = src;
173 }
174 }
175
176 dev_dbg(&ourhost->pdev->dev,
177 "selected source %d, clock %d, delta %d\n",
178 best_src, clock, best);
179
180 /* select the new clock source */
181
182 if (ourhost->cur_clk != best_src) {
183 struct clk *clk = ourhost->clk_bus[best_src];
184
185 /* turn clock off to card before changing clock source */
186 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
187
188 ourhost->cur_clk = best_src;
189 host->max_clk = clk_get_rate(clk);
190 host->timeout_clk = sdhci_s3c_get_timeout_clk(host);
191
192 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
193 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
194 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
195 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
196 }
197
198 /* reconfigure the hardware for new clock rate */
199
200 {
201 struct mmc_ios ios;
202
203 ios.clock = clock;
204
205 if (ourhost->pdata->cfg_card)
206 (ourhost->pdata->cfg_card)(ourhost->pdev, host->ioaddr,
207 &ios, NULL);
208 }
209}
210
211static struct sdhci_ops sdhci_s3c_ops = {
212 .get_max_clock = sdhci_s3c_get_max_clk,
213 .get_timeout_clock = sdhci_s3c_get_timeout_clk,
214 .set_clock = sdhci_s3c_set_clock,
215};
216
217static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
218{
219 struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
220 struct device *dev = &pdev->dev;
221 struct sdhci_host *host;
222 struct sdhci_s3c *sc;
223 struct resource *res;
224 int ret, irq, ptr, clks;
225
226 if (!pdata) {
227 dev_err(dev, "no device data specified\n");
228 return -ENOENT;
229 }
230
231 irq = platform_get_irq(pdev, 0);
232 if (irq < 0) {
233 dev_err(dev, "no irq specified\n");
234 return irq;
235 }
236
237 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
238 if (!res) {
239 dev_err(dev, "no memory specified\n");
240 return -ENOENT;
241 }
242
243 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
244 if (IS_ERR(host)) {
245 dev_err(dev, "sdhci_alloc_host() failed\n");
246 return PTR_ERR(host);
247 }
248
249 sc = sdhci_priv(host);
250
251 sc->host = host;
252 sc->pdev = pdev;
253 sc->pdata = pdata;
254
255 platform_set_drvdata(pdev, host);
256
257 sc->clk_io = clk_get(dev, "hsmmc");
258 if (IS_ERR(sc->clk_io)) {
259 dev_err(dev, "failed to get io clock\n");
260 ret = PTR_ERR(sc->clk_io);
261 goto err_io_clk;
262 }
263
264 /* enable the local io clock and keep it running for the moment. */
265 clk_enable(sc->clk_io);
266
267 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
268 struct clk *clk;
269 char *name = pdata->clocks[ptr];
270
271 if (name == NULL)
272 continue;
273
274 clk = clk_get(dev, name);
275 if (IS_ERR(clk)) {
276 dev_err(dev, "failed to get clock %s\n", name);
277 continue;
278 }
279
280 clks++;
281 sc->clk_bus[ptr] = clk;
282 clk_enable(clk);
283
284 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
285 ptr, name, clk_get_rate(clk));
286 }
287
288 if (clks == 0) {
289 dev_err(dev, "failed to find any bus clocks\n");
290 ret = -ENOENT;
291 goto err_no_busclks;
292 }
293
294 sc->ioarea = request_mem_region(res->start, resource_size(res),
295 mmc_hostname(host->mmc));
296 if (!sc->ioarea) {
297 dev_err(dev, "failed to reserve register area\n");
298 ret = -ENXIO;
299 goto err_req_regs;
300 }
301
302 host->ioaddr = ioremap_nocache(res->start, resource_size(res));
303 if (!host->ioaddr) {
304 dev_err(dev, "failed to map registers\n");
305 ret = -ENXIO;
306 goto err_req_regs;
307 }
308
309 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
310 if (pdata->cfg_gpio)
311 pdata->cfg_gpio(pdev, pdata->max_width);
312
313 host->hw_name = "samsung-hsmmc";
314 host->ops = &sdhci_s3c_ops;
315 host->quirks = 0;
316 host->irq = irq;
317
318 /* Setup quirks for the controller */
319
320 /* Currently with ADMA enabled we are getting some length
321 * interrupts that are not being dealt with, do disable
322 * ADMA until this is sorted out. */
323 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
324 host->quirks |= SDHCI_QUIRK_32BIT_ADMA_SIZE;
325
326#ifndef CONFIG_MMC_SDHCI_S3C_DMA
327
328 /* we currently see overruns on errors, so disable the SDMA
329 * support as well. */
330 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
331
332 /* PIO currently has problems with multi-block IO */
333 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
334
335#endif /* CONFIG_MMC_SDHCI_S3C_DMA */
336
337 /* It seems we do not get an DATA transfer complete on non-busy
338 * transfers, not sure if this is a problem with this specific
339 * SDHCI block, or a missing configuration that needs to be set. */
340 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
341
342 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
343 SDHCI_QUIRK_32BIT_DMA_SIZE);
344
345 ret = sdhci_add_host(host);
346 if (ret) {
347 dev_err(dev, "sdhci_add_host() failed\n");
348 goto err_add_host;
349 }
350
351 return 0;
352
353 err_add_host:
354 release_resource(sc->ioarea);
355 kfree(sc->ioarea);
356
357 err_req_regs:
358 for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
359 clk_disable(sc->clk_bus[ptr]);
360 clk_put(sc->clk_bus[ptr]);
361 }
362
363 err_no_busclks:
364 clk_disable(sc->clk_io);
365 clk_put(sc->clk_io);
366
367 err_io_clk:
368 sdhci_free_host(host);
369
370 return ret;
371}
372
373static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
374{
375 return 0;
376}
377
378#ifdef CONFIG_PM
379
380static int sdhci_s3c_suspend(struct platform_device *dev, pm_message_t pm)
381{
382 struct sdhci_host *host = platform_get_drvdata(dev);
383
384 sdhci_suspend_host(host, pm);
385 return 0;
386}
387
388static int sdhci_s3c_resume(struct platform_device *dev)
389{
390 struct sdhci_host *host = platform_get_drvdata(dev);
391
392 sdhci_resume_host(host);
393 return 0;
394}
395
396#else
397#define sdhci_s3c_suspend NULL
398#define sdhci_s3c_resume NULL
399#endif
400
401static struct platform_driver sdhci_s3c_driver = {
402 .probe = sdhci_s3c_probe,
403 .remove = __devexit_p(sdhci_s3c_remove),
404 .suspend = sdhci_s3c_suspend,
405 .resume = sdhci_s3c_resume,
406 .driver = {
407 .owner = THIS_MODULE,
408 .name = "s3c-sdhci",
409 },
410};
411
412static int __init sdhci_s3c_init(void)
413{
414 return platform_driver_register(&sdhci_s3c_driver);
415}
416
417static void __exit sdhci_s3c_exit(void)
418{
419 platform_driver_unregister(&sdhci_s3c_driver);
420}
421
422module_init(sdhci_s3c_init);
423module_exit(sdhci_s3c_exit);
424
425MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
426MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
427MODULE_LICENSE("GPL v2");
428MODULE_ALIAS("platform:s3c-sdhci");
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 9234be2226e7..6779b4ecab18 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -78,6 +78,11 @@ static void sdhci_dumpregs(struct sdhci_host *host)
78 sdhci_readl(host, SDHCI_CAPABILITIES), 78 sdhci_readl(host, SDHCI_CAPABILITIES),
79 sdhci_readl(host, SDHCI_MAX_CURRENT)); 79 sdhci_readl(host, SDHCI_MAX_CURRENT));
80 80
81 if (host->flags & SDHCI_USE_ADMA)
82 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
83 readl(host->ioaddr + SDHCI_ADMA_ERROR),
84 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
85
81 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); 86 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
82} 87}
83 88
@@ -579,7 +584,7 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
579 * longer to time out, but that's much better than having a too-short 584 * longer to time out, but that's much better than having a too-short
580 * timeout value. 585 * timeout value.
581 */ 586 */
582 if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)) 587 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
583 return 0xE; 588 return 0xE;
584 589
585 /* timeout in us */ 590 /* timeout in us */
@@ -1005,12 +1010,34 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1005{ 1010{
1006 u8 pwr; 1011 u8 pwr;
1007 1012
1008 if (host->power == power) 1013 if (power == (unsigned short)-1)
1014 pwr = 0;
1015 else {
1016 switch (1 << power) {
1017 case MMC_VDD_165_195:
1018 pwr = SDHCI_POWER_180;
1019 break;
1020 case MMC_VDD_29_30:
1021 case MMC_VDD_30_31:
1022 pwr = SDHCI_POWER_300;
1023 break;
1024 case MMC_VDD_32_33:
1025 case MMC_VDD_33_34:
1026 pwr = SDHCI_POWER_330;
1027 break;
1028 default:
1029 BUG();
1030 }
1031 }
1032
1033 if (host->pwr == pwr)
1009 return; 1034 return;
1010 1035
1011 if (power == (unsigned short)-1) { 1036 host->pwr = pwr;
1037
1038 if (pwr == 0) {
1012 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1039 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1013 goto out; 1040 return;
1014 } 1041 }
1015 1042
1016 /* 1043 /*
@@ -1020,35 +1047,23 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1020 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1047 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1021 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1048 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1022 1049
1023 pwr = SDHCI_POWER_ON;
1024
1025 switch (1 << power) {
1026 case MMC_VDD_165_195:
1027 pwr |= SDHCI_POWER_180;
1028 break;
1029 case MMC_VDD_29_30:
1030 case MMC_VDD_30_31:
1031 pwr |= SDHCI_POWER_300;
1032 break;
1033 case MMC_VDD_32_33:
1034 case MMC_VDD_33_34:
1035 pwr |= SDHCI_POWER_330;
1036 break;
1037 default:
1038 BUG();
1039 }
1040
1041 /* 1050 /*
1042 * At least the Marvell CaFe chip gets confused if we set the voltage 1051 * At least the Marvell CaFe chip gets confused if we set the voltage
1043 * and set turn on power at the same time, so set the voltage first. 1052 * and set turn on power at the same time, so set the voltage first.
1044 */ 1053 */
1045 if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)) 1054 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1046 sdhci_writeb(host, pwr & ~SDHCI_POWER_ON, SDHCI_POWER_CONTROL); 1055 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1056
1057 pwr |= SDHCI_POWER_ON;
1047 1058
1048 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1059 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1049 1060
1050out: 1061 /*
1051 host->power = power; 1062 * Some controllers need an extra 10ms delay of 10ms before they
1063 * can apply clock after applying power
1064 */
1065 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1066 mdelay(10);
1052} 1067}
1053 1068
1054/*****************************************************************************\ 1069/*****************************************************************************\
@@ -1374,6 +1389,35 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1374 sdhci_finish_command(host); 1389 sdhci_finish_command(host);
1375} 1390}
1376 1391
1392#ifdef DEBUG
1393static void sdhci_show_adma_error(struct sdhci_host *host)
1394{
1395 const char *name = mmc_hostname(host->mmc);
1396 u8 *desc = host->adma_desc;
1397 __le32 *dma;
1398 __le16 *len;
1399 u8 attr;
1400
1401 sdhci_dumpregs(host);
1402
1403 while (true) {
1404 dma = (__le32 *)(desc + 4);
1405 len = (__le16 *)(desc + 2);
1406 attr = *desc;
1407
1408 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1409 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1410
1411 desc += 8;
1412
1413 if (attr & 2)
1414 break;
1415 }
1416}
1417#else
1418static void sdhci_show_adma_error(struct sdhci_host *host) { }
1419#endif
1420
1377static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 1421static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1378{ 1422{
1379 BUG_ON(intmask == 0); 1423 BUG_ON(intmask == 0);
@@ -1403,8 +1447,11 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1403 host->data->error = -ETIMEDOUT; 1447 host->data->error = -ETIMEDOUT;
1404 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1448 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1405 host->data->error = -EILSEQ; 1449 host->data->error = -EILSEQ;
1406 else if (intmask & SDHCI_INT_ADMA_ERROR) 1450 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1451 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1452 sdhci_show_adma_error(host);
1407 host->data->error = -EIO; 1453 host->data->error = -EIO;
1454 }
1408 1455
1409 if (host->data->error) 1456 if (host->data->error)
1410 sdhci_finish_data(host); 1457 sdhci_finish_data(host);
@@ -1721,7 +1768,10 @@ int sdhci_add_host(struct sdhci_host *host)
1721 mmc->ops = &sdhci_ops; 1768 mmc->ops = &sdhci_ops;
1722 mmc->f_min = host->max_clk / 256; 1769 mmc->f_min = host->max_clk / 256;
1723 mmc->f_max = host->max_clk; 1770 mmc->f_max = host->max_clk;
1724 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1771 mmc->caps = MMC_CAP_SDIO_IRQ;
1772
1773 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1774 mmc->caps |= MMC_CAP_4_BIT_DATA;
1725 1775
1726 if (caps & SDHCI_CAN_DO_HISPD) 1776 if (caps & SDHCI_CAN_DO_HISPD)
1727 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1777 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
@@ -1794,7 +1844,7 @@ int sdhci_add_host(struct sdhci_host *host)
1794 /* 1844 /*
1795 * Maximum block count. 1845 * Maximum block count.
1796 */ 1846 */
1797 mmc->max_blk_count = 65535; 1847 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1798 1848
1799 /* 1849 /*
1800 * Init tasklets. 1850 * Init tasklets.
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 65c6f996bbd3..831ddf7dcb49 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -226,6 +226,12 @@ struct sdhci_host {
226#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19) 226#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
227/* Controller has to be forced to use block size of 2048 bytes */ 227/* Controller has to be forced to use block size of 2048 bytes */
228#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 228#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
229/* Controller cannot do multi-block transfers */
230#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
231/* Controller can only handle 1-bit data transfers */
232#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
233/* Controller needs 10ms delay between applying power and clock */
234#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
229 235
230 int irq; /* Device IRQ */ 236 int irq; /* Device IRQ */
231 void __iomem * ioaddr; /* Mapped address */ 237 void __iomem * ioaddr; /* Mapped address */
@@ -255,7 +261,7 @@ struct sdhci_host {
255 unsigned int timeout_clk; /* Timeout freq (KHz) */ 261 unsigned int timeout_clk; /* Timeout freq (KHz) */
256 262
257 unsigned int clock; /* Current clock (MHz) */ 263 unsigned int clock; /* Current clock (MHz) */
258 unsigned short power; /* Current voltage */ 264 u8 pwr; /* Current voltage */
259 265
260 struct mmc_request *mrq; /* Current request */ 266 struct mmc_request *mrq; /* Current request */
261 struct mmc_command *cmd; /* Current command */ 267 struct mmc_command *cmd; /* Current command */
diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
index 63fbd5b7d312..91991b460c45 100644
--- a/drivers/mmc/host/tmio_mmc.c
+++ b/drivers/mmc/host/tmio_mmc.c
@@ -10,7 +10,7 @@
10 * 10 *
11 * Driver for the MMC / SD / SDIO cell found in: 11 * Driver for the MMC / SD / SDIO cell found in:
12 * 12 *
13 * TC6393XB TC6391XB TC6387XB T7L66XB 13 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
14 * 14 *
15 * This driver draws mainly on scattered spec sheets, Reverse engineering 15 * This driver draws mainly on scattered spec sheets, Reverse engineering
16 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit 16 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
@@ -35,69 +35,47 @@
35 35
36#include "tmio_mmc.h" 36#include "tmio_mmc.h"
37 37
38/*
39 * Fixme - documentation conflicts on what the clock values are for the
40 * various dividers.
41 * One document I have says that its a divisor of a 24MHz clock, another 33.
42 * This probably depends on HCLK for a given platform, so we may need to
43 * require HCLK be passed to us from the MFD core.
44 *
45 */
46
47static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock) 38static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
48{ 39{
49 void __iomem *cnf = host->cnf;
50 void __iomem *ctl = host->ctl;
51 u32 clk = 0, clock; 40 u32 clk = 0, clock;
52 41
53 if (new_clock) { 42 if (new_clock) {
54 for (clock = 46875, clk = 0x100; new_clock >= (clock<<1); ) { 43 for (clock = host->mmc->f_min, clk = 0x80000080;
44 new_clock >= (clock<<1); clk >>= 1)
55 clock <<= 1; 45 clock <<= 1;
56 clk >>= 1;
57 }
58 if (clk & 0x1)
59 clk = 0x20000;
60
61 clk >>= 2;
62 tmio_iowrite8((clk & 0x8000) ? 0 : 1, cnf + CNF_SD_CLK_MODE);
63 clk |= 0x100; 46 clk |= 0x100;
64 } 47 }
65 48
66 tmio_iowrite16(clk, ctl + CTL_SD_CARD_CLK_CTL); 49 sd_config_write8(host, CNF_SD_CLK_MODE, clk >> 22);
50 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
67} 51}
68 52
69static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) 53static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
70{ 54{
71 void __iomem *ctl = host->ctl; 55 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
72
73 tmio_iowrite16(0x0000, ctl + CTL_CLK_AND_WAIT_CTL);
74 msleep(10); 56 msleep(10);
75 tmio_iowrite16(tmio_ioread16(ctl + CTL_SD_CARD_CLK_CTL) & ~0x0100, 57 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
76 ctl + CTL_SD_CARD_CLK_CTL); 58 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
77 msleep(10); 59 msleep(10);
78} 60}
79 61
80static void tmio_mmc_clk_start(struct tmio_mmc_host *host) 62static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
81{ 63{
82 void __iomem *ctl = host->ctl; 64 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
83 65 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
84 tmio_iowrite16(tmio_ioread16(ctl + CTL_SD_CARD_CLK_CTL) | 0x0100,
85 ctl + CTL_SD_CARD_CLK_CTL);
86 msleep(10); 66 msleep(10);
87 tmio_iowrite16(0x0100, ctl + CTL_CLK_AND_WAIT_CTL); 67 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
88 msleep(10); 68 msleep(10);
89} 69}
90 70
91static void reset(struct tmio_mmc_host *host) 71static void reset(struct tmio_mmc_host *host)
92{ 72{
93 void __iomem *ctl = host->ctl;
94
95 /* FIXME - should we set stop clock reg here */ 73 /* FIXME - should we set stop clock reg here */
96 tmio_iowrite16(0x0000, ctl + CTL_RESET_SD); 74 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
97 tmio_iowrite16(0x0000, ctl + CTL_RESET_SDIO); 75 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
98 msleep(10); 76 msleep(10);
99 tmio_iowrite16(0x0001, ctl + CTL_RESET_SD); 77 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
100 tmio_iowrite16(0x0001, ctl + CTL_RESET_SDIO); 78 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
101 msleep(10); 79 msleep(10);
102} 80}
103 81
@@ -129,13 +107,12 @@ tmio_mmc_finish_request(struct tmio_mmc_host *host)
129static int 107static int
130tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd) 108tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
131{ 109{
132 void __iomem *ctl = host->ctl;
133 struct mmc_data *data = host->data; 110 struct mmc_data *data = host->data;
134 int c = cmd->opcode; 111 int c = cmd->opcode;
135 112
136 /* Command 12 is handled by hardware */ 113 /* Command 12 is handled by hardware */
137 if (cmd->opcode == 12 && !cmd->arg) { 114 if (cmd->opcode == 12 && !cmd->arg) {
138 tmio_iowrite16(0x001, ctl + CTL_STOP_INTERNAL_ACTION); 115 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
139 return 0; 116 return 0;
140 } 117 }
141 118
@@ -160,18 +137,18 @@ tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
160 if (data) { 137 if (data) {
161 c |= DATA_PRESENT; 138 c |= DATA_PRESENT;
162 if (data->blocks > 1) { 139 if (data->blocks > 1) {
163 tmio_iowrite16(0x100, ctl + CTL_STOP_INTERNAL_ACTION); 140 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
164 c |= TRANSFER_MULTI; 141 c |= TRANSFER_MULTI;
165 } 142 }
166 if (data->flags & MMC_DATA_READ) 143 if (data->flags & MMC_DATA_READ)
167 c |= TRANSFER_READ; 144 c |= TRANSFER_READ;
168 } 145 }
169 146
170 enable_mmc_irqs(ctl, TMIO_MASK_CMD); 147 enable_mmc_irqs(host, TMIO_MASK_CMD);
171 148
172 /* Fire off the command */ 149 /* Fire off the command */
173 tmio_iowrite32(cmd->arg, ctl + CTL_ARG_REG); 150 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
174 tmio_iowrite16(c, ctl + CTL_SD_CMD); 151 sd_ctrl_write16(host, CTL_SD_CMD, c);
175 152
176 return 0; 153 return 0;
177} 154}
@@ -183,7 +160,6 @@ tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
183 */ 160 */
184static inline void tmio_mmc_pio_irq(struct tmio_mmc_host *host) 161static inline void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
185{ 162{
186 void __iomem *ctl = host->ctl;
187 struct mmc_data *data = host->data; 163 struct mmc_data *data = host->data;
188 unsigned short *buf; 164 unsigned short *buf;
189 unsigned int count; 165 unsigned int count;
@@ -206,9 +182,9 @@ static inline void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
206 182
207 /* Transfer the data */ 183 /* Transfer the data */
208 if (data->flags & MMC_DATA_READ) 184 if (data->flags & MMC_DATA_READ)
209 tmio_ioread16_rep(ctl + CTL_SD_DATA_PORT, buf, count >> 1); 185 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
210 else 186 else
211 tmio_iowrite16_rep(ctl + CTL_SD_DATA_PORT, buf, count >> 1); 187 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
212 188
213 host->sg_off += count; 189 host->sg_off += count;
214 190
@@ -222,7 +198,6 @@ static inline void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
222 198
223static inline void tmio_mmc_data_irq(struct tmio_mmc_host *host) 199static inline void tmio_mmc_data_irq(struct tmio_mmc_host *host)
224{ 200{
225 void __iomem *ctl = host->ctl;
226 struct mmc_data *data = host->data; 201 struct mmc_data *data = host->data;
227 struct mmc_command *stop; 202 struct mmc_command *stop;
228 203
@@ -251,13 +226,13 @@ static inline void tmio_mmc_data_irq(struct tmio_mmc_host *host)
251 */ 226 */
252 227
253 if (data->flags & MMC_DATA_READ) 228 if (data->flags & MMC_DATA_READ)
254 disable_mmc_irqs(ctl, TMIO_MASK_READOP); 229 disable_mmc_irqs(host, TMIO_MASK_READOP);
255 else 230 else
256 disable_mmc_irqs(ctl, TMIO_MASK_WRITEOP); 231 disable_mmc_irqs(host, TMIO_MASK_WRITEOP);
257 232
258 if (stop) { 233 if (stop) {
259 if (stop->opcode == 12 && !stop->arg) 234 if (stop->opcode == 12 && !stop->arg)
260 tmio_iowrite16(0x000, ctl + CTL_STOP_INTERNAL_ACTION); 235 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
261 else 236 else
262 BUG(); 237 BUG();
263 } 238 }
@@ -268,9 +243,8 @@ static inline void tmio_mmc_data_irq(struct tmio_mmc_host *host)
268static inline void tmio_mmc_cmd_irq(struct tmio_mmc_host *host, 243static inline void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
269 unsigned int stat) 244 unsigned int stat)
270{ 245{
271 void __iomem *ctl = host->ctl, *addr;
272 struct mmc_command *cmd = host->cmd; 246 struct mmc_command *cmd = host->cmd;
273 int i; 247 int i, addr;
274 248
275 if (!host->cmd) { 249 if (!host->cmd) {
276 pr_debug("Spurious CMD irq\n"); 250 pr_debug("Spurious CMD irq\n");
@@ -284,8 +258,8 @@ static inline void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
284 * modify the order of the response for short response command types. 258 * modify the order of the response for short response command types.
285 */ 259 */
286 260
287 for (i = 3, addr = ctl + CTL_RESPONSE ; i >= 0 ; i--, addr += 4) 261 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
288 cmd->resp[i] = tmio_ioread32(addr); 262 cmd->resp[i] = sd_ctrl_read32(host, addr);
289 263
290 if (cmd->flags & MMC_RSP_136) { 264 if (cmd->flags & MMC_RSP_136) {
291 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24); 265 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
@@ -307,9 +281,9 @@ static inline void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
307 */ 281 */
308 if (host->data && !cmd->error) { 282 if (host->data && !cmd->error) {
309 if (host->data->flags & MMC_DATA_READ) 283 if (host->data->flags & MMC_DATA_READ)
310 enable_mmc_irqs(ctl, TMIO_MASK_READOP); 284 enable_mmc_irqs(host, TMIO_MASK_READOP);
311 else 285 else
312 enable_mmc_irqs(ctl, TMIO_MASK_WRITEOP); 286 enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
313 } else { 287 } else {
314 tmio_mmc_finish_request(host); 288 tmio_mmc_finish_request(host);
315 } 289 }
@@ -321,20 +295,19 @@ static inline void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
321static irqreturn_t tmio_mmc_irq(int irq, void *devid) 295static irqreturn_t tmio_mmc_irq(int irq, void *devid)
322{ 296{
323 struct tmio_mmc_host *host = devid; 297 struct tmio_mmc_host *host = devid;
324 void __iomem *ctl = host->ctl;
325 unsigned int ireg, irq_mask, status; 298 unsigned int ireg, irq_mask, status;
326 299
327 pr_debug("MMC IRQ begin\n"); 300 pr_debug("MMC IRQ begin\n");
328 301
329 status = tmio_ioread32(ctl + CTL_STATUS); 302 status = sd_ctrl_read32(host, CTL_STATUS);
330 irq_mask = tmio_ioread32(ctl + CTL_IRQ_MASK); 303 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
331 ireg = status & TMIO_MASK_IRQ & ~irq_mask; 304 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
332 305
333 pr_debug_status(status); 306 pr_debug_status(status);
334 pr_debug_status(ireg); 307 pr_debug_status(ireg);
335 308
336 if (!ireg) { 309 if (!ireg) {
337 disable_mmc_irqs(ctl, status & ~irq_mask); 310 disable_mmc_irqs(host, status & ~irq_mask);
338 311
339 pr_debug("tmio_mmc: Spurious irq, disabling! " 312 pr_debug("tmio_mmc: Spurious irq, disabling! "
340 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg); 313 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg);
@@ -346,7 +319,7 @@ static irqreturn_t tmio_mmc_irq(int irq, void *devid)
346 while (ireg) { 319 while (ireg) {
347 /* Card insert / remove attempts */ 320 /* Card insert / remove attempts */
348 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) { 321 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
349 ack_mmc_irqs(ctl, TMIO_STAT_CARD_INSERT | 322 ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
350 TMIO_STAT_CARD_REMOVE); 323 TMIO_STAT_CARD_REMOVE);
351 mmc_detect_change(host->mmc, 0); 324 mmc_detect_change(host->mmc, 0);
352 } 325 }
@@ -358,25 +331,25 @@ static irqreturn_t tmio_mmc_irq(int irq, void *devid)
358 331
359 /* Command completion */ 332 /* Command completion */
360 if (ireg & TMIO_MASK_CMD) { 333 if (ireg & TMIO_MASK_CMD) {
361 ack_mmc_irqs(ctl, TMIO_MASK_CMD); 334 ack_mmc_irqs(host, TMIO_MASK_CMD);
362 tmio_mmc_cmd_irq(host, status); 335 tmio_mmc_cmd_irq(host, status);
363 } 336 }
364 337
365 /* Data transfer */ 338 /* Data transfer */
366 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) { 339 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
367 ack_mmc_irqs(ctl, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ); 340 ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
368 tmio_mmc_pio_irq(host); 341 tmio_mmc_pio_irq(host);
369 } 342 }
370 343
371 /* Data transfer completion */ 344 /* Data transfer completion */
372 if (ireg & TMIO_STAT_DATAEND) { 345 if (ireg & TMIO_STAT_DATAEND) {
373 ack_mmc_irqs(ctl, TMIO_STAT_DATAEND); 346 ack_mmc_irqs(host, TMIO_STAT_DATAEND);
374 tmio_mmc_data_irq(host); 347 tmio_mmc_data_irq(host);
375 } 348 }
376 349
377 /* Check status - keep going until we've handled it all */ 350 /* Check status - keep going until we've handled it all */
378 status = tmio_ioread32(ctl + CTL_STATUS); 351 status = sd_ctrl_read32(host, CTL_STATUS);
379 irq_mask = tmio_ioread32(ctl + CTL_IRQ_MASK); 352 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
380 ireg = status & TMIO_MASK_IRQ & ~irq_mask; 353 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
381 354
382 pr_debug("Status at end of loop: %08x\n", status); 355 pr_debug("Status at end of loop: %08x\n", status);
@@ -391,8 +364,6 @@ out:
391static int tmio_mmc_start_data(struct tmio_mmc_host *host, 364static int tmio_mmc_start_data(struct tmio_mmc_host *host,
392 struct mmc_data *data) 365 struct mmc_data *data)
393{ 366{
394 void __iomem *ctl = host->ctl;
395
396 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n", 367 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
397 data->blksz, data->blocks); 368 data->blksz, data->blocks);
398 369
@@ -407,8 +378,8 @@ static int tmio_mmc_start_data(struct tmio_mmc_host *host,
407 host->data = data; 378 host->data = data;
408 379
409 /* Set transfer length / blocksize */ 380 /* Set transfer length / blocksize */
410 tmio_iowrite16(data->blksz, ctl + CTL_SD_XFER_LEN); 381 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
411 tmio_iowrite16(data->blocks, ctl + CTL_XFER_BLK_COUNT); 382 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
412 383
413 return 0; 384 return 0;
414} 385}
@@ -449,8 +420,6 @@ fail:
449static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 420static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
450{ 421{
451 struct tmio_mmc_host *host = mmc_priv(mmc); 422 struct tmio_mmc_host *host = mmc_priv(mmc);
452 void __iomem *cnf = host->cnf;
453 void __iomem *ctl = host->ctl;
454 423
455 if (ios->clock) 424 if (ios->clock)
456 tmio_mmc_set_clock(host, ios->clock); 425 tmio_mmc_set_clock(host, ios->clock);
@@ -458,12 +427,12 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
458 /* Power sequence - OFF -> ON -> UP */ 427 /* Power sequence - OFF -> ON -> UP */
459 switch (ios->power_mode) { 428 switch (ios->power_mode) {
460 case MMC_POWER_OFF: /* power down SD bus */ 429 case MMC_POWER_OFF: /* power down SD bus */
461 tmio_iowrite8(0x00, cnf + CNF_PWR_CTL_2); 430 sd_config_write8(host, CNF_PWR_CTL_2, 0x00);
462 tmio_mmc_clk_stop(host); 431 tmio_mmc_clk_stop(host);
463 break; 432 break;
464 case MMC_POWER_ON: /* power up SD bus */ 433 case MMC_POWER_ON: /* power up SD bus */
465 434
466 tmio_iowrite8(0x02, cnf + CNF_PWR_CTL_2); 435 sd_config_write8(host, CNF_PWR_CTL_2, 0x02);
467 break; 436 break;
468 case MMC_POWER_UP: /* start bus clock */ 437 case MMC_POWER_UP: /* start bus clock */
469 tmio_mmc_clk_start(host); 438 tmio_mmc_clk_start(host);
@@ -472,10 +441,10 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
472 441
473 switch (ios->bus_width) { 442 switch (ios->bus_width) {
474 case MMC_BUS_WIDTH_1: 443 case MMC_BUS_WIDTH_1:
475 tmio_iowrite16(0x80e0, ctl + CTL_SD_MEM_CARD_OPT); 444 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
476 break; 445 break;
477 case MMC_BUS_WIDTH_4: 446 case MMC_BUS_WIDTH_4:
478 tmio_iowrite16(0x00e0, ctl + CTL_SD_MEM_CARD_OPT); 447 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
479 break; 448 break;
480 } 449 }
481 450
@@ -486,9 +455,8 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
486static int tmio_mmc_get_ro(struct mmc_host *mmc) 455static int tmio_mmc_get_ro(struct mmc_host *mmc)
487{ 456{
488 struct tmio_mmc_host *host = mmc_priv(mmc); 457 struct tmio_mmc_host *host = mmc_priv(mmc);
489 void __iomem *ctl = host->ctl;
490 458
491 return (tmio_ioread16(ctl + CTL_STATUS) & TMIO_STAT_WRPROTECT) ? 0 : 1; 459 return (sd_ctrl_read16(host, CTL_STATUS) & TMIO_STAT_WRPROTECT) ? 0 : 1;
492} 460}
493 461
494static struct mmc_host_ops tmio_mmc_ops = { 462static struct mmc_host_ops tmio_mmc_ops = {
@@ -518,13 +486,8 @@ static int tmio_mmc_resume(struct platform_device *dev)
518 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; 486 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
519 struct mmc_host *mmc = platform_get_drvdata(dev); 487 struct mmc_host *mmc = platform_get_drvdata(dev);
520 struct tmio_mmc_host *host = mmc_priv(mmc); 488 struct tmio_mmc_host *host = mmc_priv(mmc);
521 void __iomem *cnf = host->cnf;
522 int ret = 0; 489 int ret = 0;
523 490
524 /* Enable the MMC/SD Control registers */
525 tmio_iowrite16(SDCREN, cnf + CNF_CMD);
526 tmio_iowrite32(dev->resource[0].start & 0xfffe, cnf + CNF_CTL_BASE);
527
528 /* Tell the MFD core we are ready to be enabled */ 491 /* Tell the MFD core we are ready to be enabled */
529 if (cell->enable) { 492 if (cell->enable) {
530 ret = cell->enable(dev); 493 ret = cell->enable(dev);
@@ -532,6 +495,11 @@ static int tmio_mmc_resume(struct platform_device *dev)
532 goto out; 495 goto out;
533 } 496 }
534 497
498 /* Enable the MMC/SD Control registers */
499 sd_config_write16(host, CNF_CMD, SDCREN);
500 sd_config_write32(host, CNF_CTL_BASE,
501 (dev->resource[0].start >> host->bus_shift) & 0xfffe);
502
535 mmc_resume_host(mmc); 503 mmc_resume_host(mmc);
536 504
537out: 505out:
@@ -545,20 +513,25 @@ out:
545static int __devinit tmio_mmc_probe(struct platform_device *dev) 513static int __devinit tmio_mmc_probe(struct platform_device *dev)
546{ 514{
547 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; 515 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
516 struct tmio_mmc_data *pdata;
548 struct resource *res_ctl, *res_cnf; 517 struct resource *res_ctl, *res_cnf;
549 struct tmio_mmc_host *host; 518 struct tmio_mmc_host *host;
550 struct mmc_host *mmc; 519 struct mmc_host *mmc;
551 int ret = -ENOMEM; 520 int ret = -EINVAL;
552 521
553 if (dev->num_resources != 3) 522 if (dev->num_resources != 3)
554 goto out; 523 goto out;
555 524
556 res_ctl = platform_get_resource(dev, IORESOURCE_MEM, 0); 525 res_ctl = platform_get_resource(dev, IORESOURCE_MEM, 0);
557 res_cnf = platform_get_resource(dev, IORESOURCE_MEM, 1); 526 res_cnf = platform_get_resource(dev, IORESOURCE_MEM, 1);
558 if (!res_ctl || !res_cnf) { 527 if (!res_ctl || !res_cnf)
559 ret = -EINVAL;
560 goto out; 528 goto out;
561 } 529
530 pdata = cell->driver_data;
531 if (!pdata || !pdata->hclk)
532 goto out;
533
534 ret = -ENOMEM;
562 535
563 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev); 536 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev);
564 if (!mmc) 537 if (!mmc)
@@ -568,6 +541,9 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
568 host->mmc = mmc; 541 host->mmc = mmc;
569 platform_set_drvdata(dev, mmc); 542 platform_set_drvdata(dev, mmc);
570 543
544 /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
545 host->bus_shift = resource_size(res_ctl) >> 10;
546
571 host->ctl = ioremap(res_ctl->start, resource_size(res_ctl)); 547 host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
572 if (!host->ctl) 548 if (!host->ctl)
573 goto host_free; 549 goto host_free;
@@ -578,15 +554,10 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
578 554
579 mmc->ops = &tmio_mmc_ops; 555 mmc->ops = &tmio_mmc_ops;
580 mmc->caps = MMC_CAP_4_BIT_DATA; 556 mmc->caps = MMC_CAP_4_BIT_DATA;
581 mmc->f_min = 46875; /* 24000000 / 512 */ 557 mmc->f_max = pdata->hclk;
582 mmc->f_max = 24000000; 558 mmc->f_min = mmc->f_max / 512;
583 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 559 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
584 560
585 /* Enable the MMC/SD Control registers */
586 tmio_iowrite16(SDCREN, host->cnf + CNF_CMD);
587 tmio_iowrite32(dev->resource[0].start & 0xfffe,
588 host->cnf + CNF_CTL_BASE);
589
590 /* Tell the MFD core we are ready to be enabled */ 561 /* Tell the MFD core we are ready to be enabled */
591 if (cell->enable) { 562 if (cell->enable) {
592 ret = cell->enable(dev); 563 ret = cell->enable(dev);
@@ -594,14 +565,19 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
594 goto unmap_cnf; 565 goto unmap_cnf;
595 } 566 }
596 567
568 /* Enable the MMC/SD Control registers */
569 sd_config_write16(host, CNF_CMD, SDCREN);
570 sd_config_write32(host, CNF_CTL_BASE,
571 (dev->resource[0].start >> host->bus_shift) & 0xfffe);
572
597 /* Disable SD power during suspend */ 573 /* Disable SD power during suspend */
598 tmio_iowrite8(0x01, host->cnf + CNF_PWR_CTL_3); 574 sd_config_write8(host, CNF_PWR_CTL_3, 0x01);
599 575
600 /* The below is required but why? FIXME */ 576 /* The below is required but why? FIXME */
601 tmio_iowrite8(0x1f, host->cnf + CNF_STOP_CLK_CTL); 577 sd_config_write8(host, CNF_STOP_CLK_CTL, 0x1f);
602 578
603 /* Power down SD bus*/ 579 /* Power down SD bus*/
604 tmio_iowrite8(0x0, host->cnf + CNF_PWR_CTL_2); 580 sd_config_write8(host, CNF_PWR_CTL_2, 0x00);
605 581
606 tmio_mmc_clk_stop(host); 582 tmio_mmc_clk_stop(host);
607 reset(host); 583 reset(host);
@@ -612,22 +588,20 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
612 else 588 else
613 goto unmap_cnf; 589 goto unmap_cnf;
614 590
615 disable_mmc_irqs(host->ctl, TMIO_MASK_ALL); 591 disable_mmc_irqs(host, TMIO_MASK_ALL);
616 592
617 ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED, "tmio-mmc", 593 ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED |
618 host); 594 IRQF_TRIGGER_FALLING, "tmio-mmc", host);
619 if (ret) 595 if (ret)
620 goto unmap_cnf; 596 goto unmap_cnf;
621 597
622 set_irq_type(host->irq, IRQ_TYPE_EDGE_FALLING);
623
624 mmc_add_host(mmc); 598 mmc_add_host(mmc);
625 599
626 printk(KERN_INFO "%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc), 600 printk(KERN_INFO "%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc),
627 (unsigned long)host->ctl, host->irq); 601 (unsigned long)host->ctl, host->irq);
628 602
629 /* Unmask the IRQs we want to know about */ 603 /* Unmask the IRQs we want to know about */
630 enable_mmc_irqs(host->ctl, TMIO_MASK_IRQ); 604 enable_mmc_irqs(host, TMIO_MASK_IRQ);
631 605
632 return 0; 606 return 0;
633 607
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index 9c831ab2ece6..9fa998594974 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -83,34 +83,36 @@
83 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) 83 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
84#define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD) 84#define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
85 85
86#define enable_mmc_irqs(ctl, i) \ 86
87#define enable_mmc_irqs(host, i) \
87 do { \ 88 do { \
88 u32 mask;\ 89 u32 mask;\
89 mask = tmio_ioread32((ctl) + CTL_IRQ_MASK); \ 90 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \
90 mask &= ~((i) & TMIO_MASK_IRQ); \ 91 mask &= ~((i) & TMIO_MASK_IRQ); \
91 tmio_iowrite32(mask, (ctl) + CTL_IRQ_MASK); \ 92 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
92 } while (0) 93 } while (0)
93 94
94#define disable_mmc_irqs(ctl, i) \ 95#define disable_mmc_irqs(host, i) \
95 do { \ 96 do { \
96 u32 mask;\ 97 u32 mask;\
97 mask = tmio_ioread32((ctl) + CTL_IRQ_MASK); \ 98 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \
98 mask |= ((i) & TMIO_MASK_IRQ); \ 99 mask |= ((i) & TMIO_MASK_IRQ); \
99 tmio_iowrite32(mask, (ctl) + CTL_IRQ_MASK); \ 100 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
100 } while (0) 101 } while (0)
101 102
102#define ack_mmc_irqs(ctl, i) \ 103#define ack_mmc_irqs(host, i) \
103 do { \ 104 do { \
104 u32 mask;\ 105 u32 mask;\
105 mask = tmio_ioread32((ctl) + CTL_STATUS); \ 106 mask = sd_ctrl_read32((host), CTL_STATUS); \
106 mask &= ~((i) & TMIO_MASK_IRQ); \ 107 mask &= ~((i) & TMIO_MASK_IRQ); \
107 tmio_iowrite32(mask, (ctl) + CTL_STATUS); \ 108 sd_ctrl_write32((host), CTL_STATUS, mask); \
108 } while (0) 109 } while (0)
109 110
110 111
111struct tmio_mmc_host { 112struct tmio_mmc_host {
112 void __iomem *cnf; 113 void __iomem *cnf;
113 void __iomem *ctl; 114 void __iomem *ctl;
115 unsigned long bus_shift;
114 struct mmc_command *cmd; 116 struct mmc_command *cmd;
115 struct mmc_request *mrq; 117 struct mmc_request *mrq;
116 struct mmc_data *data; 118 struct mmc_data *data;
@@ -123,6 +125,63 @@ struct tmio_mmc_host {
123 unsigned int sg_off; 125 unsigned int sg_off;
124}; 126};
125 127
128#include <linux/io.h>
129
130static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
131{
132 return readw(host->ctl + (addr << host->bus_shift));
133}
134
135static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
136 u16 *buf, int count)
137{
138 readsw(host->ctl + (addr << host->bus_shift), buf, count);
139}
140
141static inline u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)
142{
143 return readw(host->ctl + (addr << host->bus_shift)) |
144 readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
145}
146
147static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
148 u16 val)
149{
150 writew(val, host->ctl + (addr << host->bus_shift));
151}
152
153static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
154 u16 *buf, int count)
155{
156 writesw(host->ctl + (addr << host->bus_shift), buf, count);
157}
158
159static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr,
160 u32 val)
161{
162 writew(val, host->ctl + (addr << host->bus_shift));
163 writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
164}
165
166static inline void sd_config_write8(struct tmio_mmc_host *host, int addr,
167 u8 val)
168{
169 writeb(val, host->cnf + (addr << host->bus_shift));
170}
171
172static inline void sd_config_write16(struct tmio_mmc_host *host, int addr,
173 u16 val)
174{
175 writew(val, host->cnf + (addr << host->bus_shift));
176}
177
178static inline void sd_config_write32(struct tmio_mmc_host *host, int addr,
179 u32 val)
180{
181 writew(val, host->cnf + (addr << host->bus_shift));
182 writew(val >> 16, host->cnf + ((addr + 2) << host->bus_shift));
183}
184
126#include <linux/scatterlist.h> 185#include <linux/scatterlist.h>
127#include <linux/blkdev.h> 186#include <linux/blkdev.h>
128 187
diff --git a/drivers/mmc/host/via-sdmmc.c b/drivers/mmc/host/via-sdmmc.c
new file mode 100644
index 000000000000..632858a94376
--- /dev/null
+++ b/drivers/mmc/host/via-sdmmc.c
@@ -0,0 +1,1362 @@
1/*
2 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
3 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 */
10
11#include <linux/pci.h>
12#include <linux/dma-mapping.h>
13#include <linux/highmem.h>
14#include <linux/delay.h>
15
16#include <linux/mmc/host.h>
17
18#define DRV_NAME "via_sdmmc"
19
20#define PCI_DEVICE_ID_VIA_9530 0x9530
21
22#define VIA_CRDR_SDC_OFF 0x200
23#define VIA_CRDR_DDMA_OFF 0x400
24#define VIA_CRDR_PCICTRL_OFF 0x600
25
26#define VIA_CRDR_MIN_CLOCK 375000
27#define VIA_CRDR_MAX_CLOCK 48000000
28
29/*
30 * PCI registers
31 */
32
33#define VIA_CRDR_PCI_WORK_MODE 0x40
34#define VIA_CRDR_PCI_DBG_MODE 0x41
35
36/*
37 * SDC MMIO Registers
38 */
39
40#define VIA_CRDR_SDCTRL 0x0
41#define VIA_CRDR_SDCTRL_START 0x01
42#define VIA_CRDR_SDCTRL_WRITE 0x04
43#define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
44#define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
45#define VIA_CRDR_SDCTRL_MULTI_WR 0x30
46#define VIA_CRDR_SDCTRL_MULTI_RD 0x40
47#define VIA_CRDR_SDCTRL_STOP 0x70
48
49#define VIA_CRDR_SDCTRL_RSP_NONE 0x0
50#define VIA_CRDR_SDCTRL_RSP_R1 0x10000
51#define VIA_CRDR_SDCTRL_RSP_R2 0x20000
52#define VIA_CRDR_SDCTRL_RSP_R3 0x30000
53#define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
54
55#define VIA_CRDR_SDCARG 0x4
56
57#define VIA_CRDR_SDBUSMODE 0x8
58#define VIA_CRDR_SDMODE_4BIT 0x02
59#define VIA_CRDR_SDMODE_CLK_ON 0x40
60
61#define VIA_CRDR_SDBLKLEN 0xc
62/*
63 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
64 * Bit 11 - Bit 13 : Reserved.
65 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
66 * INTEN : Enable SD host interrupt.
67 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
68 */
69#define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
70#define VIA_CRDR_SDBLKLEN_INTEN 0x8000
71#define VIA_CRDR_MAX_BLOCK_COUNT 65536
72#define VIA_CRDR_MAX_BLOCK_LENGTH 2048
73
74#define VIA_CRDR_SDRESP0 0x10
75#define VIA_CRDR_SDRESP1 0x14
76#define VIA_CRDR_SDRESP2 0x18
77#define VIA_CRDR_SDRESP3 0x1c
78
79#define VIA_CRDR_SDCURBLKCNT 0x20
80
81#define VIA_CRDR_SDINTMASK 0x24
82/*
83 * MBDIE : Multiple Blocks transfer Done Interrupt Enable
84 * BDDIE : Block Data transfer Done Interrupt Enable
85 * CIRIE : Card Insertion or Removal Interrupt Enable
86 * CRDIE : Command-Response transfer Done Interrupt Enable
87 * CRTOIE : Command-Response response TimeOut Interrupt Enable
88 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
89 * DTIE : Data access Timeout Interrupt Enable
90 * SCIE : reSponse CRC error Interrupt Enable
91 * RCIE : Read data CRC error Interrupt Enable
92 * WCIE : Write data CRC error Interrupt Enable
93 */
94#define VIA_CRDR_SDINTMASK_MBDIE 0x10
95#define VIA_CRDR_SDINTMASK_BDDIE 0x20
96#define VIA_CRDR_SDINTMASK_CIRIE 0x80
97#define VIA_CRDR_SDINTMASK_CRDIE 0x200
98#define VIA_CRDR_SDINTMASK_CRTOIE 0x400
99#define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
100#define VIA_CRDR_SDINTMASK_DTIE 0x1000
101#define VIA_CRDR_SDINTMASK_SCIE 0x2000
102#define VIA_CRDR_SDINTMASK_RCIE 0x4000
103#define VIA_CRDR_SDINTMASK_WCIE 0x8000
104
105#define VIA_CRDR_SDACTIVE_INTMASK \
106 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
107 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
108 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
109 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
110
111#define VIA_CRDR_SDSTATUS 0x28
112/*
113 * CECC : Reserved
114 * WP : SD card Write Protect status
115 * SLOTD : Reserved
116 * SLOTG : SD SLOT status(Gpi pin status)
117 * MBD : Multiple Blocks transfer Done interrupt status
118 * BDD : Block Data transfer Done interrupt status
119 * CD : Reserved
120 * CIR : Card Insertion or Removal interrupt detected on GPI pin
121 * IO : Reserved
122 * CRD : Command-Response transfer Done interrupt status
123 * CRTO : Command-Response response TimeOut interrupt status
124 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
125 * DT : Data access Timeout interrupt status
126 * SC : reSponse CRC error interrupt status
127 * RC : Read data CRC error interrupt status
128 * WC : Write data CRC error interrupt status
129 */
130#define VIA_CRDR_SDSTS_CECC 0x01
131#define VIA_CRDR_SDSTS_WP 0x02
132#define VIA_CRDR_SDSTS_SLOTD 0x04
133#define VIA_CRDR_SDSTS_SLOTG 0x08
134#define VIA_CRDR_SDSTS_MBD 0x10
135#define VIA_CRDR_SDSTS_BDD 0x20
136#define VIA_CRDR_SDSTS_CD 0x40
137#define VIA_CRDR_SDSTS_CIR 0x80
138#define VIA_CRDR_SDSTS_IO 0x100
139#define VIA_CRDR_SDSTS_CRD 0x200
140#define VIA_CRDR_SDSTS_CRTO 0x400
141#define VIA_CRDR_SDSTS_ASCRDIE 0x800
142#define VIA_CRDR_SDSTS_DT 0x1000
143#define VIA_CRDR_SDSTS_SC 0x2000
144#define VIA_CRDR_SDSTS_RC 0x4000
145#define VIA_CRDR_SDSTS_WC 0x8000
146
147#define VIA_CRDR_SDSTS_IGN_MASK\
148 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
149#define VIA_CRDR_SDSTS_INT_MASK \
150 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
151 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
152 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
153 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
154#define VIA_CRDR_SDSTS_W1C_MASK \
155 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
156 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
157 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
158 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
159#define VIA_CRDR_SDSTS_CMD_MASK \
160 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
161#define VIA_CRDR_SDSTS_DATA_MASK\
162 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
163 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
164
165#define VIA_CRDR_SDSTATUS2 0x2a
166/*
167 * CFE : Enable SD host automatic Clock FReezing
168 */
169#define VIA_CRDR_SDSTS_CFE 0x80
170
171#define VIA_CRDR_SDRSPTMO 0x2C
172
173#define VIA_CRDR_SDCLKSEL 0x30
174
175#define VIA_CRDR_SDEXTCTRL 0x34
176#define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
177#define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
178#define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
179#define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
180#define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
181#define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
182#define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
183#define VIA_CRDR_SDEXTCTRL_HISPD 0x80
184/* 0x38-0xFF reserved */
185
186/*
187 * Data DMA Control Registers
188 */
189
190#define VIA_CRDR_DMABASEADD 0x0
191#define VIA_CRDR_DMACOUNTER 0x4
192
193#define VIA_CRDR_DMACTRL 0x8
194/*
195 * DIR :Transaction Direction
196 * 0 : From card to memory
197 * 1 : From memory to card
198 */
199#define VIA_CRDR_DMACTRL_DIR 0x100
200#define VIA_CRDR_DMACTRL_ENIRQ 0x10000
201#define VIA_CRDR_DMACTRL_SFTRST 0x1000000
202
203#define VIA_CRDR_DMASTS 0xc
204
205#define VIA_CRDR_DMASTART 0x10
206/*0x14-0xFF reserved*/
207
208/*
209 * PCI Control Registers
210 */
211
212/*0x0 - 0x1 reserved*/
213#define VIA_CRDR_PCICLKGATT 0x2
214/*
215 * SFTRST :
216 * 0 : Soft reset all the controller and it will be de-asserted automatically
217 * 1 : Soft reset is de-asserted
218 */
219#define VIA_CRDR_PCICLKGATT_SFTRST 0x01
220/*
221 * 3V3 : Pad power select
222 * 0 : 1.8V
223 * 1 : 3.3V
224 * NOTE : No mater what the actual value should be, this bit always
225 * read as 0. This is a hardware bug.
226 */
227#define VIA_CRDR_PCICLKGATT_3V3 0x10
228/*
229 * PAD_PWRON : Pad Power on/off select
230 * 0 : Power off
231 * 1 : Power on
232 * NOTE : No mater what the actual value should be, this bit always
233 * read as 0. This is a hardware bug.
234 */
235#define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
236
237#define VIA_CRDR_PCISDCCLK 0x5
238
239#define VIA_CRDR_PCIDMACLK 0x7
240#define VIA_CRDR_PCIDMACLK_SDC 0x2
241
242#define VIA_CRDR_PCIINTCTRL 0x8
243#define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
244
245#define VIA_CRDR_PCIINTSTATUS 0x9
246#define VIA_CRDR_PCIINTSTATUS_SDC 0x04
247
248#define VIA_CRDR_PCITMOCTRL 0xa
249#define VIA_CRDR_PCITMOCTRL_NO 0x0
250#define VIA_CRDR_PCITMOCTRL_32US 0x1
251#define VIA_CRDR_PCITMOCTRL_256US 0x2
252#define VIA_CRDR_PCITMOCTRL_1024US 0x3
253#define VIA_CRDR_PCITMOCTRL_256MS 0x4
254#define VIA_CRDR_PCITMOCTRL_512MS 0x5
255#define VIA_CRDR_PCITMOCTRL_1024MS 0x6
256
257/*0xB-0xFF reserved*/
258
259enum PCI_HOST_CLK_CONTROL {
260 PCI_CLK_375K = 0x03,
261 PCI_CLK_8M = 0x04,
262 PCI_CLK_12M = 0x00,
263 PCI_CLK_16M = 0x05,
264 PCI_CLK_24M = 0x01,
265 PCI_CLK_33M = 0x06,
266 PCI_CLK_48M = 0x02
267};
268
269struct sdhcreg {
270 u32 sdcontrol_reg;
271 u32 sdcmdarg_reg;
272 u32 sdbusmode_reg;
273 u32 sdblklen_reg;
274 u32 sdresp_reg[4];
275 u32 sdcurblkcnt_reg;
276 u32 sdintmask_reg;
277 u32 sdstatus_reg;
278 u32 sdrsptmo_reg;
279 u32 sdclksel_reg;
280 u32 sdextctrl_reg;
281};
282
283struct pcictrlreg {
284 u8 reserve[2];
285 u8 pciclkgat_reg;
286 u8 pcinfcclk_reg;
287 u8 pcimscclk_reg;
288 u8 pcisdclk_reg;
289 u8 pcicaclk_reg;
290 u8 pcidmaclk_reg;
291 u8 pciintctrl_reg;
292 u8 pciintstatus_reg;
293 u8 pcitmoctrl_reg;
294 u8 Resv;
295};
296
297struct via_crdr_mmc_host {
298 struct mmc_host *mmc;
299 struct mmc_request *mrq;
300 struct mmc_command *cmd;
301 struct mmc_data *data;
302
303 void __iomem *mmiobase;
304 void __iomem *sdhc_mmiobase;
305 void __iomem *ddma_mmiobase;
306 void __iomem *pcictrl_mmiobase;
307
308 struct pcictrlreg pm_pcictrl_reg;
309 struct sdhcreg pm_sdhc_reg;
310
311 struct work_struct carddet_work;
312 struct tasklet_struct finish_tasklet;
313
314 struct timer_list timer;
315 spinlock_t lock;
316 u8 power;
317 int reject;
318 unsigned int quirks;
319};
320
321/* some devices need a very long delay for power to stabilize */
322#define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
323
324static struct pci_device_id via_ids[] = {
325 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
327 {0,}
328};
329
330MODULE_DEVICE_TABLE(pci, via_ids);
331
332static void via_print_sdchc(struct via_crdr_mmc_host *host)
333{
334 void __iomem *addrbase = host->sdhc_mmiobase;
335
336 pr_debug("SDC MMIO Registers:\n");
337 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
338 readl(addrbase + VIA_CRDR_SDCTRL),
339 readl(addrbase + VIA_CRDR_SDCARG),
340 readl(addrbase + VIA_CRDR_SDBUSMODE));
341 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
342 readl(addrbase + VIA_CRDR_SDBLKLEN),
343 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
344 readl(addrbase + VIA_CRDR_SDINTMASK));
345 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
346 readl(addrbase + VIA_CRDR_SDSTATUS),
347 readl(addrbase + VIA_CRDR_SDCLKSEL),
348 readl(addrbase + VIA_CRDR_SDEXTCTRL));
349}
350
351static void via_print_pcictrl(struct via_crdr_mmc_host *host)
352{
353 void __iomem *addrbase = host->pcictrl_mmiobase;
354
355 pr_debug("PCI Control Registers:\n");
356 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
357 readb(addrbase + VIA_CRDR_PCICLKGATT),
358 readb(addrbase + VIA_CRDR_PCISDCCLK),
359 readb(addrbase + VIA_CRDR_PCIDMACLK));
360 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
361 readb(addrbase + VIA_CRDR_PCIINTCTRL),
362 readb(addrbase + VIA_CRDR_PCIINTSTATUS));
363}
364
365static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
366{
367 struct pcictrlreg *pm_pcictrl_reg;
368 void __iomem *addrbase;
369
370 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
371 addrbase = host->pcictrl_mmiobase;
372
373 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
374 pm_pcictrl_reg->pciclkgat_reg |=
375 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
376 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
377 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
378 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
379 pm_pcictrl_reg->pciintstatus_reg =
380 readb(addrbase + VIA_CRDR_PCIINTSTATUS);
381 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
382}
383
384static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
385{
386 struct pcictrlreg *pm_pcictrl_reg;
387 void __iomem *addrbase;
388
389 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
390 addrbase = host->pcictrl_mmiobase;
391
392 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
393 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
394 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
395 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
396 writeb(pm_pcictrl_reg->pciintstatus_reg,
397 addrbase + VIA_CRDR_PCIINTSTATUS);
398 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
399}
400
401static void via_save_sdcreg(struct via_crdr_mmc_host *host)
402{
403 struct sdhcreg *pm_sdhc_reg;
404 void __iomem *addrbase;
405
406 pm_sdhc_reg = &(host->pm_sdhc_reg);
407 addrbase = host->sdhc_mmiobase;
408
409 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
410 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
411 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
412 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
413 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
414 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
415 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
416 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
417 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
418 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
419}
420
421static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
422{
423 struct sdhcreg *pm_sdhc_reg;
424 void __iomem *addrbase;
425
426 pm_sdhc_reg = &(host->pm_sdhc_reg);
427 addrbase = host->sdhc_mmiobase;
428
429 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
430 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
431 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
432 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
433 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
434 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
435 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
436 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
437 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
438 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
439}
440
441static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
442{
443 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
444 msleep(300);
445 else
446 msleep(3);
447}
448
449static void via_set_ddma(struct via_crdr_mmc_host *host,
450 dma_addr_t dmaaddr, u32 count, int dir, int enirq)
451{
452 void __iomem *addrbase;
453 u32 ctrl_data = 0;
454
455 if (enirq)
456 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
457
458 if (dir)
459 ctrl_data |= VIA_CRDR_DMACTRL_DIR;
460
461 addrbase = host->ddma_mmiobase;
462
463 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
464 writel(count, addrbase + VIA_CRDR_DMACOUNTER);
465 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
466 writel(0x01, addrbase + VIA_CRDR_DMASTART);
467
468 /* It seems that our DMA can not work normally with 375kHz clock */
469 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
470 addrbase = host->pcictrl_mmiobase;
471 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
472 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
473 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
474 }
475}
476
477static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
478 struct mmc_data *data)
479{
480 void __iomem *addrbase;
481 u32 blk_reg;
482 int count;
483
484 WARN_ON(host->data);
485
486 /* Sanity checks */
487 BUG_ON(data->blksz > host->mmc->max_blk_size);
488 BUG_ON(data->blocks > host->mmc->max_blk_count);
489
490 host->data = data;
491
492 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
493 ((data->flags & MMC_DATA_READ) ?
494 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
495 BUG_ON(count != 1);
496
497 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
498 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
499
500 addrbase = host->sdhc_mmiobase;
501
502 blk_reg = data->blksz - 1;
503 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
504 blk_reg |= (data->blocks) << 16;
505
506 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
507}
508
509static void via_sdc_get_response(struct via_crdr_mmc_host *host,
510 struct mmc_command *cmd)
511{
512 void __iomem *addrbase = host->sdhc_mmiobase;
513 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
514 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
515 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
516 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
517
518 if (cmd->flags & MMC_RSP_136) {
519 cmd->resp[0] = ((u8) (dwdata1)) |
520 (((u8) (dwdata0 >> 24)) << 8) |
521 (((u8) (dwdata0 >> 16)) << 16) |
522 (((u8) (dwdata0 >> 8)) << 24);
523
524 cmd->resp[1] = ((u8) (dwdata2)) |
525 (((u8) (dwdata1 >> 24)) << 8) |
526 (((u8) (dwdata1 >> 16)) << 16) |
527 (((u8) (dwdata1 >> 8)) << 24);
528
529 cmd->resp[2] = ((u8) (dwdata3)) |
530 (((u8) (dwdata2 >> 24)) << 8) |
531 (((u8) (dwdata2 >> 16)) << 16) |
532 (((u8) (dwdata2 >> 8)) << 24);
533
534 cmd->resp[3] = 0xff |
535 ((((u8) (dwdata3 >> 24))) << 8) |
536 (((u8) (dwdata3 >> 16)) << 16) |
537 (((u8) (dwdata3 >> 8)) << 24);
538 } else {
539 dwdata0 >>= 8;
540 cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
541 (((dwdata0 >> 8) & 0xff) << 16) |
542 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
543
544 dwdata1 >>= 8;
545 cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
546 (((dwdata1 >> 8) & 0xff) << 16) |
547 (((dwdata1 >> 16) & 0xff) << 8);
548 }
549}
550
551static void via_sdc_send_command(struct via_crdr_mmc_host *host,
552 struct mmc_command *cmd)
553{
554 void __iomem *addrbase;
555 struct mmc_data *data;
556 u32 cmdctrl = 0;
557
558 WARN_ON(host->cmd);
559
560 data = cmd->data;
561 mod_timer(&host->timer, jiffies + HZ);
562 host->cmd = cmd;
563
564 /*Command index*/
565 cmdctrl = cmd->opcode << 8;
566
567 /*Response type*/
568 switch (mmc_resp_type(cmd)) {
569 case MMC_RSP_NONE:
570 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
571 break;
572 case MMC_RSP_R1:
573 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
574 break;
575 case MMC_RSP_R1B:
576 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
577 break;
578 case MMC_RSP_R2:
579 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
580 break;
581 case MMC_RSP_R3:
582 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
583 break;
584 default:
585 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
586 break;
587 }
588
589 if (!(cmd->data))
590 goto nodata;
591
592 via_sdc_preparedata(host, data);
593
594 /*Command control*/
595 if (data->blocks > 1) {
596 if (data->flags & MMC_DATA_WRITE) {
597 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
598 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
599 } else {
600 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
601 }
602 } else {
603 if (data->flags & MMC_DATA_WRITE) {
604 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
605 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
606 } else {
607 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
608 }
609 }
610
611nodata:
612 if (cmd == host->mrq->stop)
613 cmdctrl |= VIA_CRDR_SDCTRL_STOP;
614
615 cmdctrl |= VIA_CRDR_SDCTRL_START;
616
617 addrbase = host->sdhc_mmiobase;
618 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
619 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
620}
621
622static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
623{
624 struct mmc_data *data;
625
626 BUG_ON(!host->data);
627
628 data = host->data;
629 host->data = NULL;
630
631 if (data->error)
632 data->bytes_xfered = 0;
633 else
634 data->bytes_xfered = data->blocks * data->blksz;
635
636 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
637 ((data->flags & MMC_DATA_READ) ?
638 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
639
640 if (data->stop)
641 via_sdc_send_command(host, data->stop);
642 else
643 tasklet_schedule(&host->finish_tasklet);
644}
645
646static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
647{
648 via_sdc_get_response(host, host->cmd);
649
650 host->cmd->error = 0;
651
652 if (!host->cmd->data)
653 tasklet_schedule(&host->finish_tasklet);
654
655 host->cmd = NULL;
656}
657
658static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
659{
660 void __iomem *addrbase;
661 struct via_crdr_mmc_host *host;
662 unsigned long flags;
663 u16 status;
664
665 host = mmc_priv(mmc);
666
667 spin_lock_irqsave(&host->lock, flags);
668
669 addrbase = host->pcictrl_mmiobase;
670 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
671
672 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
673 status &= VIA_CRDR_SDSTS_W1C_MASK;
674 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
675
676 WARN_ON(host->mrq != NULL);
677 host->mrq = mrq;
678
679 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
680 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
681 host->mrq->cmd->error = -ENOMEDIUM;
682 tasklet_schedule(&host->finish_tasklet);
683 } else {
684 via_sdc_send_command(host, mrq->cmd);
685 }
686
687 mmiowb();
688 spin_unlock_irqrestore(&host->lock, flags);
689}
690
691static void via_sdc_set_power(struct via_crdr_mmc_host *host,
692 unsigned short power, unsigned int on)
693{
694 unsigned long flags;
695 u8 gatt;
696
697 spin_lock_irqsave(&host->lock, flags);
698
699 host->power = (1 << power);
700
701 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
702 if (host->power == MMC_VDD_165_195)
703 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
704 else
705 gatt |= VIA_CRDR_PCICLKGATT_3V3;
706 if (on)
707 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
708 else
709 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
710 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
711
712 mmiowb();
713 spin_unlock_irqrestore(&host->lock, flags);
714
715 via_pwron_sleep(host);
716}
717
718static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
719{
720 struct via_crdr_mmc_host *host;
721 unsigned long flags;
722 void __iomem *addrbase;
723 u32 org_data, sdextctrl;
724 u8 clock;
725
726 host = mmc_priv(mmc);
727
728 spin_lock_irqsave(&host->lock, flags);
729
730 addrbase = host->sdhc_mmiobase;
731 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
732 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
733
734 if (ios->bus_width == MMC_BUS_WIDTH_1)
735 org_data &= ~VIA_CRDR_SDMODE_4BIT;
736 else
737 org_data |= VIA_CRDR_SDMODE_4BIT;
738
739 if (ios->power_mode == MMC_POWER_OFF)
740 org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
741 else
742 org_data |= VIA_CRDR_SDMODE_CLK_ON;
743
744 if (ios->timing == MMC_TIMING_SD_HS)
745 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
746 else
747 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
748
749 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
750 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
751
752 if (ios->clock >= 48000000)
753 clock = PCI_CLK_48M;
754 else if (ios->clock >= 33000000)
755 clock = PCI_CLK_33M;
756 else if (ios->clock >= 24000000)
757 clock = PCI_CLK_24M;
758 else if (ios->clock >= 16000000)
759 clock = PCI_CLK_16M;
760 else if (ios->clock >= 12000000)
761 clock = PCI_CLK_12M;
762 else if (ios->clock >= 8000000)
763 clock = PCI_CLK_8M;
764 else
765 clock = PCI_CLK_375K;
766
767 addrbase = host->pcictrl_mmiobase;
768 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
769 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
770
771 mmiowb();
772 spin_unlock_irqrestore(&host->lock, flags);
773
774 if (ios->power_mode != MMC_POWER_OFF)
775 via_sdc_set_power(host, ios->vdd, 1);
776 else
777 via_sdc_set_power(host, ios->vdd, 0);
778}
779
780static int via_sdc_get_ro(struct mmc_host *mmc)
781{
782 struct via_crdr_mmc_host *host;
783 unsigned long flags;
784 u16 status;
785
786 host = mmc_priv(mmc);
787
788 spin_lock_irqsave(&host->lock, flags);
789
790 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
791
792 spin_unlock_irqrestore(&host->lock, flags);
793
794 return !(status & VIA_CRDR_SDSTS_WP);
795}
796
797static const struct mmc_host_ops via_sdc_ops = {
798 .request = via_sdc_request,
799 .set_ios = via_sdc_set_ios,
800 .get_ro = via_sdc_get_ro,
801};
802
803static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
804{
805 void __iomem *addrbase;
806 unsigned long flags;
807 u8 gatt;
808
809 addrbase = host->pcictrl_mmiobase;
810
811 spin_lock_irqsave(&host->lock, flags);
812
813 via_save_pcictrlreg(host);
814 via_save_sdcreg(host);
815
816 spin_unlock_irqrestore(&host->lock, flags);
817
818 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
819 if (host->power == MMC_VDD_165_195)
820 gatt &= VIA_CRDR_PCICLKGATT_3V3;
821 else
822 gatt |= VIA_CRDR_PCICLKGATT_3V3;
823 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
824 via_pwron_sleep(host);
825 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
826 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
827 msleep(3);
828
829 spin_lock_irqsave(&host->lock, flags);
830
831 via_restore_pcictrlreg(host);
832 via_restore_sdcreg(host);
833
834 mmiowb();
835 spin_unlock_irqrestore(&host->lock, flags);
836}
837
838static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
839{
840 BUG_ON(intmask == 0);
841
842 if (!host->cmd) {
843 pr_err("%s: Got command interrupt 0x%x even "
844 "though no command operation was in progress.\n",
845 mmc_hostname(host->mmc), intmask);
846 return;
847 }
848
849 if (intmask & VIA_CRDR_SDSTS_CRTO)
850 host->cmd->error = -ETIMEDOUT;
851 else if (intmask & VIA_CRDR_SDSTS_SC)
852 host->cmd->error = -EILSEQ;
853
854 if (host->cmd->error)
855 tasklet_schedule(&host->finish_tasklet);
856 else if (intmask & VIA_CRDR_SDSTS_CRD)
857 via_sdc_finish_command(host);
858}
859
860static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
861{
862 BUG_ON(intmask == 0);
863
864 if (intmask & VIA_CRDR_SDSTS_DT)
865 host->data->error = -ETIMEDOUT;
866 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
867 host->data->error = -EILSEQ;
868
869 via_sdc_finish_data(host);
870}
871
872static irqreturn_t via_sdc_isr(int irq, void *dev_id)
873{
874 struct via_crdr_mmc_host *sdhost = dev_id;
875 void __iomem *addrbase;
876 u8 pci_status;
877 u16 sd_status;
878 irqreturn_t result;
879
880 if (!sdhost)
881 return IRQ_NONE;
882
883 spin_lock(&sdhost->lock);
884
885 addrbase = sdhost->pcictrl_mmiobase;
886 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
887 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
888 result = IRQ_NONE;
889 goto out;
890 }
891
892 addrbase = sdhost->sdhc_mmiobase;
893 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
894 sd_status &= VIA_CRDR_SDSTS_INT_MASK;
895 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
896 if (!sd_status) {
897 result = IRQ_NONE;
898 goto out;
899 }
900
901 if (sd_status & VIA_CRDR_SDSTS_CIR) {
902 writew(sd_status & VIA_CRDR_SDSTS_CIR,
903 addrbase + VIA_CRDR_SDSTATUS);
904
905 schedule_work(&sdhost->carddet_work);
906 }
907
908 sd_status &= ~VIA_CRDR_SDSTS_CIR;
909 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
910 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
911 addrbase + VIA_CRDR_SDSTATUS);
912 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
913 }
914 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
915 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
916 addrbase + VIA_CRDR_SDSTATUS);
917 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
918 }
919
920 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
921 if (sd_status) {
922 pr_err("%s: Unexpected interrupt 0x%x\n",
923 mmc_hostname(sdhost->mmc), sd_status);
924 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
925 }
926
927 result = IRQ_HANDLED;
928
929 mmiowb();
930out:
931 spin_unlock(&sdhost->lock);
932
933 return result;
934}
935
936static void via_sdc_timeout(unsigned long ulongdata)
937{
938 struct via_crdr_mmc_host *sdhost;
939 unsigned long flags;
940
941 sdhost = (struct via_crdr_mmc_host *)ulongdata;
942
943 spin_lock_irqsave(&sdhost->lock, flags);
944
945 if (sdhost->mrq) {
946 pr_err("%s: Timeout waiting for hardware interrupt."
947 "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
948 sdhost->mrq->cmd->opcode);
949
950 if (sdhost->data) {
951 writel(VIA_CRDR_DMACTRL_SFTRST,
952 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
953 sdhost->data->error = -ETIMEDOUT;
954 via_sdc_finish_data(sdhost);
955 } else {
956 if (sdhost->cmd)
957 sdhost->cmd->error = -ETIMEDOUT;
958 else
959 sdhost->mrq->cmd->error = -ETIMEDOUT;
960 tasklet_schedule(&sdhost->finish_tasklet);
961 }
962 }
963
964 mmiowb();
965 spin_unlock_irqrestore(&sdhost->lock, flags);
966}
967
968static void via_sdc_tasklet_finish(unsigned long param)
969{
970 struct via_crdr_mmc_host *host;
971 unsigned long flags;
972 struct mmc_request *mrq;
973
974 host = (struct via_crdr_mmc_host *)param;
975
976 spin_lock_irqsave(&host->lock, flags);
977
978 del_timer(&host->timer);
979 mrq = host->mrq;
980 host->mrq = NULL;
981 host->cmd = NULL;
982 host->data = NULL;
983
984 spin_unlock_irqrestore(&host->lock, flags);
985
986 mmc_request_done(host->mmc, mrq);
987}
988
989static void via_sdc_card_detect(struct work_struct *work)
990{
991 struct via_crdr_mmc_host *host;
992 void __iomem *addrbase;
993 unsigned long flags;
994 u16 status;
995
996 host = container_of(work, struct via_crdr_mmc_host, carddet_work);
997
998 addrbase = host->ddma_mmiobase;
999 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
1000
1001 spin_lock_irqsave(&host->lock, flags);
1002
1003 addrbase = host->pcictrl_mmiobase;
1004 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
1005
1006 addrbase = host->sdhc_mmiobase;
1007 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1008 if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
1009 if (host->mrq) {
1010 pr_err("%s: Card removed during transfer!\n",
1011 mmc_hostname(host->mmc));
1012 host->mrq->cmd->error = -ENOMEDIUM;
1013 tasklet_schedule(&host->finish_tasklet);
1014 }
1015
1016 mmiowb();
1017 spin_unlock_irqrestore(&host->lock, flags);
1018
1019 via_reset_pcictrl(host);
1020
1021 spin_lock_irqsave(&host->lock, flags);
1022 }
1023
1024 mmiowb();
1025 spin_unlock_irqrestore(&host->lock, flags);
1026
1027 via_print_pcictrl(host);
1028 via_print_sdchc(host);
1029
1030 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1031}
1032
1033static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1034{
1035 struct mmc_host *mmc = host->mmc;
1036 void __iomem *addrbase;
1037 u32 lenreg;
1038 u32 status;
1039
1040 init_timer(&host->timer);
1041 host->timer.data = (unsigned long)host;
1042 host->timer.function = via_sdc_timeout;
1043
1044 spin_lock_init(&host->lock);
1045
1046 mmc->f_min = VIA_CRDR_MIN_CLOCK;
1047 mmc->f_max = VIA_CRDR_MAX_CLOCK;
1048 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1049 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1050 mmc->ops = &via_sdc_ops;
1051
1052 /*Hardware cannot do scatter lists*/
1053 mmc->max_hw_segs = 1;
1054 mmc->max_phys_segs = 1;
1055
1056 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1057 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1058
1059 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1060 mmc->max_req_size = mmc->max_seg_size;
1061
1062 INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1063
1064 tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish,
1065 (unsigned long)host);
1066
1067 addrbase = host->sdhc_mmiobase;
1068 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1069 msleep(1);
1070
1071 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1072 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1073
1074 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1075 status &= VIA_CRDR_SDSTS_W1C_MASK;
1076 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1077
1078 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1079 status |= VIA_CRDR_SDSTS_CFE;
1080 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1081
1082 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1083
1084 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1085 msleep(1);
1086}
1087
1088static int __devinit via_sd_probe(struct pci_dev *pcidev,
1089 const struct pci_device_id *id)
1090{
1091 struct mmc_host *mmc;
1092 struct via_crdr_mmc_host *sdhost;
1093 u32 base, len;
1094 u8 rev, gatt;
1095 int ret;
1096
1097 pci_read_config_byte(pcidev, PCI_CLASS_REVISION, &rev);
1098 pr_info(DRV_NAME
1099 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1100 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1101 (int)rev);
1102
1103 ret = pci_enable_device(pcidev);
1104 if (ret)
1105 return ret;
1106
1107 ret = pci_request_regions(pcidev, DRV_NAME);
1108 if (ret)
1109 goto disable;
1110
1111 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1112 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1113
1114 mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1115 if (!mmc) {
1116 ret = -ENOMEM;
1117 goto release;
1118 }
1119
1120 sdhost = mmc_priv(mmc);
1121 sdhost->mmc = mmc;
1122 dev_set_drvdata(&pcidev->dev, sdhost);
1123
1124 len = pci_resource_len(pcidev, 0);
1125 base = pci_resource_start(pcidev, 0);
1126 sdhost->mmiobase = ioremap_nocache(base, len);
1127 if (!sdhost->mmiobase) {
1128 ret = -ENOMEM;
1129 goto free_mmc_host;
1130 }
1131
1132 sdhost->sdhc_mmiobase =
1133 sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1134 sdhost->ddma_mmiobase =
1135 sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1136 sdhost->pcictrl_mmiobase =
1137 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1138
1139 sdhost->power = MMC_VDD_165_195;
1140
1141 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1142 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1143 via_pwron_sleep(sdhost);
1144 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1145 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1146 msleep(3);
1147
1148 via_init_mmc_host(sdhost);
1149
1150 ret =
1151 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1152 sdhost);
1153 if (ret)
1154 goto unmap;
1155
1156 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1157 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1158 writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1159 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1160
1161 /* device-specific quirks */
1162 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1163 pcidev->subsystem_device == 0x3891)
1164 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1165
1166 mmc_add_host(mmc);
1167
1168 return 0;
1169
1170unmap:
1171 iounmap(sdhost->mmiobase);
1172free_mmc_host:
1173 dev_set_drvdata(&pcidev->dev, NULL);
1174 mmc_free_host(mmc);
1175release:
1176 pci_release_regions(pcidev);
1177disable:
1178 pci_disable_device(pcidev);
1179
1180 return ret;
1181}
1182
1183static void __devexit via_sd_remove(struct pci_dev *pcidev)
1184{
1185 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1186 unsigned long flags;
1187 u8 gatt;
1188
1189 spin_lock_irqsave(&sdhost->lock, flags);
1190
1191 /* Ensure we don't accept more commands from mmc layer */
1192 sdhost->reject = 1;
1193
1194 /* Disable generating further interrupts */
1195 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1196 mmiowb();
1197
1198 if (sdhost->mrq) {
1199 printk(KERN_ERR "%s: Controller removed during "
1200 "transfer\n", mmc_hostname(sdhost->mmc));
1201
1202 /* make sure all DMA is stopped */
1203 writel(VIA_CRDR_DMACTRL_SFTRST,
1204 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1205 mmiowb();
1206 sdhost->mrq->cmd->error = -ENOMEDIUM;
1207 if (sdhost->mrq->stop)
1208 sdhost->mrq->stop->error = -ENOMEDIUM;
1209 tasklet_schedule(&sdhost->finish_tasklet);
1210 }
1211 spin_unlock_irqrestore(&sdhost->lock, flags);
1212
1213 mmc_remove_host(sdhost->mmc);
1214
1215 free_irq(pcidev->irq, sdhost);
1216
1217 del_timer_sync(&sdhost->timer);
1218
1219 tasklet_kill(&sdhost->finish_tasklet);
1220
1221 /* switch off power */
1222 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1223 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1224 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1225
1226 iounmap(sdhost->mmiobase);
1227 dev_set_drvdata(&pcidev->dev, NULL);
1228 mmc_free_host(sdhost->mmc);
1229 pci_release_regions(pcidev);
1230 pci_disable_device(pcidev);
1231
1232 pr_info(DRV_NAME
1233 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1234 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1235}
1236
1237#ifdef CONFIG_PM
1238
1239static void via_init_sdc_pm(struct via_crdr_mmc_host *host)
1240{
1241 struct sdhcreg *pm_sdhcreg;
1242 void __iomem *addrbase;
1243 u32 lenreg;
1244 u16 status;
1245
1246 pm_sdhcreg = &(host->pm_sdhc_reg);
1247 addrbase = host->sdhc_mmiobase;
1248
1249 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1250
1251 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1252 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1253
1254 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1255 status &= VIA_CRDR_SDSTS_W1C_MASK;
1256 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1257
1258 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1259 status |= VIA_CRDR_SDSTS_CFE;
1260 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1261
1262 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1263 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1264 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1265 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1266 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1267 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1268
1269 via_print_pcictrl(host);
1270 via_print_sdchc(host);
1271}
1272
1273static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state)
1274{
1275 struct via_crdr_mmc_host *host;
1276 int ret = 0;
1277
1278 host = pci_get_drvdata(pcidev);
1279
1280 via_save_pcictrlreg(host);
1281 via_save_sdcreg(host);
1282
1283 ret = mmc_suspend_host(host->mmc, state);
1284
1285 pci_save_state(pcidev);
1286 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1287 pci_disable_device(pcidev);
1288 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1289
1290 return ret;
1291}
1292
1293static int via_sd_resume(struct pci_dev *pcidev)
1294{
1295 struct via_crdr_mmc_host *sdhost;
1296 int ret = 0;
1297 u8 gatt;
1298
1299 sdhost = pci_get_drvdata(pcidev);
1300
1301 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1302 if (sdhost->power == MMC_VDD_165_195)
1303 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1304 else
1305 gatt |= VIA_CRDR_PCICLKGATT_3V3;
1306 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1307 via_pwron_sleep(sdhost);
1308 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1309 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1310 msleep(3);
1311
1312 msleep(100);
1313
1314 pci_set_power_state(pcidev, PCI_D0);
1315 pci_restore_state(pcidev);
1316 ret = pci_enable_device(pcidev);
1317 if (ret)
1318 return ret;
1319
1320 via_restore_pcictrlreg(sdhost);
1321 via_init_sdc_pm(sdhost);
1322
1323 ret = mmc_resume_host(sdhost->mmc);
1324
1325 return ret;
1326}
1327
1328#else /* CONFIG_PM */
1329
1330#define via_sd_suspend NULL
1331#define via_sd_resume NULL
1332
1333#endif /* CONFIG_PM */
1334
1335static struct pci_driver via_sd_driver = {
1336 .name = DRV_NAME,
1337 .id_table = via_ids,
1338 .probe = via_sd_probe,
1339 .remove = __devexit_p(via_sd_remove),
1340 .suspend = via_sd_suspend,
1341 .resume = via_sd_resume,
1342};
1343
1344static int __init via_sd_drv_init(void)
1345{
1346 pr_info(DRV_NAME ": VIA SD/MMC Card Reader driver "
1347 "(C) 2008 VIA Technologies, Inc.\n");
1348
1349 return pci_register_driver(&via_sd_driver);
1350}
1351
1352static void __exit via_sd_drv_exit(void)
1353{
1354 pci_unregister_driver(&via_sd_driver);
1355}
1356
1357module_init(via_sd_drv_init);
1358module_exit(via_sd_drv_exit);
1359
1360MODULE_LICENSE("GPL");
1361MODULE_AUTHOR("VIA Technologies Inc.");
1362MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-31 00:13:09 -0500