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authorSan Mehat <san@android.com>2009-09-22 19:44:22 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-23 10:39:32 -0400
commit9d2bd7383c71d38c60328a3dc8a946eda2013826 (patch)
treec37b8432be89186a8a6a0751388cf84e7930824f /drivers/mmc
parentccdfe3a66a57f5e36f56101e60946ee341eb5f1b (diff)
mmc: msm_sdccc: driver for HTC Dream
MMC Driver for HTC Dream. I picked the code up from Google git trees, removed stuff not strictly necessary, and did a few cleanups. It still works :-). Signed-off-by: Pavel Machek <pavel@ucw.cz> Cc: Brian Swetland <swetland@google.com> Cc: Pierre Ossman <drzeus-list@drzeus.cx> Cc: Joe Perches <joe@perches.com> Cc: Matt Fleming <matt@console-pimps.org> Cc: Ian Molton <ian@mnementh.co.uk> Cc: "Roberto A. Foglietta" <roberto.foglietta@gmail.com> Cc: Philip Langdale <philipl@overt.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/Kconfig7
-rw-r--r--drivers/mmc/host/Makefile1
-rw-r--r--drivers/mmc/host/msm_sdcc.c1301
-rw-r--r--drivers/mmc/host/msm_sdcc.h238
4 files changed, 1547 insertions, 0 deletions
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 891ef18bd77b..34fdfa968fe9 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -199,6 +199,13 @@ config MMC_IMX
199 199
200 If unsure, say N. 200 If unsure, say N.
201 201
202config MMC_MSM7X00A
203 tristate "Qualcomm MSM 7X00A SDCC Controller Support"
204 depends on MMC && ARCH_MSM
205 help
206 This provides support for the SD/MMC cell found in the
207 MSM 7X00A controllers from Qualcomm.
208
202config MMC_MXC 209config MMC_MXC
203 tristate "Freescale i.MX2/3 Multimedia Card Interface support" 210 tristate "Freescale i.MX2/3 Multimedia Card Interface support"
204 depends on ARCH_MXC 211 depends on ARCH_MXC
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index cf153f628457..abcb0400e06d 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o
23obj-$(CONFIG_MMC_AT91) += at91_mci.o 23obj-$(CONFIG_MMC_AT91) += at91_mci.o
24obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o 24obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
25obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o 25obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
26obj-$(CONFIG_MMC_MSM7X00A) += msm_sdcc.o
26obj-$(CONFIG_MMC_MVSDIO) += mvsdio.o 27obj-$(CONFIG_MMC_MVSDIO) += mvsdio.o
27obj-$(CONFIG_MMC_SPI) += mmc_spi.o 28obj-$(CONFIG_MMC_SPI) += mmc_spi.o
28ifeq ($(CONFIG_OF),y) 29ifeq ($(CONFIG_OF),y)
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
new file mode 100644
index 000000000000..042f21702988
--- /dev/null
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -0,0 +1,1301 @@
1/*
2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
3 *
4 * Copyright (C) 2007 Google Inc,
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Based on mmci.c
12 *
13 * Author: San Mehat (san@android.com)
14 *
15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
20#include <linux/ioport.h>
21#include <linux/device.h>
22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/highmem.h>
26#include <linux/log2.h>
27#include <linux/mmc/host.h>
28#include <linux/mmc/card.h>
29#include <linux/clk.h>
30#include <linux/scatterlist.h>
31#include <linux/platform_device.h>
32#include <linux/dma-mapping.h>
33#include <linux/debugfs.h>
34#include <linux/io.h>
35#include <linux/memory.h>
36
37#include <asm/cacheflush.h>
38#include <asm/div64.h>
39#include <asm/sizes.h>
40
41#include <asm/mach/mmc.h>
42#include <mach/msm_iomap.h>
43#include <mach/dma.h>
44#include <mach/htc_pwrsink.h>
45
46
47#include "msm_sdcc.h"
48
49#define DRIVER_NAME "msm-sdcc"
50
51static unsigned int msmsdcc_fmin = 144000;
52static unsigned int msmsdcc_fmax = 50000000;
53static unsigned int msmsdcc_4bit = 1;
54static unsigned int msmsdcc_pwrsave = 1;
55static unsigned int msmsdcc_piopoll = 1;
56static unsigned int msmsdcc_sdioirq;
57
58#define PIO_SPINMAX 30
59#define CMD_SPINMAX 20
60
61
62
63static void
64msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
65 u32 c);
66
67static void
68msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
69{
70 writel(0, host->base + MMCICOMMAND);
71
72 BUG_ON(host->curr.data);
73
74 host->curr.mrq = NULL;
75 host->curr.cmd = NULL;
76
77 if (mrq->data)
78 mrq->data->bytes_xfered = host->curr.data_xfered;
79 if (mrq->cmd->error == -ETIMEDOUT)
80 mdelay(5);
81
82 /*
83 * Need to drop the host lock here; mmc_request_done may call
84 * back into the driver...
85 */
86 spin_unlock(&host->lock);
87 mmc_request_done(host->mmc, mrq);
88 spin_lock(&host->lock);
89}
90
91static void
92msmsdcc_stop_data(struct msmsdcc_host *host)
93{
94 writel(0, host->base + MMCIDATACTRL);
95 host->curr.data = NULL;
96 host->curr.got_dataend = host->curr.got_datablkend = 0;
97}
98
99uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
100{
101 if (host->pdev_id == 1)
102 return MSM_SDC1_PHYS + MMCIFIFO;
103 else if (host->pdev_id == 2)
104 return MSM_SDC2_PHYS + MMCIFIFO;
105 else if (host->pdev_id == 3)
106 return MSM_SDC3_PHYS + MMCIFIFO;
107 else if (host->pdev_id == 4)
108 return MSM_SDC4_PHYS + MMCIFIFO;
109 else
110 BUG();
111 return 0;
112}
113
114static void
115msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
116 unsigned int result,
117 struct msm_dmov_errdata *err)
118{
119 struct msmsdcc_dma_data *dma_data =
120 container_of(cmd, struct msmsdcc_dma_data, hdr);
121 struct msmsdcc_host *host = dma_data->host;
122 unsigned long flags;
123 struct mmc_request *mrq;
124
125 spin_lock_irqsave(&host->lock, flags);
126 mrq = host->curr.mrq;
127 BUG_ON(!mrq);
128
129 if (!(result & DMOV_RSLT_VALID)) {
130 printk(KERN_ERR "msmsdcc: Invalid DataMover result\n");
131 goto out;
132 }
133
134 if (result & DMOV_RSLT_DONE) {
135 host->curr.data_xfered = host->curr.xfer_size;
136 } else {
137 /* Error or flush */
138 if (result & DMOV_RSLT_ERROR)
139 printk(KERN_ERR "%s: DMA error (0x%.8x)\n",
140 mmc_hostname(host->mmc), result);
141 if (result & DMOV_RSLT_FLUSH)
142 printk(KERN_ERR "%s: DMA channel flushed (0x%.8x)\n",
143 mmc_hostname(host->mmc), result);
144 if (err)
145 printk(KERN_ERR
146 "Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
147 err->flush[0], err->flush[1], err->flush[2],
148 err->flush[3], err->flush[4], err->flush[5]);
149 if (!mrq->data->error)
150 mrq->data->error = -EIO;
151 }
152 host->dma.busy = 0;
153 dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
154 host->dma.dir);
155
156 if (host->curr.user_pages) {
157 struct scatterlist *sg = host->dma.sg;
158 int i;
159
160 for (i = 0; i < host->dma.num_ents; i++, sg++)
161 flush_dcache_page(sg_page(sg));
162 }
163
164 host->dma.sg = NULL;
165
166 if ((host->curr.got_dataend && host->curr.got_datablkend)
167 || mrq->data->error) {
168
169 /*
170 * If we've already gotten our DATAEND / DATABLKEND
171 * for this request, then complete it through here.
172 */
173 msmsdcc_stop_data(host);
174
175 if (!mrq->data->error)
176 host->curr.data_xfered = host->curr.xfer_size;
177 if (!mrq->data->stop || mrq->cmd->error) {
178 writel(0, host->base + MMCICOMMAND);
179 host->curr.mrq = NULL;
180 host->curr.cmd = NULL;
181 mrq->data->bytes_xfered = host->curr.data_xfered;
182
183 spin_unlock_irqrestore(&host->lock, flags);
184 mmc_request_done(host->mmc, mrq);
185 return;
186 } else
187 msmsdcc_start_command(host, mrq->data->stop, 0);
188 }
189
190out:
191 spin_unlock_irqrestore(&host->lock, flags);
192 return;
193}
194
195static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
196{
197 if (host->dma.channel == -1)
198 return -ENOENT;
199
200 if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
201 return -EINVAL;
202 if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
203 return -EINVAL;
204 return 0;
205}
206
207static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
208{
209 struct msmsdcc_nc_dmadata *nc;
210 dmov_box *box;
211 uint32_t rows;
212 uint32_t crci;
213 unsigned int n;
214 int i, rc;
215 struct scatterlist *sg = data->sg;
216
217 rc = validate_dma(host, data);
218 if (rc)
219 return rc;
220
221 host->dma.sg = data->sg;
222 host->dma.num_ents = data->sg_len;
223
224 nc = host->dma.nc;
225
226 if (host->pdev_id == 1)
227 crci = MSMSDCC_CRCI_SDC1;
228 else if (host->pdev_id == 2)
229 crci = MSMSDCC_CRCI_SDC2;
230 else if (host->pdev_id == 3)
231 crci = MSMSDCC_CRCI_SDC3;
232 else if (host->pdev_id == 4)
233 crci = MSMSDCC_CRCI_SDC4;
234 else {
235 host->dma.sg = NULL;
236 host->dma.num_ents = 0;
237 return -ENOENT;
238 }
239
240 if (data->flags & MMC_DATA_READ)
241 host->dma.dir = DMA_FROM_DEVICE;
242 else
243 host->dma.dir = DMA_TO_DEVICE;
244
245 host->curr.user_pages = 0;
246
247 n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
248 host->dma.num_ents, host->dma.dir);
249
250 if (n != host->dma.num_ents) {
251 printk(KERN_ERR "%s: Unable to map in all sg elements\n",
252 mmc_hostname(host->mmc));
253 host->dma.sg = NULL;
254 host->dma.num_ents = 0;
255 return -ENOMEM;
256 }
257
258 box = &nc->cmd[0];
259 for (i = 0; i < host->dma.num_ents; i++) {
260 box->cmd = CMD_MODE_BOX;
261
262 if (i == (host->dma.num_ents - 1))
263 box->cmd |= CMD_LC;
264 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
265 (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
266 (sg_dma_len(sg) / MCI_FIFOSIZE) ;
267
268 if (data->flags & MMC_DATA_READ) {
269 box->src_row_addr = msmsdcc_fifo_addr(host);
270 box->dst_row_addr = sg_dma_address(sg);
271
272 box->src_dst_len = (MCI_FIFOSIZE << 16) |
273 (MCI_FIFOSIZE);
274 box->row_offset = MCI_FIFOSIZE;
275
276 box->num_rows = rows * ((1 << 16) + 1);
277 box->cmd |= CMD_SRC_CRCI(crci);
278 } else {
279 box->src_row_addr = sg_dma_address(sg);
280 box->dst_row_addr = msmsdcc_fifo_addr(host);
281
282 box->src_dst_len = (MCI_FIFOSIZE << 16) |
283 (MCI_FIFOSIZE);
284 box->row_offset = (MCI_FIFOSIZE << 16);
285
286 box->num_rows = rows * ((1 << 16) + 1);
287 box->cmd |= CMD_DST_CRCI(crci);
288 }
289 box++;
290 sg++;
291 }
292
293 /* location of command block must be 64 bit aligned */
294 BUG_ON(host->dma.cmd_busaddr & 0x07);
295
296 nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
297 host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
298 DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
299 host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
300
301 return 0;
302}
303
304static void
305msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data)
306{
307 unsigned int datactrl, timeout;
308 unsigned long long clks;
309 void __iomem *base = host->base;
310 unsigned int pio_irqmask = 0;
311
312 host->curr.data = data;
313 host->curr.xfer_size = data->blksz * data->blocks;
314 host->curr.xfer_remain = host->curr.xfer_size;
315 host->curr.data_xfered = 0;
316 host->curr.got_dataend = 0;
317 host->curr.got_datablkend = 0;
318
319 memset(&host->pio, 0, sizeof(host->pio));
320
321 clks = (unsigned long long)data->timeout_ns * host->clk_rate;
322 do_div(clks, 1000000000UL);
323 timeout = data->timeout_clks + (unsigned int)clks;
324 writel(timeout, base + MMCIDATATIMER);
325
326 writel(host->curr.xfer_size, base + MMCIDATALENGTH);
327
328 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
329
330 if (!msmsdcc_config_dma(host, data))
331 datactrl |= MCI_DPSM_DMAENABLE;
332 else {
333 host->pio.sg = data->sg;
334 host->pio.sg_len = data->sg_len;
335 host->pio.sg_off = 0;
336
337 if (data->flags & MMC_DATA_READ) {
338 pio_irqmask = MCI_RXFIFOHALFFULLMASK;
339 if (host->curr.xfer_remain < MCI_FIFOSIZE)
340 pio_irqmask |= MCI_RXDATAAVLBLMASK;
341 } else
342 pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
343 }
344
345 if (data->flags & MMC_DATA_READ)
346 datactrl |= MCI_DPSM_DIRECTION;
347
348 writel(pio_irqmask, base + MMCIMASK1);
349 writel(datactrl, base + MMCIDATACTRL);
350
351 if (datactrl & MCI_DPSM_DMAENABLE) {
352 host->dma.busy = 1;
353 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
354 }
355}
356
357static void
358msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
359{
360 void __iomem *base = host->base;
361
362 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
363 writel(0, base + MMCICOMMAND);
364 udelay(2 + ((5 * 1000000) / host->clk_rate));
365 }
366
367 c |= cmd->opcode | MCI_CPSM_ENABLE;
368
369 if (cmd->flags & MMC_RSP_PRESENT) {
370 if (cmd->flags & MMC_RSP_136)
371 c |= MCI_CPSM_LONGRSP;
372 c |= MCI_CPSM_RESPONSE;
373 }
374
375 if ((((cmd->opcode == 17) || (cmd->opcode == 18)) ||
376 ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
377 (cmd->opcode == 53))
378 c |= MCI_CSPM_DATCMD;
379
380 if (cmd == cmd->mrq->stop)
381 c |= MCI_CSPM_MCIABORT;
382
383 host->curr.cmd = cmd;
384
385 host->stats.cmds++;
386
387 writel(cmd->arg, base + MMCIARGUMENT);
388 writel(c, base + MMCICOMMAND);
389}
390
391static void
392msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
393 unsigned int status)
394{
395 if (status & MCI_DATACRCFAIL) {
396 printk(KERN_ERR "%s: Data CRC error\n",
397 mmc_hostname(host->mmc));
398 printk(KERN_ERR "%s: opcode 0x%.8x\n", __func__,
399 data->mrq->cmd->opcode);
400 printk(KERN_ERR "%s: blksz %d, blocks %d\n", __func__,
401 data->blksz, data->blocks);
402 data->error = -EILSEQ;
403 } else if (status & MCI_DATATIMEOUT) {
404 printk(KERN_ERR "%s: Data timeout\n", mmc_hostname(host->mmc));
405 data->error = -ETIMEDOUT;
406 } else if (status & MCI_RXOVERRUN) {
407 printk(KERN_ERR "%s: RX overrun\n", mmc_hostname(host->mmc));
408 data->error = -EIO;
409 } else if (status & MCI_TXUNDERRUN) {
410 printk(KERN_ERR "%s: TX underrun\n", mmc_hostname(host->mmc));
411 data->error = -EIO;
412 } else {
413 printk(KERN_ERR "%s: Unknown error (0x%.8x)\n",
414 mmc_hostname(host->mmc), status);
415 data->error = -EIO;
416 }
417}
418
419
420static int
421msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
422{
423 void __iomem *base = host->base;
424 uint32_t *ptr = (uint32_t *) buffer;
425 int count = 0;
426
427 while (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL) {
428
429 *ptr = readl(base + MMCIFIFO + (count % MCI_FIFOSIZE));
430 ptr++;
431 count += sizeof(uint32_t);
432
433 remain -= sizeof(uint32_t);
434 if (remain == 0)
435 break;
436 }
437 return count;
438}
439
440static int
441msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
442 unsigned int remain, u32 status)
443{
444 void __iomem *base = host->base;
445 char *ptr = buffer;
446
447 do {
448 unsigned int count, maxcnt;
449
450 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
451 MCI_FIFOHALFSIZE;
452 count = min(remain, maxcnt);
453
454 writesl(base + MMCIFIFO, ptr, count >> 2);
455 ptr += count;
456 remain -= count;
457
458 if (remain == 0)
459 break;
460
461 status = readl(base + MMCISTATUS);
462 } while (status & MCI_TXFIFOHALFEMPTY);
463
464 return ptr - buffer;
465}
466
467static int
468msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
469{
470 while (maxspin) {
471 if ((readl(host->base + MMCISTATUS) & mask))
472 return 0;
473 udelay(1);
474 --maxspin;
475 }
476 return -ETIMEDOUT;
477}
478
479static int
480msmsdcc_pio_irq(int irq, void *dev_id)
481{
482 struct msmsdcc_host *host = dev_id;
483 void __iomem *base = host->base;
484 uint32_t status;
485
486 status = readl(base + MMCISTATUS);
487
488 do {
489 unsigned long flags;
490 unsigned int remain, len;
491 char *buffer;
492
493 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
494 if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
495 break;
496
497 if (msmsdcc_spin_on_status(host,
498 (MCI_TXFIFOHALFEMPTY |
499 MCI_RXDATAAVLBL),
500 PIO_SPINMAX)) {
501 break;
502 }
503 }
504
505 /* Map the current scatter buffer */
506 local_irq_save(flags);
507 buffer = kmap_atomic(sg_page(host->pio.sg),
508 KM_BIO_SRC_IRQ) + host->pio.sg->offset;
509 buffer += host->pio.sg_off;
510 remain = host->pio.sg->length - host->pio.sg_off;
511 len = 0;
512 if (status & MCI_RXACTIVE)
513 len = msmsdcc_pio_read(host, buffer, remain);
514 if (status & MCI_TXACTIVE)
515 len = msmsdcc_pio_write(host, buffer, remain, status);
516
517 /* Unmap the buffer */
518 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
519 local_irq_restore(flags);
520
521 host->pio.sg_off += len;
522 host->curr.xfer_remain -= len;
523 host->curr.data_xfered += len;
524 remain -= len;
525
526 if (remain == 0) {
527 /* This sg page is full - do some housekeeping */
528 if (status & MCI_RXACTIVE && host->curr.user_pages)
529 flush_dcache_page(sg_page(host->pio.sg));
530
531 if (!--host->pio.sg_len) {
532 memset(&host->pio, 0, sizeof(host->pio));
533 break;
534 }
535
536 /* Advance to next sg */
537 host->pio.sg++;
538 host->pio.sg_off = 0;
539 }
540
541 status = readl(base + MMCISTATUS);
542 } while (1);
543
544 if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
545 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
546
547 if (!host->curr.xfer_remain)
548 writel(0, base + MMCIMASK1);
549
550 return IRQ_HANDLED;
551}
552
553static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
554{
555 struct mmc_command *cmd = host->curr.cmd;
556 void __iomem *base = host->base;
557
558 host->curr.cmd = NULL;
559 cmd->resp[0] = readl(base + MMCIRESPONSE0);
560 cmd->resp[1] = readl(base + MMCIRESPONSE1);
561 cmd->resp[2] = readl(base + MMCIRESPONSE2);
562 cmd->resp[3] = readl(base + MMCIRESPONSE3);
563
564 del_timer(&host->command_timer);
565 if (status & MCI_CMDTIMEOUT) {
566 cmd->error = -ETIMEDOUT;
567 } else if (status & MCI_CMDCRCFAIL &&
568 cmd->flags & MMC_RSP_CRC) {
569 printk(KERN_ERR "%s: Command CRC error\n",
570 mmc_hostname(host->mmc));
571 cmd->error = -EILSEQ;
572 }
573
574 if (!cmd->data || cmd->error) {
575 if (host->curr.data && host->dma.sg)
576 msm_dmov_stop_cmd(host->dma.channel,
577 &host->dma.hdr, 0);
578 else if (host->curr.data) { /* Non DMA */
579 msmsdcc_stop_data(host);
580 msmsdcc_request_end(host, cmd->mrq);
581 } else /* host->data == NULL */
582 msmsdcc_request_end(host, cmd->mrq);
583 } else if (!(cmd->data->flags & MMC_DATA_READ))
584 msmsdcc_start_data(host, cmd->data);
585}
586
587static irqreturn_t
588msmsdcc_irq(int irq, void *dev_id)
589{
590 struct msmsdcc_host *host = dev_id;
591 void __iomem *base = host->base;
592 u32 status;
593 int ret = 0;
594 int cardint = 0;
595
596 spin_lock(&host->lock);
597
598 do {
599 struct mmc_data *data;
600 status = readl(base + MMCISTATUS);
601
602 status &= (readl(base + MMCIMASK0) |
603 MCI_DATABLOCKENDMASK);
604 writel(status, base + MMCICLEAR);
605
606 data = host->curr.data;
607 if (data) {
608 /* Check for data errors */
609 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|
610 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
611 msmsdcc_data_err(host, data, status);
612 host->curr.data_xfered = 0;
613 if (host->dma.sg)
614 msm_dmov_stop_cmd(host->dma.channel,
615 &host->dma.hdr, 0);
616 else {
617 msmsdcc_stop_data(host);
618 if (!data->stop)
619 msmsdcc_request_end(host,
620 data->mrq);
621 else
622 msmsdcc_start_command(host,
623 data->stop,
624 0);
625 }
626 }
627
628 /* Check for data done */
629 if (!host->curr.got_dataend && (status & MCI_DATAEND))
630 host->curr.got_dataend = 1;
631
632 if (!host->curr.got_datablkend &&
633 (status & MCI_DATABLOCKEND)) {
634 host->curr.got_datablkend = 1;
635 }
636
637 if (host->curr.got_dataend &&
638 host->curr.got_datablkend) {
639 /*
640 * If DMA is still in progress, we complete
641 * via the completion handler
642 */
643 if (!host->dma.busy) {
644 /*
645 * There appears to be an issue in the
646 * controller where if you request a
647 * small block transfer (< fifo size),
648 * you may get your DATAEND/DATABLKEND
649 * irq without the PIO data irq.
650 *
651 * Check to see if theres still data
652 * to be read, and simulate a PIO irq.
653 */
654 if (readl(base + MMCISTATUS) &
655 MCI_RXDATAAVLBL)
656 msmsdcc_pio_irq(1, host);
657
658 msmsdcc_stop_data(host);
659 if (!data->error)
660 host->curr.data_xfered =
661 host->curr.xfer_size;
662
663 if (!data->stop)
664 msmsdcc_request_end(host,
665 data->mrq);
666 else
667 msmsdcc_start_command(host,
668 data->stop, 0);
669 }
670 }
671 }
672
673 if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
674 MCI_CMDTIMEOUT) && host->curr.cmd) {
675 msmsdcc_do_cmdirq(host, status);
676 }
677
678 if (status & MCI_SDIOINTOPER) {
679 cardint = 1;
680 status &= ~MCI_SDIOINTOPER;
681 }
682 ret = 1;
683 } while (status);
684
685 spin_unlock(&host->lock);
686
687 /*
688 * We have to delay handling the card interrupt as it calls
689 * back into the driver.
690 */
691 if (cardint)
692 mmc_signal_sdio_irq(host->mmc);
693
694 return IRQ_RETVAL(ret);
695}
696
697static void
698msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
699{
700 struct msmsdcc_host *host = mmc_priv(mmc);
701 unsigned long flags;
702
703 WARN_ON(host->curr.mrq != NULL);
704 WARN_ON(host->pwr == 0);
705
706 spin_lock_irqsave(&host->lock, flags);
707
708 host->stats.reqs++;
709
710 if (host->eject) {
711 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
712 mrq->cmd->error = 0;
713 mrq->data->bytes_xfered = mrq->data->blksz *
714 mrq->data->blocks;
715 } else
716 mrq->cmd->error = -ENOMEDIUM;
717
718 spin_unlock_irqrestore(&host->lock, flags);
719 mmc_request_done(mmc, mrq);
720 return;
721 }
722
723 host->curr.mrq = mrq;
724
725 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
726 msmsdcc_start_data(host, mrq->data);
727
728 msmsdcc_start_command(host, mrq->cmd, 0);
729
730 if (host->cmdpoll && !msmsdcc_spin_on_status(host,
731 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
732 CMD_SPINMAX)) {
733 uint32_t status = readl(host->base + MMCISTATUS);
734 msmsdcc_do_cmdirq(host, status);
735 writel(MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
736 host->base + MMCICLEAR);
737 host->stats.cmdpoll_hits++;
738 } else {
739 host->stats.cmdpoll_misses++;
740 mod_timer(&host->command_timer, jiffies + HZ);
741 }
742 spin_unlock_irqrestore(&host->lock, flags);
743}
744
745static void
746msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
747{
748 struct msmsdcc_host *host = mmc_priv(mmc);
749 u32 clk = 0, pwr = 0;
750 int rc;
751
752 if (ios->clock) {
753
754 if (!host->clks_on) {
755 clk_enable(host->pclk);
756 clk_enable(host->clk);
757 host->clks_on = 1;
758 }
759 if (ios->clock != host->clk_rate) {
760 rc = clk_set_rate(host->clk, ios->clock);
761 if (rc < 0)
762 printk(KERN_ERR
763 "Error setting clock rate (%d)\n", rc);
764 else
765 host->clk_rate = ios->clock;
766 }
767 clk |= MCI_CLK_ENABLE;
768 }
769
770 if (ios->bus_width == MMC_BUS_WIDTH_4)
771 clk |= (2 << 10); /* Set WIDEBUS */
772
773 if (ios->clock > 400000 && msmsdcc_pwrsave)
774 clk |= (1 << 9); /* PWRSAVE */
775
776 clk |= (1 << 12); /* FLOW_ENA */
777 clk |= (1 << 15); /* feedback clock */
778
779 if (host->plat->translate_vdd)
780 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
781
782 switch (ios->power_mode) {
783 case MMC_POWER_OFF:
784 htc_pwrsink_set(PWRSINK_SDCARD, 0);
785 break;
786 case MMC_POWER_UP:
787 pwr |= MCI_PWR_UP;
788 break;
789 case MMC_POWER_ON:
790 htc_pwrsink_set(PWRSINK_SDCARD, 100);
791 pwr |= MCI_PWR_ON;
792 break;
793 }
794
795 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
796 pwr |= MCI_OD;
797
798 writel(clk, host->base + MMCICLOCK);
799
800 if (host->pwr != pwr) {
801 host->pwr = pwr;
802 writel(pwr, host->base + MMCIPOWER);
803 }
804
805 if (!(clk & MCI_CLK_ENABLE) && host->clks_on) {
806 clk_disable(host->clk);
807 clk_disable(host->pclk);
808 host->clks_on = 0;
809 }
810}
811
812static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
813{
814 struct msmsdcc_host *host = mmc_priv(mmc);
815 unsigned long flags;
816 u32 status;
817
818 spin_lock_irqsave(&host->lock, flags);
819 if (msmsdcc_sdioirq == 1) {
820 status = readl(host->base + MMCIMASK0);
821 if (enable)
822 status |= MCI_SDIOINTOPERMASK;
823 else
824 status &= ~MCI_SDIOINTOPERMASK;
825 host->saved_irq0mask = status;
826 writel(status, host->base + MMCIMASK0);
827 }
828 spin_unlock_irqrestore(&host->lock, flags);
829}
830
831static const struct mmc_host_ops msmsdcc_ops = {
832 .request = msmsdcc_request,
833 .set_ios = msmsdcc_set_ios,
834 .enable_sdio_irq = msmsdcc_enable_sdio_irq,
835};
836
837static void
838msmsdcc_check_status(unsigned long data)
839{
840 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
841 unsigned int status;
842
843 if (!host->plat->status) {
844 mmc_detect_change(host->mmc, 0);
845 goto out;
846 }
847
848 status = host->plat->status(mmc_dev(host->mmc));
849 host->eject = !status;
850 if (status ^ host->oldstat) {
851 printk(KERN_INFO
852 "%s: Slot status change detected (%d -> %d)\n",
853 mmc_hostname(host->mmc), host->oldstat, status);
854 if (status)
855 mmc_detect_change(host->mmc, (5 * HZ) / 2);
856 else
857 mmc_detect_change(host->mmc, 0);
858 }
859
860 host->oldstat = status;
861
862out:
863 if (host->timer.function)
864 mod_timer(&host->timer, jiffies + HZ);
865}
866
867static irqreturn_t
868msmsdcc_platform_status_irq(int irq, void *dev_id)
869{
870 struct msmsdcc_host *host = dev_id;
871
872 printk(KERN_DEBUG "%s: %d\n", __func__, irq);
873 msmsdcc_check_status((unsigned long) host);
874 return IRQ_HANDLED;
875}
876
877static void
878msmsdcc_status_notify_cb(int card_present, void *dev_id)
879{
880 struct msmsdcc_host *host = dev_id;
881
882 printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
883 card_present);
884 msmsdcc_check_status((unsigned long) host);
885}
886
887/*
888 * called when a command expires.
889 * Dump some debugging, and then error
890 * out the transaction.
891 */
892static void
893msmsdcc_command_expired(unsigned long _data)
894{
895 struct msmsdcc_host *host = (struct msmsdcc_host *) _data;
896 struct mmc_request *mrq;
897 unsigned long flags;
898
899 spin_lock_irqsave(&host->lock, flags);
900 mrq = host->curr.mrq;
901
902 if (!mrq) {
903 printk(KERN_INFO "%s: Command expiry misfire\n",
904 mmc_hostname(host->mmc));
905 spin_unlock_irqrestore(&host->lock, flags);
906 return;
907 }
908
909 printk(KERN_ERR "%s: Command timeout (%p %p %p %p)\n",
910 mmc_hostname(host->mmc), mrq, mrq->cmd,
911 mrq->data, host->dma.sg);
912
913 mrq->cmd->error = -ETIMEDOUT;
914 msmsdcc_stop_data(host);
915
916 writel(0, host->base + MMCICOMMAND);
917
918 host->curr.mrq = NULL;
919 host->curr.cmd = NULL;
920
921 spin_unlock_irqrestore(&host->lock, flags);
922 mmc_request_done(host->mmc, mrq);
923}
924
925static int
926msmsdcc_init_dma(struct msmsdcc_host *host)
927{
928 memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
929 host->dma.host = host;
930 host->dma.channel = -1;
931
932 if (!host->dmares)
933 return -ENODEV;
934
935 host->dma.nc = dma_alloc_coherent(NULL,
936 sizeof(struct msmsdcc_nc_dmadata),
937 &host->dma.nc_busaddr,
938 GFP_KERNEL);
939 if (host->dma.nc == NULL) {
940 printk(KERN_ERR "Unable to allocate DMA buffer\n");
941 return -ENOMEM;
942 }
943 memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
944 host->dma.cmd_busaddr = host->dma.nc_busaddr;
945 host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
946 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
947 host->dma.channel = host->dmares->start;
948
949 return 0;
950}
951
952#ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
953static void
954do_resume_work(struct work_struct *work)
955{
956 struct msmsdcc_host *host =
957 container_of(work, struct msmsdcc_host, resume_task);
958 struct mmc_host *mmc = host->mmc;
959
960 if (mmc) {
961 mmc_resume_host(mmc);
962 if (host->stat_irq)
963 enable_irq(host->stat_irq);
964 }
965}
966#endif
967
968static int
969msmsdcc_probe(struct platform_device *pdev)
970{
971 struct mmc_platform_data *plat = pdev->dev.platform_data;
972 struct msmsdcc_host *host;
973 struct mmc_host *mmc;
974 struct resource *cmd_irqres = NULL;
975 struct resource *pio_irqres = NULL;
976 struct resource *stat_irqres = NULL;
977 struct resource *memres = NULL;
978 struct resource *dmares = NULL;
979 int ret;
980
981 /* must have platform data */
982 if (!plat) {
983 printk(KERN_ERR "%s: Platform data not available\n", __func__);
984 ret = -EINVAL;
985 goto out;
986 }
987
988 if (pdev->id < 1 || pdev->id > 4)
989 return -EINVAL;
990
991 if (pdev->resource == NULL || pdev->num_resources < 2) {
992 printk(KERN_ERR "%s: Invalid resource\n", __func__);
993 return -ENXIO;
994 }
995
996 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
997 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
998 cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
999 "cmd_irq");
1000 pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1001 "pio_irq");
1002 stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1003 "status_irq");
1004
1005 if (!cmd_irqres || !pio_irqres || !memres) {
1006 printk(KERN_ERR "%s: Invalid resource\n", __func__);
1007 return -ENXIO;
1008 }
1009
1010 /*
1011 * Setup our host structure
1012 */
1013
1014 mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1015 if (!mmc) {
1016 ret = -ENOMEM;
1017 goto out;
1018 }
1019
1020 host = mmc_priv(mmc);
1021 host->pdev_id = pdev->id;
1022 host->plat = plat;
1023 host->mmc = mmc;
1024
1025 host->cmdpoll = 1;
1026
1027 host->base = ioremap(memres->start, PAGE_SIZE);
1028 if (!host->base) {
1029 ret = -ENOMEM;
1030 goto out;
1031 }
1032
1033 host->cmd_irqres = cmd_irqres;
1034 host->pio_irqres = pio_irqres;
1035 host->memres = memres;
1036 host->dmares = dmares;
1037 spin_lock_init(&host->lock);
1038
1039 /*
1040 * Setup DMA
1041 */
1042 msmsdcc_init_dma(host);
1043
1044 /*
1045 * Setup main peripheral bus clock
1046 */
1047 host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1048 if (IS_ERR(host->pclk)) {
1049 ret = PTR_ERR(host->pclk);
1050 goto host_free;
1051 }
1052
1053 ret = clk_enable(host->pclk);
1054 if (ret)
1055 goto pclk_put;
1056
1057 host->pclk_rate = clk_get_rate(host->pclk);
1058
1059 /*
1060 * Setup SDC MMC clock
1061 */
1062 host->clk = clk_get(&pdev->dev, "sdc_clk");
1063 if (IS_ERR(host->clk)) {
1064 ret = PTR_ERR(host->clk);
1065 goto pclk_disable;
1066 }
1067
1068 ret = clk_enable(host->clk);
1069 if (ret)
1070 goto clk_put;
1071
1072 ret = clk_set_rate(host->clk, msmsdcc_fmin);
1073 if (ret) {
1074 printk(KERN_ERR "%s: Clock rate set failed (%d)\n",
1075 __func__, ret);
1076 goto clk_disable;
1077 }
1078
1079 host->clk_rate = clk_get_rate(host->clk);
1080
1081 host->clks_on = 1;
1082
1083 /*
1084 * Setup MMC host structure
1085 */
1086 mmc->ops = &msmsdcc_ops;
1087 mmc->f_min = msmsdcc_fmin;
1088 mmc->f_max = msmsdcc_fmax;
1089 mmc->ocr_avail = plat->ocr_mask;
1090
1091 if (msmsdcc_4bit)
1092 mmc->caps |= MMC_CAP_4_BIT_DATA;
1093 if (msmsdcc_sdioirq)
1094 mmc->caps |= MMC_CAP_SDIO_IRQ;
1095 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1096
1097 mmc->max_phys_segs = NR_SG;
1098 mmc->max_hw_segs = NR_SG;
1099 mmc->max_blk_size = 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1100 mmc->max_blk_count = 65536;
1101
1102 mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */
1103 mmc->max_seg_size = mmc->max_req_size;
1104
1105 writel(0, host->base + MMCIMASK0);
1106 writel(0x5e007ff, host->base + MMCICLEAR); /* Add: 1 << 25 */
1107
1108 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1109 host->saved_irq0mask = MCI_IRQENABLE;
1110
1111 /*
1112 * Setup card detect change
1113 */
1114
1115 memset(&host->timer, 0, sizeof(host->timer));
1116
1117 if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1118 unsigned long irqflags = IRQF_SHARED |
1119 (stat_irqres->flags & IRQF_TRIGGER_MASK);
1120
1121 host->stat_irq = stat_irqres->start;
1122 ret = request_irq(host->stat_irq,
1123 msmsdcc_platform_status_irq,
1124 irqflags,
1125 DRIVER_NAME " (slot)",
1126 host);
1127 if (ret) {
1128 printk(KERN_ERR "Unable to get slot IRQ %d (%d)\n",
1129 host->stat_irq, ret);
1130 goto clk_disable;
1131 }
1132 } else if (plat->register_status_notify) {
1133 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1134 } else if (!plat->status)
1135 printk(KERN_ERR "%s: No card detect facilities available\n",
1136 mmc_hostname(mmc));
1137 else {
1138 init_timer(&host->timer);
1139 host->timer.data = (unsigned long)host;
1140 host->timer.function = msmsdcc_check_status;
1141 host->timer.expires = jiffies + HZ;
1142 add_timer(&host->timer);
1143 }
1144
1145 if (plat->status) {
1146 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1147 host->eject = !host->oldstat;
1148 }
1149
1150 /*
1151 * Setup a command timer. We currently need this due to
1152 * some 'strange' timeout / error handling situations.
1153 */
1154 init_timer(&host->command_timer);
1155 host->command_timer.data = (unsigned long) host;
1156 host->command_timer.function = msmsdcc_command_expired;
1157
1158 ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1159 DRIVER_NAME " (cmd)", host);
1160 if (ret)
1161 goto stat_irq_free;
1162
1163 ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1164 DRIVER_NAME " (pio)", host);
1165 if (ret)
1166 goto cmd_irq_free;
1167
1168 mmc_set_drvdata(pdev, mmc);
1169 mmc_add_host(mmc);
1170
1171 printk(KERN_INFO
1172 "%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1173 mmc_hostname(mmc), (unsigned long long)memres->start,
1174 (unsigned int) cmd_irqres->start,
1175 (unsigned int) host->stat_irq, host->dma.channel);
1176 printk(KERN_INFO "%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1177 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1178 printk(KERN_INFO "%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1179 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1180 printk(KERN_INFO "%s: Slot eject status = %d\n", mmc_hostname(mmc),
1181 host->eject);
1182 printk(KERN_INFO "%s: Power save feature enable = %d\n",
1183 mmc_hostname(mmc), msmsdcc_pwrsave);
1184
1185 if (host->dma.channel != -1) {
1186 printk(KERN_INFO
1187 "%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1188 mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1189 printk(KERN_INFO
1190 "%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1191 mmc_hostname(mmc), host->dma.cmd_busaddr,
1192 host->dma.cmdptr_busaddr);
1193 } else
1194 printk(KERN_INFO
1195 "%s: PIO transfer enabled\n", mmc_hostname(mmc));
1196 if (host->timer.function)
1197 printk(KERN_INFO "%s: Polling status mode enabled\n",
1198 mmc_hostname(mmc));
1199
1200 return 0;
1201 cmd_irq_free:
1202 free_irq(cmd_irqres->start, host);
1203 stat_irq_free:
1204 if (host->stat_irq)
1205 free_irq(host->stat_irq, host);
1206 clk_disable:
1207 clk_disable(host->clk);
1208 clk_put:
1209 clk_put(host->clk);
1210 pclk_disable:
1211 clk_disable(host->pclk);
1212 pclk_put:
1213 clk_put(host->pclk);
1214 host_free:
1215 mmc_free_host(mmc);
1216 out:
1217 return ret;
1218}
1219
1220static int
1221msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1222{
1223 struct mmc_host *mmc = mmc_get_drvdata(dev);
1224 int rc = 0;
1225
1226 if (mmc) {
1227 struct msmsdcc_host *host = mmc_priv(mmc);
1228
1229 if (host->stat_irq)
1230 disable_irq(host->stat_irq);
1231
1232 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1233 rc = mmc_suspend_host(mmc, state);
1234 if (!rc) {
1235 writel(0, host->base + MMCIMASK0);
1236
1237 if (host->clks_on) {
1238 clk_disable(host->clk);
1239 clk_disable(host->pclk);
1240 host->clks_on = 0;
1241 }
1242 }
1243 }
1244 return rc;
1245}
1246
1247static int
1248msmsdcc_resume(struct platform_device *dev)
1249{
1250 struct mmc_host *mmc = mmc_get_drvdata(dev);
1251 unsigned long flags;
1252
1253 if (mmc) {
1254 struct msmsdcc_host *host = mmc_priv(mmc);
1255
1256 spin_lock_irqsave(&host->lock, flags);
1257
1258 if (!host->clks_on) {
1259 clk_enable(host->pclk);
1260 clk_enable(host->clk);
1261 host->clks_on = 1;
1262 }
1263
1264 writel(host->saved_irq0mask, host->base + MMCIMASK0);
1265
1266 spin_unlock_irqrestore(&host->lock, flags);
1267
1268 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1269 mmc_resume_host(mmc);
1270 if (host->stat_irq)
1271 enable_irq(host->stat_irq);
1272 else if (host->stat_irq)
1273 enable_irq(host->stat_irq);
1274 }
1275 return 0;
1276}
1277
1278static struct platform_driver msmsdcc_driver = {
1279 .probe = msmsdcc_probe,
1280 .suspend = msmsdcc_suspend,
1281 .resume = msmsdcc_resume,
1282 .driver = {
1283 .name = "msm_sdcc",
1284 },
1285};
1286
1287static int __init msmsdcc_init(void)
1288{
1289 return platform_driver_register(&msmsdcc_driver);
1290}
1291
1292static void __exit msmsdcc_exit(void)
1293{
1294 platform_driver_unregister(&msmsdcc_driver);
1295}
1296
1297module_init(msmsdcc_init);
1298module_exit(msmsdcc_exit);
1299
1300MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1301MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
new file mode 100644
index 000000000000..8c8448469811
--- /dev/null
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -0,0 +1,238 @@
1/*
2 * linux/drivers/mmc/host/msmsdcc.h - QCT MSM7K SDC Controller
3 *
4 * Copyright (C) 2008 Google, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * - Based on mmci.h
11 */
12
13#ifndef _MSM_SDCC_H
14#define _MSM_SDCC_H
15
16#define MSMSDCC_CRCI_SDC1 6
17#define MSMSDCC_CRCI_SDC2 7
18#define MSMSDCC_CRCI_SDC3 12
19#define MSMSDCC_CRCI_SDC4 13
20
21#define MMCIPOWER 0x000
22#define MCI_PWR_OFF 0x00
23#define MCI_PWR_UP 0x02
24#define MCI_PWR_ON 0x03
25#define MCI_OD (1 << 6)
26
27#define MMCICLOCK 0x004
28#define MCI_CLK_ENABLE (1 << 8)
29#define MCI_CLK_PWRSAVE (1 << 9)
30#define MCI_CLK_WIDEBUS (1 << 10)
31#define MCI_CLK_FLOWENA (1 << 12)
32#define MCI_CLK_INVERTOUT (1 << 13)
33#define MCI_CLK_SELECTIN (1 << 14)
34
35#define MMCIARGUMENT 0x008
36#define MMCICOMMAND 0x00c
37#define MCI_CPSM_RESPONSE (1 << 6)
38#define MCI_CPSM_LONGRSP (1 << 7)
39#define MCI_CPSM_INTERRUPT (1 << 8)
40#define MCI_CPSM_PENDING (1 << 9)
41#define MCI_CPSM_ENABLE (1 << 10)
42#define MCI_CPSM_PROGENA (1 << 11)
43#define MCI_CSPM_DATCMD (1 << 12)
44#define MCI_CSPM_MCIABORT (1 << 13)
45#define MCI_CSPM_CCSENABLE (1 << 14)
46#define MCI_CSPM_CCSDISABLE (1 << 15)
47
48
49#define MMCIRESPCMD 0x010
50#define MMCIRESPONSE0 0x014
51#define MMCIRESPONSE1 0x018
52#define MMCIRESPONSE2 0x01c
53#define MMCIRESPONSE3 0x020
54#define MMCIDATATIMER 0x024
55#define MMCIDATALENGTH 0x028
56
57#define MMCIDATACTRL 0x02c
58#define MCI_DPSM_ENABLE (1 << 0)
59#define MCI_DPSM_DIRECTION (1 << 1)
60#define MCI_DPSM_MODE (1 << 2)
61#define MCI_DPSM_DMAENABLE (1 << 3)
62
63#define MMCIDATACNT 0x030
64#define MMCISTATUS 0x034
65#define MCI_CMDCRCFAIL (1 << 0)
66#define MCI_DATACRCFAIL (1 << 1)
67#define MCI_CMDTIMEOUT (1 << 2)
68#define MCI_DATATIMEOUT (1 << 3)
69#define MCI_TXUNDERRUN (1 << 4)
70#define MCI_RXOVERRUN (1 << 5)
71#define MCI_CMDRESPEND (1 << 6)
72#define MCI_CMDSENT (1 << 7)
73#define MCI_DATAEND (1 << 8)
74#define MCI_DATABLOCKEND (1 << 10)
75#define MCI_CMDACTIVE (1 << 11)
76#define MCI_TXACTIVE (1 << 12)
77#define MCI_RXACTIVE (1 << 13)
78#define MCI_TXFIFOHALFEMPTY (1 << 14)
79#define MCI_RXFIFOHALFFULL (1 << 15)
80#define MCI_TXFIFOFULL (1 << 16)
81#define MCI_RXFIFOFULL (1 << 17)
82#define MCI_TXFIFOEMPTY (1 << 18)
83#define MCI_RXFIFOEMPTY (1 << 19)
84#define MCI_TXDATAAVLBL (1 << 20)
85#define MCI_RXDATAAVLBL (1 << 21)
86#define MCI_SDIOINTR (1 << 22)
87#define MCI_PROGDONE (1 << 23)
88#define MCI_ATACMDCOMPL (1 << 24)
89#define MCI_SDIOINTOPER (1 << 25)
90#define MCI_CCSTIMEOUT (1 << 26)
91
92#define MMCICLEAR 0x038
93#define MCI_CMDCRCFAILCLR (1 << 0)
94#define MCI_DATACRCFAILCLR (1 << 1)
95#define MCI_CMDTIMEOUTCLR (1 << 2)
96#define MCI_DATATIMEOUTCLR (1 << 3)
97#define MCI_TXUNDERRUNCLR (1 << 4)
98#define MCI_RXOVERRUNCLR (1 << 5)
99#define MCI_CMDRESPENDCLR (1 << 6)
100#define MCI_CMDSENTCLR (1 << 7)
101#define MCI_DATAENDCLR (1 << 8)
102#define MCI_DATABLOCKENDCLR (1 << 10)
103
104#define MMCIMASK0 0x03c
105#define MCI_CMDCRCFAILMASK (1 << 0)
106#define MCI_DATACRCFAILMASK (1 << 1)
107#define MCI_CMDTIMEOUTMASK (1 << 2)
108#define MCI_DATATIMEOUTMASK (1 << 3)
109#define MCI_TXUNDERRUNMASK (1 << 4)
110#define MCI_RXOVERRUNMASK (1 << 5)
111#define MCI_CMDRESPENDMASK (1 << 6)
112#define MCI_CMDSENTMASK (1 << 7)
113#define MCI_DATAENDMASK (1 << 8)
114#define MCI_DATABLOCKENDMASK (1 << 10)
115#define MCI_CMDACTIVEMASK (1 << 11)
116#define MCI_TXACTIVEMASK (1 << 12)
117#define MCI_RXACTIVEMASK (1 << 13)
118#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
119#define MCI_RXFIFOHALFFULLMASK (1 << 15)
120#define MCI_TXFIFOFULLMASK (1 << 16)
121#define MCI_RXFIFOFULLMASK (1 << 17)
122#define MCI_TXFIFOEMPTYMASK (1 << 18)
123#define MCI_RXFIFOEMPTYMASK (1 << 19)
124#define MCI_TXDATAAVLBLMASK (1 << 20)
125#define MCI_RXDATAAVLBLMASK (1 << 21)
126#define MCI_SDIOINTMASK (1 << 22)
127#define MCI_PROGDONEMASK (1 << 23)
128#define MCI_ATACMDCOMPLMASK (1 << 24)
129#define MCI_SDIOINTOPERMASK (1 << 25)
130#define MCI_CCSTIMEOUTMASK (1 << 26)
131
132#define MMCIMASK1 0x040
133#define MMCIFIFOCNT 0x044
134#define MCICCSTIMER 0x058
135
136#define MMCIFIFO 0x080 /* to 0x0bc */
137
138#define MCI_IRQENABLE \
139 (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
140 MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
141 MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATAENDMASK)
142
143/*
144 * The size of the FIFO in bytes.
145 */
146#define MCI_FIFOSIZE (16*4)
147
148#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
149
150#define NR_SG 32
151
152struct clk;
153
154struct msmsdcc_nc_dmadata {
155 dmov_box cmd[NR_SG];
156 uint32_t cmdptr;
157};
158
159struct msmsdcc_dma_data {
160 struct msmsdcc_nc_dmadata *nc;
161 dma_addr_t nc_busaddr;
162 dma_addr_t cmd_busaddr;
163 dma_addr_t cmdptr_busaddr;
164
165 struct msm_dmov_cmd hdr;
166 enum dma_data_direction dir;
167
168 struct scatterlist *sg;
169 int num_ents;
170
171 int channel;
172 struct msmsdcc_host *host;
173 int busy; /* Set if DM is busy */
174};
175
176struct msmsdcc_pio_data {
177 struct scatterlist *sg;
178 unsigned int sg_len;
179 unsigned int sg_off;
180};
181
182struct msmsdcc_curr_req {
183 struct mmc_request *mrq;
184 struct mmc_command *cmd;
185 struct mmc_data *data;
186 unsigned int xfer_size; /* Total data size */
187 unsigned int xfer_remain; /* Bytes remaining to send */
188 unsigned int data_xfered; /* Bytes acked by BLKEND irq */
189 int got_dataend;
190 int got_datablkend;
191 int user_pages;
192};
193
194struct msmsdcc_stats {
195 unsigned int reqs;
196 unsigned int cmds;
197 unsigned int cmdpoll_hits;
198 unsigned int cmdpoll_misses;
199};
200
201struct msmsdcc_host {
202 struct resource *cmd_irqres;
203 struct resource *pio_irqres;
204 struct resource *memres;
205 struct resource *dmares;
206 void __iomem *base;
207 int pdev_id;
208 unsigned int stat_irq;
209
210 struct msmsdcc_curr_req curr;
211
212 struct mmc_host *mmc;
213 struct clk *clk; /* main MMC bus clock */
214 struct clk *pclk; /* SDCC peripheral bus clock */
215 unsigned int clks_on; /* set if clocks are enabled */
216 struct timer_list command_timer;
217
218 unsigned int eject; /* eject state */
219
220 spinlock_t lock;
221
222 unsigned int clk_rate; /* Current clock rate */
223 unsigned int pclk_rate;
224
225 u32 pwr;
226 u32 saved_irq0mask; /* MMCIMASK0 reg value */
227 struct mmc_platform_data *plat;
228
229 struct timer_list timer;
230 unsigned int oldstat;
231
232 struct msmsdcc_dma_data dma;
233 struct msmsdcc_pio_data pio;
234 int cmdpoll;
235 struct msmsdcc_stats stats;
236};
237
238#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 01:48:57 -0500