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authorUlf Hansson <ulf.hansson@linaro.org>2014-11-25 07:05:13 -0500
committerUlf Hansson <ulf.hansson@linaro.org>2014-11-26 08:40:39 -0500
commit903101a83949d6fc77c092cef07e9c1e10c07e46 (patch)
treecbe49cd9bf780ae112300069846d0952bbfafb0d /drivers/mmc
parent996903de92f0c7a32d8c83f37d7ebcea0def8660 (diff)
mmc: omap_hsmmc: Fix UHS card with DDR50 support
The commit, mmc: omap: clarify DDR timing mode between SD-UHS and eMMC, switched omap_hsmmc to support MMC DDR mode instead of UHS DDR50 mode. Add UHS DDR50 mode again and this time let's also keep the MMC DDR mode. Fixes: 5438ad95a57c (mmc: omap: clarify DDR timing mode between SD-UHS and eMMC) Reported-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/omap_hsmmc.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 82b40b85293f..7c71dcdcba8b 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -628,6 +628,7 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
628 */ 628 */
629 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 629 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
630 (ios->timing != MMC_TIMING_MMC_DDR52) && 630 (ios->timing != MMC_TIMING_MMC_DDR52) &&
631 (ios->timing != MMC_TIMING_UHS_DDR50) &&
631 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 632 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
632 regval = OMAP_HSMMC_READ(host->base, HCTL); 633 regval = OMAP_HSMMC_READ(host->base, HCTL);
633 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 634 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
@@ -647,7 +648,8 @@ static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
647 u32 con; 648 u32 con;
648 649
649 con = OMAP_HSMMC_READ(host->base, CON); 650 con = OMAP_HSMMC_READ(host->base, CON);
650 if (ios->timing == MMC_TIMING_MMC_DDR52) 651 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
652 ios->timing == MMC_TIMING_UHS_DDR50)
651 con |= DDR; /* configure in DDR mode */ 653 con |= DDR; /* configure in DDR mode */
652 else 654 else
653 con &= ~DDR; 655 con &= ~DDR;