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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-11 16:56:38 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-11 16:56:38 -0500
commit6a5971d8fea1f4a8c33dfe0cec6a1c490f0c9cde (patch)
tree982911522177da03dd839d816a6a93cc210e4657 /drivers/mmc
parentcff2f741b8ee8a70b208830e330de053efd4fc45 (diff)
parent70e78c40ed6c25bb34d642848e485d79ffc55c26 (diff)
Merge tag 'char-misc-3.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull Char/Misc driver merge from Greg Kroah-Hartman: "Here is the "big" char/misc driver patches for 3.8-rc1. I'm starting to put random driver subsystems that I had previously sent you through the driver-core tree in this tree, as it makes more sense to do so. Nothing major here, the various __dev* removals, some mei driver updates, and other random driver-specific things from the different maintainers and developers. Note, some MFD drivers got added through this tree, and they are also coming in through the "real" MFD tree as well, due to some major mis-communication between me and the different developers. If you have any merge conflicts, take the ones from the MFD tree, not these ones, sorry about that. All of this has been in linux-next for a while. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>" Fix up trivial conflict in drivers/mmc/host/Kconfig due to new drivers having been added (both at the end, as usual..) * tag 'char-misc-3.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (84 commits) MAINTAINERS: remove drivers/staging/hv/ misc/st_kim: Free resources in the error path of probe() drivers/char: for hpet, add count checking, and ~0UL instead of -1 w1-gpio: Simplify & get rid of defines w1-gpio: Pinctrl-fy extcon: remove use of __devexit_p extcon: remove use of __devinit extcon: remove use of __devexit drivers: uio: Only allocate new private data when probing device tree node drivers: uio_dmem_genirq: Allow partial success when opening device drivers: uio_dmem_genirq: Don't use DMA_ERROR_CODE to indicate unmapped regions drivers: uio_dmem_genirq: Don't mix address spaces for dynamic region vaddr uio: remove use of __devexit uio: remove use of __devinitdata uio: remove use of __devinit uio: remove use of __devexit_p char: remove use of __devexit char: remove use of __devinitconst char: remove use of __devinitdata char: remove use of __devinit ...
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/Kconfig7
-rw-r--r--drivers/mmc/host/Makefile2
-rw-r--r--drivers/mmc/host/rtsx_pci_sdmmc.c1348
3 files changed, 1357 insertions, 0 deletions
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index bebbe167fd89..737e4edc241b 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -624,3 +624,10 @@ config MMC_WMT
624 624
625 To compile this driver as a module, choose M here: the 625 To compile this driver as a module, choose M here: the
626 module will be called wmt-sdmmc. 626 module will be called wmt-sdmmc.
627
628config MMC_REALTEK_PCI
629 tristate "Realtek PCI-E SD/MMC Card Interface Driver"
630 depends on MFD_RTSX_PCI
631 help
632 Say Y here to include driver code to support SD/MMC card interface
633 of Realtek PCI-E card reader
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index c5eddc1b4833..b648058d7182 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -47,6 +47,8 @@ obj-$(CONFIG_MMC_VUB300) += vub300.o
47obj-$(CONFIG_MMC_USHC) += ushc.o 47obj-$(CONFIG_MMC_USHC) += ushc.o
48obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o 48obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
49 49
50obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
51
50obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o 52obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
51obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o 53obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o
52obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o 54obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c
new file mode 100644
index 000000000000..12eff6f8cab7
--- /dev/null
+++ b/drivers/mmc/host/rtsx_pci_sdmmc.c
@@ -0,0 +1,1348 @@
1/* Realtek PCI-Express SD/MMC Card Interface driver
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/module.h>
24#include <linux/highmem.h>
25#include <linux/delay.h>
26#include <linux/platform_device.h>
27#include <linux/mmc/host.h>
28#include <linux/mmc/mmc.h>
29#include <linux/mmc/sd.h>
30#include <linux/mmc/card.h>
31#include <linux/mfd/rtsx_pci.h>
32#include <asm/unaligned.h>
33
34/* SD Tuning Data Structure
35 * Record continuous timing phase path
36 */
37struct timing_phase_path {
38 int start;
39 int end;
40 int mid;
41 int len;
42};
43
44struct realtek_pci_sdmmc {
45 struct platform_device *pdev;
46 struct rtsx_pcr *pcr;
47 struct mmc_host *mmc;
48 struct mmc_request *mrq;
49
50 struct mutex host_mutex;
51
52 u8 ssc_depth;
53 unsigned int clock;
54 bool vpclk;
55 bool double_clk;
56 bool eject;
57 bool initial_mode;
58 bool ddr_mode;
59};
60
61static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
62{
63 return &(host->pdev->dev);
64}
65
66static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
67{
68 rtsx_pci_write_register(host->pcr, CARD_STOP,
69 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
70}
71
72#ifdef DEBUG
73static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
74{
75 struct rtsx_pcr *pcr = host->pcr;
76 u16 i;
77 u8 *ptr;
78
79 /* Print SD host internal registers */
80 rtsx_pci_init_cmd(pcr);
81 for (i = 0xFDA0; i <= 0xFDAE; i++)
82 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
83 for (i = 0xFD52; i <= 0xFD69; i++)
84 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
85 rtsx_pci_send_cmd(pcr, 100);
86
87 ptr = rtsx_pci_get_cmd_data(pcr);
88 for (i = 0xFDA0; i <= 0xFDAE; i++)
89 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
90 for (i = 0xFD52; i <= 0xFD69; i++)
91 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
92}
93#else
94#define sd_print_debug_regs(host)
95#endif /* DEBUG */
96
97static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
98 u8 *buf, int buf_len, int timeout)
99{
100 struct rtsx_pcr *pcr = host->pcr;
101 int err, i;
102 u8 trans_mode;
103
104 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
105
106 if (!buf)
107 buf_len = 0;
108
109 if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
110 trans_mode = SD_TM_AUTO_TUNING;
111 else
112 trans_mode = SD_TM_NORMAL_READ;
113
114 rtsx_pci_init_cmd(pcr);
115
116 for (i = 0; i < 5; i++)
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
118
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
121 0xFF, (u8)(byte_cnt >> 8));
122 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
123 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
124
125 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
126 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
127 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
128 if (trans_mode != SD_TM_AUTO_TUNING)
129 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
130 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
131
132 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
133 0xFF, trans_mode | SD_TRANSFER_START);
134 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
135 SD_TRANSFER_END, SD_TRANSFER_END);
136
137 err = rtsx_pci_send_cmd(pcr, timeout);
138 if (err < 0) {
139 sd_print_debug_regs(host);
140 dev_dbg(sdmmc_dev(host),
141 "rtsx_pci_send_cmd fail (err = %d)\n", err);
142 return err;
143 }
144
145 if (buf && buf_len) {
146 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
147 if (err < 0) {
148 dev_dbg(sdmmc_dev(host),
149 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
150 return err;
151 }
152 }
153
154 return 0;
155}
156
157static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
158 u8 *buf, int buf_len, int timeout)
159{
160 struct rtsx_pcr *pcr = host->pcr;
161 int err, i;
162 u8 trans_mode;
163
164 if (!buf)
165 buf_len = 0;
166
167 if (buf && buf_len) {
168 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
169 if (err < 0) {
170 dev_dbg(sdmmc_dev(host),
171 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
172 return err;
173 }
174 }
175
176 trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
177 rtsx_pci_init_cmd(pcr);
178
179 if (cmd) {
180 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
181 cmd[0] - 0x40);
182
183 for (i = 0; i < 5; i++)
184 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
185 SD_CMD0 + i, 0xFF, cmd[i]);
186 }
187
188 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
189 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
190 0xFF, (u8)(byte_cnt >> 8));
191 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
192 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
193
194 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
195 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
196 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
197
198 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
199 trans_mode | SD_TRANSFER_START);
200 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
201 SD_TRANSFER_END, SD_TRANSFER_END);
202
203 err = rtsx_pci_send_cmd(pcr, timeout);
204 if (err < 0) {
205 sd_print_debug_regs(host);
206 dev_dbg(sdmmc_dev(host),
207 "rtsx_pci_send_cmd fail (err = %d)\n", err);
208 return err;
209 }
210
211 return 0;
212}
213
214static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
215 struct mmc_command *cmd)
216{
217 struct rtsx_pcr *pcr = host->pcr;
218 u8 cmd_idx = (u8)cmd->opcode;
219 u32 arg = cmd->arg;
220 int err = 0;
221 int timeout = 100;
222 int i;
223 u8 *ptr;
224 int stat_idx = 0;
225 u8 rsp_type;
226 int rsp_len = 5;
227
228 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
229 __func__, cmd_idx, arg);
230
231 /* Response type:
232 * R0
233 * R1, R5, R6, R7
234 * R1b
235 * R2
236 * R3, R4
237 */
238 switch (mmc_resp_type(cmd)) {
239 case MMC_RSP_NONE:
240 rsp_type = SD_RSP_TYPE_R0;
241 rsp_len = 0;
242 break;
243 case MMC_RSP_R1:
244 rsp_type = SD_RSP_TYPE_R1;
245 break;
246 case MMC_RSP_R1B:
247 rsp_type = SD_RSP_TYPE_R1b;
248 break;
249 case MMC_RSP_R2:
250 rsp_type = SD_RSP_TYPE_R2;
251 rsp_len = 16;
252 break;
253 case MMC_RSP_R3:
254 rsp_type = SD_RSP_TYPE_R3;
255 break;
256 default:
257 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
258 err = -EINVAL;
259 goto out;
260 }
261
262 if (rsp_type == SD_RSP_TYPE_R1b)
263 timeout = 3000;
264
265 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
266 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
267 0xFF, SD_CLK_TOGGLE_EN);
268 if (err < 0)
269 goto out;
270 }
271
272 rtsx_pci_init_cmd(pcr);
273
274 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
275 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
276 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
277 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
278 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
279
280 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
281 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
282 0x01, PINGPONG_BUFFER);
283 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
284 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
285 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
286 SD_TRANSFER_END | SD_STAT_IDLE,
287 SD_TRANSFER_END | SD_STAT_IDLE);
288
289 if (rsp_type == SD_RSP_TYPE_R2) {
290 /* Read data from ping-pong buffer */
291 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
292 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
293 stat_idx = 16;
294 } else if (rsp_type != SD_RSP_TYPE_R0) {
295 /* Read data from SD_CMDx registers */
296 for (i = SD_CMD0; i <= SD_CMD4; i++)
297 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
298 stat_idx = 5;
299 }
300
301 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
302
303 err = rtsx_pci_send_cmd(pcr, timeout);
304 if (err < 0) {
305 sd_print_debug_regs(host);
306 sd_clear_error(host);
307 dev_dbg(sdmmc_dev(host),
308 "rtsx_pci_send_cmd error (err = %d)\n", err);
309 goto out;
310 }
311
312 if (rsp_type == SD_RSP_TYPE_R0) {
313 err = 0;
314 goto out;
315 }
316
317 /* Eliminate returned value of CHECK_REG_CMD */
318 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
319
320 /* Check (Start,Transmission) bit of Response */
321 if ((ptr[0] & 0xC0) != 0) {
322 err = -EILSEQ;
323 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
324 goto out;
325 }
326
327 /* Check CRC7 */
328 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
329 if (ptr[stat_idx] & SD_CRC7_ERR) {
330 err = -EILSEQ;
331 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
332 goto out;
333 }
334 }
335
336 if (rsp_type == SD_RSP_TYPE_R2) {
337 for (i = 0; i < 4; i++) {
338 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
339 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
340 i, cmd->resp[i]);
341 }
342 } else {
343 cmd->resp[0] = get_unaligned_be32(ptr + 1);
344 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
345 cmd->resp[0]);
346 }
347
348out:
349 cmd->error = err;
350}
351
352static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
353{
354 struct rtsx_pcr *pcr = host->pcr;
355 struct mmc_host *mmc = host->mmc;
356 struct mmc_card *card = mmc->card;
357 struct mmc_data *data = mrq->data;
358 int uhs = mmc_sd_card_uhs(card);
359 int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
360 u8 cfg2, trans_mode;
361 int err;
362 size_t data_len = data->blksz * data->blocks;
363
364 if (read) {
365 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
366 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
367 trans_mode = SD_TM_AUTO_READ_3;
368 } else {
369 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
370 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
371 trans_mode = SD_TM_AUTO_WRITE_3;
372 }
373
374 if (!uhs)
375 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
376
377 rtsx_pci_init_cmd(pcr);
378
379 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
380 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
381 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
382 0xFF, (u8)data->blocks);
383 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
384 0xFF, (u8)(data->blocks >> 8));
385 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
386 CARD_DATA_SOURCE, 0x01, RING_BUFFER);
387
388 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
389 DMA_DONE_INT, DMA_DONE_INT);
390 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
391 0xFF, (u8)(data_len >> 24));
392 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
393 0xFF, (u8)(data_len >> 16));
394 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
395 0xFF, (u8)(data_len >> 8));
396 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
397 if (read) {
398 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
399 0x03 | DMA_PACK_SIZE_MASK,
400 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
401 } else {
402 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
403 0x03 | DMA_PACK_SIZE_MASK,
404 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
405 }
406
407 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
408 0x01, RING_BUFFER);
409
410 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
411 trans_mode | SD_TRANSFER_START);
412 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
413 SD_TRANSFER_END, SD_TRANSFER_END);
414
415 rtsx_pci_send_cmd_no_wait(pcr);
416
417 err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000);
418 if (err < 0) {
419 sd_clear_error(host);
420 return err;
421 }
422
423 return 0;
424}
425
426static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
427{
428 rtsx_pci_write_register(host->pcr, SD_CFG1,
429 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
430}
431
432static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
433{
434 rtsx_pci_write_register(host->pcr, SD_CFG1,
435 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
436}
437
438static void sd_normal_rw(struct realtek_pci_sdmmc *host,
439 struct mmc_request *mrq)
440{
441 struct mmc_command *cmd = mrq->cmd;
442 struct mmc_data *data = mrq->data;
443 u8 _cmd[5], *buf;
444
445 _cmd[0] = 0x40 | (u8)cmd->opcode;
446 put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
447
448 buf = kzalloc(data->blksz, GFP_NOIO);
449 if (!buf) {
450 cmd->error = -ENOMEM;
451 return;
452 }
453
454 if (data->flags & MMC_DATA_READ) {
455 if (host->initial_mode)
456 sd_disable_initial_mode(host);
457
458 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
459 data->blksz, 200);
460
461 if (host->initial_mode)
462 sd_enable_initial_mode(host);
463
464 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
465 } else {
466 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
467
468 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
469 data->blksz, 200);
470 }
471
472 kfree(buf);
473}
474
475static int sd_change_phase(struct realtek_pci_sdmmc *host, u8 sample_point)
476{
477 struct rtsx_pcr *pcr = host->pcr;
478 int err;
479
480 dev_dbg(sdmmc_dev(host), "%s: sample_point = %d\n",
481 __func__, sample_point);
482
483 rtsx_pci_init_cmd(pcr);
484
485 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
486 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPRX_CTL, 0x1F, sample_point);
487 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
488 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
489 PHASE_NOT_RESET, PHASE_NOT_RESET);
490 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
491 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
492
493 err = rtsx_pci_send_cmd(pcr, 100);
494 if (err < 0)
495 return err;
496
497 return 0;
498}
499
500static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
501{
502 struct timing_phase_path path[MAX_PHASE + 1];
503 int i, j, cont_path_cnt;
504 int new_block, max_len, final_path_idx;
505 u8 final_phase = 0xFF;
506
507 /* Parse phase_map, take it as a bit-ring */
508 cont_path_cnt = 0;
509 new_block = 1;
510 j = 0;
511 for (i = 0; i < MAX_PHASE + 1; i++) {
512 if (phase_map & (1 << i)) {
513 if (new_block) {
514 new_block = 0;
515 j = cont_path_cnt++;
516 path[j].start = i;
517 path[j].end = i;
518 } else {
519 path[j].end = i;
520 }
521 } else {
522 new_block = 1;
523 if (cont_path_cnt) {
524 /* Calculate path length and middle point */
525 int idx = cont_path_cnt - 1;
526 path[idx].len =
527 path[idx].end - path[idx].start + 1;
528 path[idx].mid =
529 path[idx].start + path[idx].len / 2;
530 }
531 }
532 }
533
534 if (cont_path_cnt == 0) {
535 dev_dbg(sdmmc_dev(host), "No continuous phase path\n");
536 goto finish;
537 } else {
538 /* Calculate last continuous path length and middle point */
539 int idx = cont_path_cnt - 1;
540 path[idx].len = path[idx].end - path[idx].start + 1;
541 path[idx].mid = path[idx].start + path[idx].len / 2;
542 }
543
544 /* Connect the first and last continuous paths if they are adjacent */
545 if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
546 /* Using negative index */
547 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
548 path[0].len += path[cont_path_cnt - 1].len;
549 path[0].mid = path[0].start + path[0].len / 2;
550 /* Convert negative middle point index to positive one */
551 if (path[0].mid < 0)
552 path[0].mid += MAX_PHASE + 1;
553 cont_path_cnt--;
554 }
555
556 /* Choose the longest continuous phase path */
557 max_len = 0;
558 final_phase = 0;
559 final_path_idx = 0;
560 for (i = 0; i < cont_path_cnt; i++) {
561 if (path[i].len > max_len) {
562 max_len = path[i].len;
563 final_phase = (u8)path[i].mid;
564 final_path_idx = i;
565 }
566
567 dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n",
568 i, path[i].start);
569 dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n",
570 i, path[i].end);
571 dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n",
572 i, path[i].len);
573 dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n",
574 i, path[i].mid);
575 }
576
577finish:
578 dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase);
579 return final_phase;
580}
581
582static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
583{
584 int err, i;
585 u8 val = 0;
586
587 for (i = 0; i < 100; i++) {
588 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
589 if (val & SD_DATA_IDLE)
590 return;
591
592 udelay(100);
593 }
594}
595
596static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
597 u8 opcode, u8 sample_point)
598{
599 int err;
600 u8 cmd[5] = {0};
601
602 err = sd_change_phase(host, sample_point);
603 if (err < 0)
604 return err;
605
606 cmd[0] = 0x40 | opcode;
607 err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
608 if (err < 0) {
609 /* Wait till SD DATA IDLE */
610 sd_wait_data_idle(host);
611 sd_clear_error(host);
612 return err;
613 }
614
615 return 0;
616}
617
618static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
619 u8 opcode, u32 *phase_map)
620{
621 int err, i;
622 u32 raw_phase_map = 0;
623
624 for (i = MAX_PHASE; i >= 0; i--) {
625 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
626 if (err == 0)
627 raw_phase_map |= 1 << i;
628 }
629
630 if (phase_map)
631 *phase_map = raw_phase_map;
632
633 return 0;
634}
635
636static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
637{
638 int err, i;
639 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
640 u8 final_phase;
641
642 for (i = 0; i < RX_TUNING_CNT; i++) {
643 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
644 if (err < 0)
645 return err;
646
647 if (raw_phase_map[i] == 0)
648 break;
649 }
650
651 phase_map = 0xFFFFFFFF;
652 for (i = 0; i < RX_TUNING_CNT; i++) {
653 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
654 i, raw_phase_map[i]);
655 phase_map &= raw_phase_map[i];
656 }
657 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
658
659 if (phase_map) {
660 final_phase = sd_search_final_phase(host, phase_map);
661 if (final_phase == 0xFF)
662 return -EINVAL;
663
664 err = sd_change_phase(host, final_phase);
665 if (err < 0)
666 return err;
667 } else {
668 return -EINVAL;
669 }
670
671 return 0;
672}
673
674static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
675{
676 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
677 struct rtsx_pcr *pcr = host->pcr;
678 struct mmc_command *cmd = mrq->cmd;
679 struct mmc_data *data = mrq->data;
680 unsigned int data_size = 0;
681
682 if (host->eject) {
683 cmd->error = -ENOMEDIUM;
684 goto finish;
685 }
686
687 mutex_lock(&pcr->pcr_mutex);
688
689 rtsx_pci_start_run(pcr);
690
691 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
692 host->initial_mode, host->double_clk, host->vpclk);
693 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
694 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
695 CARD_SHARE_MASK, CARD_SHARE_48_SD);
696
697 mutex_lock(&host->host_mutex);
698 host->mrq = mrq;
699 mutex_unlock(&host->host_mutex);
700
701 if (mrq->data)
702 data_size = data->blocks * data->blksz;
703
704 if (!data_size || mmc_op_multi(cmd->opcode) ||
705 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
706 (cmd->opcode == MMC_WRITE_BLOCK)) {
707 sd_send_cmd_get_rsp(host, cmd);
708
709 if (!cmd->error && data_size) {
710 sd_rw_multi(host, mrq);
711
712 if (mmc_op_multi(cmd->opcode) && mrq->stop)
713 sd_send_cmd_get_rsp(host, mrq->stop);
714 }
715 } else {
716 sd_normal_rw(host, mrq);
717 }
718
719 if (mrq->data) {
720 if (cmd->error || data->error)
721 data->bytes_xfered = 0;
722 else
723 data->bytes_xfered = data->blocks * data->blksz;
724 }
725
726 mutex_unlock(&pcr->pcr_mutex);
727
728finish:
729 if (cmd->error)
730 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
731
732 mutex_lock(&host->host_mutex);
733 host->mrq = NULL;
734 mutex_unlock(&host->host_mutex);
735
736 mmc_request_done(mmc, mrq);
737}
738
739static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
740 unsigned char bus_width)
741{
742 int err = 0;
743 u8 width[] = {
744 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
745 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
746 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
747 };
748
749 if (bus_width <= MMC_BUS_WIDTH_8)
750 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
751 0x03, width[bus_width]);
752
753 return err;
754}
755
756static int sd_power_on(struct realtek_pci_sdmmc *host)
757{
758 struct rtsx_pcr *pcr = host->pcr;
759 int err;
760
761 rtsx_pci_init_cmd(pcr);
762 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
763 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
764 CARD_SHARE_MASK, CARD_SHARE_48_SD);
765 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
766 SD_CLK_EN, SD_CLK_EN);
767 err = rtsx_pci_send_cmd(pcr, 100);
768 if (err < 0)
769 return err;
770
771 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
772 if (err < 0)
773 return err;
774
775 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
776 if (err < 0)
777 return err;
778
779 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
780 if (err < 0)
781 return err;
782
783 return 0;
784}
785
786static int sd_power_off(struct realtek_pci_sdmmc *host)
787{
788 struct rtsx_pcr *pcr = host->pcr;
789 int err;
790
791 rtsx_pci_init_cmd(pcr);
792
793 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
794 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
795
796 err = rtsx_pci_send_cmd(pcr, 100);
797 if (err < 0)
798 return err;
799
800 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
801 if (err < 0)
802 return err;
803
804 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
805}
806
807static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
808 unsigned char power_mode)
809{
810 int err;
811
812 if (power_mode == MMC_POWER_OFF)
813 err = sd_power_off(host);
814 else
815 err = sd_power_on(host);
816
817 return err;
818}
819
820static int sd_set_timing(struct realtek_pci_sdmmc *host,
821 unsigned char timing, bool *ddr_mode)
822{
823 struct rtsx_pcr *pcr = host->pcr;
824 int err = 0;
825
826 *ddr_mode = false;
827
828 rtsx_pci_init_cmd(pcr);
829
830 switch (timing) {
831 case MMC_TIMING_UHS_SDR104:
832 case MMC_TIMING_UHS_SDR50:
833 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
834 0x0C | SD_ASYNC_FIFO_NOT_RST,
835 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
836 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
837 CLK_LOW_FREQ, CLK_LOW_FREQ);
838 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
839 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
840 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
841 break;
842
843 case MMC_TIMING_UHS_DDR50:
844 *ddr_mode = true;
845
846 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
847 0x0C | SD_ASYNC_FIFO_NOT_RST,
848 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
849 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
850 CLK_LOW_FREQ, CLK_LOW_FREQ);
851 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
852 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
853 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
854 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
855 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
856 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
857 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
858 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
859 break;
860
861 case MMC_TIMING_MMC_HS:
862 case MMC_TIMING_SD_HS:
863 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
864 0x0C, SD_20_MODE);
865 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
866 CLK_LOW_FREQ, CLK_LOW_FREQ);
867 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
868 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
869 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
870 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
871 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
872 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
873 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
874 break;
875
876 default:
877 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
878 SD_CFG1, 0x0C, SD_20_MODE);
879 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
880 CLK_LOW_FREQ, CLK_LOW_FREQ);
881 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
882 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
883 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
884 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
885 SD_PUSH_POINT_CTL, 0xFF, 0);
886 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
887 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
888 break;
889 }
890
891 err = rtsx_pci_send_cmd(pcr, 100);
892
893 return err;
894}
895
896static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
897{
898 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
899 struct rtsx_pcr *pcr = host->pcr;
900
901 if (host->eject)
902 return;
903
904 mutex_lock(&pcr->pcr_mutex);
905
906 rtsx_pci_start_run(pcr);
907
908 sd_set_bus_width(host, ios->bus_width);
909 sd_set_power_mode(host, ios->power_mode);
910 sd_set_timing(host, ios->timing, &host->ddr_mode);
911
912 host->vpclk = false;
913 host->double_clk = true;
914
915 switch (ios->timing) {
916 case MMC_TIMING_UHS_SDR104:
917 case MMC_TIMING_UHS_SDR50:
918 host->ssc_depth = RTSX_SSC_DEPTH_2M;
919 host->vpclk = true;
920 host->double_clk = false;
921 break;
922 case MMC_TIMING_UHS_DDR50:
923 case MMC_TIMING_UHS_SDR25:
924 host->ssc_depth = RTSX_SSC_DEPTH_1M;
925 break;
926 default:
927 host->ssc_depth = RTSX_SSC_DEPTH_500K;
928 break;
929 }
930
931 host->initial_mode = (ios->clock <= 1000000) ? true : false;
932
933 host->clock = ios->clock;
934 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
935 host->initial_mode, host->double_clk, host->vpclk);
936
937 mutex_unlock(&pcr->pcr_mutex);
938}
939
940static int sdmmc_get_ro(struct mmc_host *mmc)
941{
942 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
943 struct rtsx_pcr *pcr = host->pcr;
944 int ro = 0;
945 u32 val;
946
947 if (host->eject)
948 return -ENOMEDIUM;
949
950 mutex_lock(&pcr->pcr_mutex);
951
952 rtsx_pci_start_run(pcr);
953
954 /* Check SD mechanical write-protect switch */
955 val = rtsx_pci_readl(pcr, RTSX_BIPR);
956 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
957 if (val & SD_WRITE_PROTECT)
958 ro = 1;
959
960 mutex_unlock(&pcr->pcr_mutex);
961
962 return ro;
963}
964
965static int sdmmc_get_cd(struct mmc_host *mmc)
966{
967 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
968 struct rtsx_pcr *pcr = host->pcr;
969 int cd = 0;
970 u32 val;
971
972 if (host->eject)
973 return -ENOMEDIUM;
974
975 mutex_lock(&pcr->pcr_mutex);
976
977 rtsx_pci_start_run(pcr);
978
979 /* Check SD card detect */
980 val = rtsx_pci_card_exist(pcr);
981 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
982 if (val & SD_EXIST)
983 cd = 1;
984
985 mutex_unlock(&pcr->pcr_mutex);
986
987 return cd;
988}
989
990static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
991{
992 struct rtsx_pcr *pcr = host->pcr;
993 int err;
994 u8 stat;
995
996 /* Reference to Signal Voltage Switch Sequence in SD spec.
997 * Wait for a period of time so that the card can drive SD_CMD and
998 * SD_DAT[3:0] to low after sending back CMD11 response.
999 */
1000 mdelay(1);
1001
1002 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1003 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1004 * abort the voltage switch sequence;
1005 */
1006 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1007 if (err < 0)
1008 return err;
1009
1010 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1011 SD_DAT1_STATUS | SD_DAT0_STATUS))
1012 return -EINVAL;
1013
1014 /* Stop toggle SD clock */
1015 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1016 0xFF, SD_CLK_FORCE_STOP);
1017 if (err < 0)
1018 return err;
1019
1020 return 0;
1021}
1022
1023static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1024{
1025 struct rtsx_pcr *pcr = host->pcr;
1026 int err;
1027 u8 stat, mask, val;
1028
1029 /* Wait 1.8V output of voltage regulator in card stable */
1030 msleep(50);
1031
1032 /* Toggle SD clock again */
1033 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1034 if (err < 0)
1035 return err;
1036
1037 /* Wait for a period of time so that the card can drive
1038 * SD_DAT[3:0] to high at 1.8V
1039 */
1040 msleep(20);
1041
1042 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1043 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1044 if (err < 0)
1045 return err;
1046
1047 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1048 SD_DAT1_STATUS | SD_DAT0_STATUS;
1049 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1050 SD_DAT1_STATUS | SD_DAT0_STATUS;
1051 if ((stat & mask) != val) {
1052 dev_dbg(sdmmc_dev(host),
1053 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1054 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1055 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1056 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1057 return -EINVAL;
1058 }
1059
1060 return 0;
1061}
1062
1063static int sd_change_bank_voltage(struct realtek_pci_sdmmc *host, u8 voltage)
1064{
1065 struct rtsx_pcr *pcr = host->pcr;
1066 int err;
1067
1068 if (voltage == SD_IO_3V3) {
1069 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
1070 if (err < 0)
1071 return err;
1072 } else if (voltage == SD_IO_1V8) {
1073 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24);
1074 if (err < 0)
1075 return err;
1076 } else {
1077 return -EINVAL;
1078 }
1079
1080 return 0;
1081}
1082
1083static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1084{
1085 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1086 struct rtsx_pcr *pcr = host->pcr;
1087 int err = 0;
1088 u8 voltage;
1089
1090 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1091 __func__, ios->signal_voltage);
1092
1093 if (host->eject)
1094 return -ENOMEDIUM;
1095
1096 mutex_lock(&pcr->pcr_mutex);
1097
1098 rtsx_pci_start_run(pcr);
1099
1100 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1101 voltage = SD_IO_3V3;
1102 else
1103 voltage = SD_IO_1V8;
1104
1105 if (voltage == SD_IO_1V8) {
1106 err = rtsx_pci_write_register(pcr,
1107 SD30_DRIVE_SEL, 0x07, DRIVER_TYPE_B);
1108 if (err < 0)
1109 goto out;
1110
1111 err = sd_wait_voltage_stable_1(host);
1112 if (err < 0)
1113 goto out;
1114 }
1115
1116 err = sd_change_bank_voltage(host, voltage);
1117 if (err < 0)
1118 goto out;
1119
1120 if (voltage == SD_IO_1V8) {
1121 err = sd_wait_voltage_stable_2(host);
1122 if (err < 0)
1123 goto out;
1124 }
1125
1126 /* Stop toggle SD clock in idle */
1127 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1128 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1129
1130out:
1131 mutex_unlock(&pcr->pcr_mutex);
1132
1133 return err;
1134}
1135
1136static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1137{
1138 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1139 struct rtsx_pcr *pcr = host->pcr;
1140 int err = 0;
1141
1142 if (host->eject)
1143 return -ENOMEDIUM;
1144
1145 mutex_lock(&pcr->pcr_mutex);
1146
1147 rtsx_pci_start_run(pcr);
1148
1149 if (!host->ddr_mode)
1150 err = sd_tuning_rx(host, MMC_SEND_TUNING_BLOCK);
1151
1152 mutex_unlock(&pcr->pcr_mutex);
1153
1154 return err;
1155}
1156
1157static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1158 .request = sdmmc_request,
1159 .set_ios = sdmmc_set_ios,
1160 .get_ro = sdmmc_get_ro,
1161 .get_cd = sdmmc_get_cd,
1162 .start_signal_voltage_switch = sdmmc_switch_voltage,
1163 .execute_tuning = sdmmc_execute_tuning,
1164};
1165
1166#ifdef CONFIG_PM
1167static int rtsx_pci_sdmmc_suspend(struct platform_device *pdev,
1168 pm_message_t state)
1169{
1170 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1171 struct mmc_host *mmc = host->mmc;
1172 int err;
1173
1174 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1175
1176 err = mmc_suspend_host(mmc);
1177 if (err)
1178 return err;
1179
1180 return 0;
1181}
1182
1183static int rtsx_pci_sdmmc_resume(struct platform_device *pdev)
1184{
1185 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1186 struct mmc_host *mmc = host->mmc;
1187
1188 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1189
1190 return mmc_resume_host(mmc);
1191}
1192#else /* CONFIG_PM */
1193#define rtsx_pci_sdmmc_suspend NULL
1194#define rtsx_pci_sdmmc_resume NULL
1195#endif /* CONFIG_PM */
1196
1197static void init_extra_caps(struct realtek_pci_sdmmc *host)
1198{
1199 struct mmc_host *mmc = host->mmc;
1200 struct rtsx_pcr *pcr = host->pcr;
1201
1202 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1203
1204 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1205 mmc->caps |= MMC_CAP_UHS_SDR50;
1206 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1207 mmc->caps |= MMC_CAP_UHS_SDR104;
1208 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1209 mmc->caps |= MMC_CAP_UHS_DDR50;
1210 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1211 mmc->caps |= MMC_CAP_1_8V_DDR;
1212 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1213 mmc->caps |= MMC_CAP_8_BIT_DATA;
1214}
1215
1216static void realtek_init_host(struct realtek_pci_sdmmc *host)
1217{
1218 struct mmc_host *mmc = host->mmc;
1219
1220 mmc->f_min = 250000;
1221 mmc->f_max = 208000000;
1222 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1223 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1224 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1225 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1226 mmc->max_current_330 = 400;
1227 mmc->max_current_180 = 800;
1228 mmc->ops = &realtek_pci_sdmmc_ops;
1229
1230 init_extra_caps(host);
1231
1232 mmc->max_segs = 256;
1233 mmc->max_seg_size = 65536;
1234 mmc->max_blk_size = 512;
1235 mmc->max_blk_count = 65535;
1236 mmc->max_req_size = 524288;
1237}
1238
1239static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1240{
1241 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1242
1243 mmc_detect_change(host->mmc, 0);
1244}
1245
1246static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1247{
1248 struct mmc_host *mmc;
1249 struct realtek_pci_sdmmc *host;
1250 struct rtsx_pcr *pcr;
1251 struct pcr_handle *handle = pdev->dev.platform_data;
1252
1253 if (!handle)
1254 return -ENXIO;
1255
1256 pcr = handle->pcr;
1257 if (!pcr)
1258 return -ENXIO;
1259
1260 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1261
1262 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1263 if (!mmc)
1264 return -ENOMEM;
1265
1266 host = mmc_priv(mmc);
1267 host->pcr = pcr;
1268 host->mmc = mmc;
1269 host->pdev = pdev;
1270 platform_set_drvdata(pdev, host);
1271 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1272 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1273
1274 mutex_init(&host->host_mutex);
1275
1276 realtek_init_host(host);
1277
1278 mmc_add_host(mmc);
1279
1280 return 0;
1281}
1282
1283static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1284{
1285 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1286 struct rtsx_pcr *pcr;
1287 struct mmc_host *mmc;
1288
1289 if (!host)
1290 return 0;
1291
1292 pcr = host->pcr;
1293 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1294 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1295 mmc = host->mmc;
1296 host->eject = true;
1297
1298 mutex_lock(&host->host_mutex);
1299 if (host->mrq) {
1300 dev_dbg(&(pdev->dev),
1301 "%s: Controller removed during transfer\n",
1302 mmc_hostname(mmc));
1303
1304 rtsx_pci_complete_unfinished_transfer(pcr);
1305
1306 host->mrq->cmd->error = -ENOMEDIUM;
1307 if (host->mrq->stop)
1308 host->mrq->stop->error = -ENOMEDIUM;
1309 mmc_request_done(mmc, host->mrq);
1310 }
1311 mutex_unlock(&host->host_mutex);
1312
1313 mmc_remove_host(mmc);
1314 mmc_free_host(mmc);
1315
1316 platform_set_drvdata(pdev, NULL);
1317
1318 dev_dbg(&(pdev->dev),
1319 ": Realtek PCI-E SDMMC controller has been removed\n");
1320
1321 return 0;
1322}
1323
1324static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1325 {
1326 .name = DRV_NAME_RTSX_PCI_SDMMC,
1327 }, {
1328 /* sentinel */
1329 }
1330};
1331MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1332
1333static struct platform_driver rtsx_pci_sdmmc_driver = {
1334 .probe = rtsx_pci_sdmmc_drv_probe,
1335 .remove = rtsx_pci_sdmmc_drv_remove,
1336 .id_table = rtsx_pci_sdmmc_ids,
1337 .suspend = rtsx_pci_sdmmc_suspend,
1338 .resume = rtsx_pci_sdmmc_resume,
1339 .driver = {
1340 .owner = THIS_MODULE,
1341 .name = DRV_NAME_RTSX_PCI_SDMMC,
1342 },
1343};
1344module_platform_driver(rtsx_pci_sdmmc_driver);
1345
1346MODULE_LICENSE("GPL");
1347MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1348MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-14 18:54:29 -0500