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authorShawn Guo <shawn.guo@linaro.org>2013-01-21 06:02:26 -0500
committerChris Ball <cjb@laptop.org>2013-02-24 14:37:02 -0500
commit2a15f981aec7c6b800c0d285ee1a63acc8487b9b (patch)
tree5065e0a3104a0cc1587b0f8b755972096b9e9c8b /drivers/mmc
parent58c8c4fbdb5576a0afa377b1a730566b25c25cba (diff)
mmc: sdhci-esdhc-imx: Auto CMD23 support for usdhc
SDHCI core will try to use Auto CMD23 for mmc card. Currently, we will see the following message with mmc card on usdhc due to the lacking of Auto CMD23 support in the driver. $ mmc0: new high speed MMC card at address 0001 mmcblk1: mmc0:0001 MMC02G 1.87 GiB mmcblk1: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00 mmcblk1: retrying using single block read mmcblk1: Enable Auto CMD23 support for usdhc so that mmc card can work in multiple block mode. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci-esdhc-imx.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 968a70f1a420..24daaf4e20ba 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -36,6 +36,9 @@
36#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 36#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
37#define ESDHC_WTMK_LVL 0x44 37#define ESDHC_WTMK_LVL 0x44
38#define ESDHC_MIX_CTRL 0x48 38#define ESDHC_MIX_CTRL 0x48
39#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
40/* Bits 3 and 6 are not SDHCI standard definitions */
41#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
39 42
40/* 43/*
41 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 44 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
@@ -251,7 +254,12 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
251 254
252 if (is_imx6q_usdhc(imx_data)) { 255 if (is_imx6q_usdhc(imx_data)) {
253 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 256 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
254 m = val | (m & 0xffff0000); 257 /* Swap AC23 bit */
258 if (val & SDHCI_TRNS_AUTO_CMD23) {
259 val &= ~SDHCI_TRNS_AUTO_CMD23;
260 val |= ESDHC_MIX_CTRL_AC23EN;
261 }
262 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
255 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 263 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
256 } else { 264 } else {
257 /* 265 /*