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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-03 16:28:14 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-03 16:28:14 -0400
commitd6748066ad0e8b2514545998f8367ebb3906f299 (patch)
treef7a9bfd764a8fb781aeda0ef2249afbab42dddf7 /drivers/mmc
parentf04c045f8ce69c22bda9d99eb927276b776135fc (diff)
parent3ba1e543ab4b02640d396098f2f6a199560d5f2d (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits) MIPS: O32: Provide definition of registers ta0 .. ta3. MIPS: perf: Add Octeon support for hardware perf. MIPS: perf: Add support for 64-bit perf counters. MIPS: perf: Reorganize contents of perf support files. MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c MIPS: Add accessor macros for 64-bit performance counter registers. MIPS: Add probes for more Octeon II CPUs. MIPS: Add more CPU identifiers for Octeon II CPUs. MIPS: XLR, XLS: Add comment for smp setup MIPS: JZ4740: GPIO: Check correct IRQ in demux handler MIPS: JZ4740: GPIO: Simplify IRQ demuxer MIPS: JZ4740: Use generic irq chip MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines MIPS: Alchemy: kill au1xxx.h header MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep MIPS: Alchemy: Redo PCI as platform driver MIPS: Alchemy: more base address cleanup MIPS: Alchemy: rewrite USB platform setup. MIPS: Alchemy: abstract USB block control register access ... Fix up trivial conflicts in: arch/mips/alchemy/devboards/db1x00/platform.c drivers/ide/Kconfig drivers/mmc/host/au1xmmc.c drivers/video/Kconfig sound/mips/Kconfig
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/Kconfig2
-rw-r--r--drivers/mmc/host/au1xmmc.c92
2 files changed, 50 insertions, 44 deletions
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 87d5067ba629..cf444b0ca2cc 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -263,7 +263,7 @@ config MMC_WBSD
263 263
264config MMC_AU1X 264config MMC_AU1X
265 tristate "Alchemy AU1XX0 MMC Card Interface support" 265 tristate "Alchemy AU1XX0 MMC Card Interface support"
266 depends on SOC_AU1200 266 depends on MIPS_ALCHEMY
267 help 267 help
268 This selects the AMD Alchemy(R) Multimedia card interface. 268 This selects the AMD Alchemy(R) Multimedia card interface.
269 If you have a Alchemy platform with a MMC slot, say Y or M here. 269 If you have a Alchemy platform with a MMC slot, say Y or M here.
diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c
index 707bc7dddd22..5d3b9ae64523 100644
--- a/drivers/mmc/host/au1xmmc.c
+++ b/drivers/mmc/host/au1xmmc.c
@@ -64,11 +64,8 @@
64#define AU1XMMC_DESCRIPTOR_COUNT 1 64#define AU1XMMC_DESCRIPTOR_COUNT 1
65 65
66/* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */ 66/* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
67#ifdef CONFIG_SOC_AU1100 67#define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
68#define AU1XMMC_DESCRIPTOR_SIZE 0x0000ffff 68#define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
69#else /* Au1200 */
70#define AU1XMMC_DESCRIPTOR_SIZE 0x003fffff
71#endif
72 69
73#define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ 70#define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
74 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ 71 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
@@ -127,6 +124,7 @@ struct au1xmmc_host {
127#define HOST_F_XMIT 0x0001 124#define HOST_F_XMIT 0x0001
128#define HOST_F_RECV 0x0002 125#define HOST_F_RECV 0x0002
129#define HOST_F_DMA 0x0010 126#define HOST_F_DMA 0x0010
127#define HOST_F_DBDMA 0x0020
130#define HOST_F_ACTIVE 0x0100 128#define HOST_F_ACTIVE 0x0100
131#define HOST_F_STOP 0x1000 129#define HOST_F_STOP 0x1000
132 130
@@ -151,6 +149,16 @@ struct au1xmmc_host {
151#define DMA_CHANNEL(h) \ 149#define DMA_CHANNEL(h) \
152 (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) 150 (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
153 151
152static inline int has_dbdma(void)
153{
154 switch (alchemy_get_cputype()) {
155 case ALCHEMY_CPU_AU1200:
156 return 1;
157 default:
158 return 0;
159 }
160}
161
154static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) 162static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
155{ 163{
156 u32 val = au_readl(HOST_CONFIG(host)); 164 u32 val = au_readl(HOST_CONFIG(host));
@@ -353,14 +361,12 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
353 data->bytes_xfered = 0; 361 data->bytes_xfered = 0;
354 362
355 if (!data->error) { 363 if (!data->error) {
356 if (host->flags & HOST_F_DMA) { 364 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
357#ifdef CONFIG_SOC_AU1200 /* DBDMA */
358 u32 chan = DMA_CHANNEL(host); 365 u32 chan = DMA_CHANNEL(host);
359 366
360 chan_tab_t *c = *((chan_tab_t **)chan); 367 chan_tab_t *c = *((chan_tab_t **)chan);
361 au1x_dma_chan_t *cp = c->chan_ptr; 368 au1x_dma_chan_t *cp = c->chan_ptr;
362 data->bytes_xfered = cp->ddma_bytecnt; 369 data->bytes_xfered = cp->ddma_bytecnt;
363#endif
364 } else 370 } else
365 data->bytes_xfered = 371 data->bytes_xfered =
366 (data->blocks * data->blksz) - host->pio.len; 372 (data->blocks * data->blksz) - host->pio.len;
@@ -570,11 +576,10 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
570 576
571 host->status = HOST_S_DATA; 577 host->status = HOST_S_DATA;
572 578
573 if (host->flags & HOST_F_DMA) { 579 if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) {
574#ifdef CONFIG_SOC_AU1200 /* DBDMA */
575 u32 channel = DMA_CHANNEL(host); 580 u32 channel = DMA_CHANNEL(host);
576 581
577 /* Start the DMA as soon as the buffer gets something in it */ 582 /* Start the DBDMA as soon as the buffer gets something in it */
578 583
579 if (host->flags & HOST_F_RECV) { 584 if (host->flags & HOST_F_RECV) {
580 u32 mask = SD_STATUS_DB | SD_STATUS_NE; 585 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
@@ -584,7 +589,6 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
584 } 589 }
585 590
586 au1xxx_dbdma_start(channel); 591 au1xxx_dbdma_start(channel);
587#endif
588 } 592 }
589} 593}
590 594
@@ -633,8 +637,7 @@ static int au1xmmc_prepare_data(struct au1xmmc_host *host,
633 637
634 au_writel(data->blksz - 1, HOST_BLKSIZE(host)); 638 au_writel(data->blksz - 1, HOST_BLKSIZE(host));
635 639
636 if (host->flags & HOST_F_DMA) { 640 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
637#ifdef CONFIG_SOC_AU1200 /* DBDMA */
638 int i; 641 int i;
639 u32 channel = DMA_CHANNEL(host); 642 u32 channel = DMA_CHANNEL(host);
640 643
@@ -663,7 +666,6 @@ static int au1xmmc_prepare_data(struct au1xmmc_host *host,
663 666
664 datalen -= len; 667 datalen -= len;
665 } 668 }
666#endif
667 } else { 669 } else {
668 host->pio.index = 0; 670 host->pio.index = 0;
669 host->pio.offset = 0; 671 host->pio.offset = 0;
@@ -838,7 +840,6 @@ static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
838 return IRQ_HANDLED; 840 return IRQ_HANDLED;
839} 841}
840 842
841#ifdef CONFIG_SOC_AU1200
842/* 8bit memory DMA device */ 843/* 8bit memory DMA device */
843static dbdev_tab_t au1xmmc_mem_dbdev = { 844static dbdev_tab_t au1xmmc_mem_dbdev = {
844 .dev_id = DSCR_CMD0_ALWAYS, 845 .dev_id = DSCR_CMD0_ALWAYS,
@@ -905,7 +906,7 @@ static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
905 au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT); 906 au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
906 907
907 /* DBDMA is good to go */ 908 /* DBDMA is good to go */
908 host->flags |= HOST_F_DMA; 909 host->flags |= HOST_F_DMA | HOST_F_DBDMA;
909 910
910 return 0; 911 return 0;
911} 912}
@@ -918,7 +919,6 @@ static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
918 au1xxx_dbdma_chan_free(host->rx_chan); 919 au1xxx_dbdma_chan_free(host->rx_chan);
919 } 920 }
920} 921}
921#endif
922 922
923static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en) 923static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
924{ 924{
@@ -997,8 +997,16 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
997 mmc->f_min = 450000; 997 mmc->f_min = 450000;
998 mmc->f_max = 24000000; 998 mmc->f_max = 24000000;
999 999
1000 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; 1000 switch (alchemy_get_cputype()) {
1001 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; 1001 case ALCHEMY_CPU_AU1100:
1002 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
1003 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1004 break;
1005 case ALCHEMY_CPU_AU1200:
1006 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1007 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1008 break;
1009 }
1002 1010
1003 mmc->max_blk_size = 2048; 1011 mmc->max_blk_size = 2048;
1004 mmc->max_blk_count = 512; 1012 mmc->max_blk_count = 512;
@@ -1028,11 +1036,11 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
1028 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, 1036 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1029 (unsigned long)host); 1037 (unsigned long)host);
1030 1038
1031#ifdef CONFIG_SOC_AU1200 1039 if (has_dbdma()) {
1032 ret = au1xmmc_dbdma_init(host); 1040 ret = au1xmmc_dbdma_init(host);
1033 if (ret) 1041 if (ret)
1034 pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n"); 1042 pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n");
1035#endif 1043 }
1036 1044
1037#ifdef CONFIG_LEDS_CLASS 1045#ifdef CONFIG_LEDS_CLASS
1038 if (host->platdata && host->platdata->led) { 1046 if (host->platdata && host->platdata->led) {
@@ -1073,9 +1081,8 @@ out5:
1073 au_writel(0, HOST_CONFIG2(host)); 1081 au_writel(0, HOST_CONFIG2(host));
1074 au_sync(); 1082 au_sync();
1075 1083
1076#ifdef CONFIG_SOC_AU1200 1084 if (host->flags & HOST_F_DBDMA)
1077 au1xmmc_dbdma_shutdown(host); 1085 au1xmmc_dbdma_shutdown(host);
1078#endif
1079 1086
1080 tasklet_kill(&host->data_task); 1087 tasklet_kill(&host->data_task);
1081 tasklet_kill(&host->finish_task); 1088 tasklet_kill(&host->finish_task);
@@ -1120,9 +1127,9 @@ static int __devexit au1xmmc_remove(struct platform_device *pdev)
1120 tasklet_kill(&host->data_task); 1127 tasklet_kill(&host->data_task);
1121 tasklet_kill(&host->finish_task); 1128 tasklet_kill(&host->finish_task);
1122 1129
1123#ifdef CONFIG_SOC_AU1200 1130 if (host->flags & HOST_F_DBDMA)
1124 au1xmmc_dbdma_shutdown(host); 1131 au1xmmc_dbdma_shutdown(host);
1125#endif 1132
1126 au1xmmc_set_power(host, 0); 1133 au1xmmc_set_power(host, 0);
1127 1134
1128 free_irq(host->irq, host); 1135 free_irq(host->irq, host);
@@ -1181,24 +1188,23 @@ static struct platform_driver au1xmmc_driver = {
1181 1188
1182static int __init au1xmmc_init(void) 1189static int __init au1xmmc_init(void)
1183{ 1190{
1184#ifdef CONFIG_SOC_AU1200 1191 if (has_dbdma()) {
1185 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride 1192 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1186 * of 8 bits. And since devices are shared, we need to create 1193 * of 8 bits. And since devices are shared, we need to create
1187 * our own to avoid freaking out other devices. 1194 * our own to avoid freaking out other devices.
1188 */ 1195 */
1189 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); 1196 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1190 if (!memid) 1197 if (!memid)
1191 pr_err("au1xmmc: cannot add memory dbdma dev\n"); 1198 pr_err("au1xmmc: cannot add memory dbdma\n");
1192#endif 1199 }
1193 return platform_driver_register(&au1xmmc_driver); 1200 return platform_driver_register(&au1xmmc_driver);
1194} 1201}
1195 1202
1196static void __exit au1xmmc_exit(void) 1203static void __exit au1xmmc_exit(void)
1197{ 1204{
1198#ifdef CONFIG_SOC_AU1200 1205 if (has_dbdma() && memid)
1199 if (memid)
1200 au1xxx_ddma_del_device(memid); 1206 au1xxx_ddma_del_device(memid);
1201#endif 1207
1202 platform_driver_unregister(&au1xmmc_driver); 1208 platform_driver_unregister(&au1xmmc_driver);
1203} 1209}
1204 1210