diff options
| author | Pierre Ossman <drzeus@drzeus.cx> | 2007-02-11 13:57:36 -0500 |
|---|---|---|
| committer | Pierre Ossman <drzeus@drzeus.cx> | 2007-05-01 07:04:17 -0400 |
| commit | 1c6a0718f0bfdab0d9b7da5f7b74f38a0058c03a (patch) | |
| tree | 5e7f2a26d5d1782d87c596b40f874c6c0b8b8e1a /drivers/mmc/imxmmc.h | |
| parent | 98ac2162699f7e9880683cb954891817f20b607c (diff) | |
mmc: Move host and card drivers to subdirs
Clean up the drivers/mmc directory by moving card and host drivers
into subdirectories.
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
Diffstat (limited to 'drivers/mmc/imxmmc.h')
| -rw-r--r-- | drivers/mmc/imxmmc.h | 67 |
1 files changed, 0 insertions, 67 deletions
diff --git a/drivers/mmc/imxmmc.h b/drivers/mmc/imxmmc.h deleted file mode 100644 index e5339e334dbb..000000000000 --- a/drivers/mmc/imxmmc.h +++ /dev/null | |||
| @@ -1,67 +0,0 @@ | |||
| 1 | |||
| 2 | # define __REG16(x) (*((volatile u16 *)IO_ADDRESS(x))) | ||
| 3 | |||
| 4 | #define MMC_STR_STP_CLK __REG16(IMX_MMC_BASE + 0x00) | ||
| 5 | #define MMC_STATUS __REG16(IMX_MMC_BASE + 0x04) | ||
| 6 | #define MMC_CLK_RATE __REG16(IMX_MMC_BASE + 0x08) | ||
| 7 | #define MMC_CMD_DAT_CONT __REG16(IMX_MMC_BASE + 0x0C) | ||
| 8 | #define MMC_RES_TO __REG16(IMX_MMC_BASE + 0x10) | ||
| 9 | #define MMC_READ_TO __REG16(IMX_MMC_BASE + 0x14) | ||
| 10 | #define MMC_BLK_LEN __REG16(IMX_MMC_BASE + 0x18) | ||
| 11 | #define MMC_NOB __REG16(IMX_MMC_BASE + 0x1C) | ||
| 12 | #define MMC_REV_NO __REG16(IMX_MMC_BASE + 0x20) | ||
| 13 | #define MMC_INT_MASK __REG16(IMX_MMC_BASE + 0x24) | ||
| 14 | #define MMC_CMD __REG16(IMX_MMC_BASE + 0x28) | ||
| 15 | #define MMC_ARGH __REG16(IMX_MMC_BASE + 0x2C) | ||
| 16 | #define MMC_ARGL __REG16(IMX_MMC_BASE + 0x30) | ||
| 17 | #define MMC_RES_FIFO __REG16(IMX_MMC_BASE + 0x34) | ||
| 18 | #define MMC_BUFFER_ACCESS __REG16(IMX_MMC_BASE + 0x38) | ||
| 19 | #define MMC_BUFFER_ACCESS_OFS 0x38 | ||
| 20 | |||
| 21 | |||
| 22 | #define STR_STP_CLK_ENDIAN (1<<5) | ||
| 23 | #define STR_STP_CLK_RESET (1<<3) | ||
| 24 | #define STR_STP_CLK_ENABLE (1<<2) | ||
| 25 | #define STR_STP_CLK_START_CLK (1<<1) | ||
| 26 | #define STR_STP_CLK_STOP_CLK (1<<0) | ||
| 27 | #define STATUS_CARD_PRESENCE (1<<15) | ||
| 28 | #define STATUS_SDIO_INT_ACTIVE (1<<14) | ||
| 29 | #define STATUS_END_CMD_RESP (1<<13) | ||
| 30 | #define STATUS_WRITE_OP_DONE (1<<12) | ||
| 31 | #define STATUS_DATA_TRANS_DONE (1<<11) | ||
| 32 | #define STATUS_WR_CRC_ERROR_CODE_MASK (3<<10) | ||
| 33 | #define STATUS_CARD_BUS_CLK_RUN (1<<8) | ||
| 34 | #define STATUS_APPL_BUFF_FF (1<<7) | ||
| 35 | #define STATUS_APPL_BUFF_FE (1<<6) | ||
| 36 | #define STATUS_RESP_CRC_ERR (1<<5) | ||
| 37 | #define STATUS_CRC_READ_ERR (1<<3) | ||
| 38 | #define STATUS_CRC_WRITE_ERR (1<<2) | ||
| 39 | #define STATUS_TIME_OUT_RESP (1<<1) | ||
| 40 | #define STATUS_TIME_OUT_READ (1<<0) | ||
| 41 | #define STATUS_ERR_MASK 0x2f | ||
| 42 | #define CLK_RATE_PRESCALER(x) ((x) & 0x7) | ||
| 43 | #define CLK_RATE_CLK_RATE(x) (((x) & 0x7) << 3) | ||
| 44 | #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1<<12) | ||
| 45 | #define CMD_DAT_CONT_STOP_READWAIT (1<<11) | ||
| 46 | #define CMD_DAT_CONT_START_READWAIT (1<<10) | ||
| 47 | #define CMD_DAT_CONT_BUS_WIDTH_1 (0<<8) | ||
| 48 | #define CMD_DAT_CONT_BUS_WIDTH_4 (2<<8) | ||
| 49 | #define CMD_DAT_CONT_INIT (1<<7) | ||
| 50 | #define CMD_DAT_CONT_BUSY (1<<6) | ||
| 51 | #define CMD_DAT_CONT_STREAM_BLOCK (1<<5) | ||
| 52 | #define CMD_DAT_CONT_WRITE (1<<4) | ||
| 53 | #define CMD_DAT_CONT_DATA_ENABLE (1<<3) | ||
| 54 | #define CMD_DAT_CONT_RESPONSE_FORMAT_R1 (1) | ||
| 55 | #define CMD_DAT_CONT_RESPONSE_FORMAT_R2 (2) | ||
| 56 | #define CMD_DAT_CONT_RESPONSE_FORMAT_R3 (3) | ||
| 57 | #define CMD_DAT_CONT_RESPONSE_FORMAT_R4 (4) | ||
| 58 | #define CMD_DAT_CONT_RESPONSE_FORMAT_R5 (5) | ||
| 59 | #define CMD_DAT_CONT_RESPONSE_FORMAT_R6 (6) | ||
| 60 | #define INT_MASK_AUTO_CARD_DETECT (1<<6) | ||
| 61 | #define INT_MASK_DAT0_EN (1<<5) | ||
| 62 | #define INT_MASK_SDIO (1<<4) | ||
| 63 | #define INT_MASK_BUF_READY (1<<3) | ||
| 64 | #define INT_MASK_END_CMD_RES (1<<2) | ||
| 65 | #define INT_MASK_WRITE_OP_DONE (1<<1) | ||
| 66 | #define INT_MASK_DATA_TRAN (1<<0) | ||
| 67 | #define INT_ALL (0x7f) | ||