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authorArindam Nath <arindam.nath@amd.com>2011-05-05 02:48:59 -0400
committerChris Ball <cjb@laptop.org>2011-05-24 23:53:24 -0400
commitd6d50a15a2897d4133d536dd4343b5cf21163db3 (patch)
treeb56723c1b3e74ae2ae9e9d7fb39e916cdfa74958 /drivers/mmc/host
parent013909c4ffd16ded4895528b856fd8782df04dc6 (diff)
mmc: sd: add support for driver type selection
This patch adds support for setting driver strength during UHS-I initialization procedure. Since UHS-I cards set S18A (bit 24) in response to ACMD41, we use this as a base for UHS-I initialization. We modify the parameter list of mmc_sd_get_cid() so that we can save the ROCR from ACMD41 to check whether bit 24 is set. We decide whether the Host Controller supports A, C, or D driver type depending on the Capabilities register. Driver type B is suported by default. We then set the appropriate driver type for the card using CMD6 mode 1. As per Host Controller spec v3.00, we set driver type for the host only if Preset Value Enable in the Host Control2 register is not set. SDHCI_HOST_CONTROL has been renamed to SDHCI_HOST_CONTROL1 to conform to the spec. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc/host')
-rw-r--r--drivers/mmc/host/sdhci.c27
-rw-r--r--drivers/mmc/host/sdhci.h11
2 files changed, 37 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 4e2031449a23..8072e16d6d46 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1245,6 +1245,25 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1245 1245
1246 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1246 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1247 1247
1248 if (host->version >= SDHCI_SPEC_300) {
1249 u16 ctrl_2;
1250
1251 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1252 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1253 /*
1254 * We only need to set Driver Strength if the
1255 * preset value enable is not set.
1256 */
1257 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1258 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1259 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1260 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1261 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1262
1263 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1264 }
1265 }
1266
1248 /* 1267 /*
1249 * Some (ENE) controllers go apeshit on some ios operation, 1268 * Some (ENE) controllers go apeshit on some ios operation,
1250 * signalling timeout and CRC errors even on CMD0. Resetting 1269 * signalling timeout and CRC errors even on CMD0. Resetting
@@ -2086,6 +2105,14 @@ int sdhci_add_host(struct sdhci_host *host)
2086 if (caps[1] & SDHCI_SUPPORT_DDR50) 2105 if (caps[1] & SDHCI_SUPPORT_DDR50)
2087 mmc->caps |= MMC_CAP_UHS_DDR50; 2106 mmc->caps |= MMC_CAP_UHS_DDR50;
2088 2107
2108 /* Driver Type(s) (A, C, D) supported by the host */
2109 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2110 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2111 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2112 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2113 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2114 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2115
2089 ocr_avail = 0; 2116 ocr_avail = 0;
2090 /* 2117 /*
2091 * According to SD Host Controller spec v3.00, if the Host System 2118 * According to SD Host Controller spec v3.00, if the Host System
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 5cba2fea46e0..667bf8874be7 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -71,7 +71,7 @@
71#define SDHCI_DATA_LVL_MASK 0x00F00000 71#define SDHCI_DATA_LVL_MASK 0x00F00000
72#define SDHCI_DATA_LVL_SHIFT 20 72#define SDHCI_DATA_LVL_SHIFT 20
73 73
74#define SDHCI_HOST_CONTROL 0x28 74#define SDHCI_HOST_CONTROL 0x28
75#define SDHCI_CTRL_LED 0x01 75#define SDHCI_CTRL_LED 0x01
76#define SDHCI_CTRL_4BITBUS 0x02 76#define SDHCI_CTRL_4BITBUS 0x02
77#define SDHCI_CTRL_HISPD 0x04 77#define SDHCI_CTRL_HISPD 0x04
@@ -150,6 +150,12 @@
150 150
151#define SDHCI_HOST_CONTROL2 0x3E 151#define SDHCI_HOST_CONTROL2 0x3E
152#define SDHCI_CTRL_VDD_180 0x0008 152#define SDHCI_CTRL_VDD_180 0x0008
153#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
154#define SDHCI_CTRL_DRV_TYPE_B 0x0000
155#define SDHCI_CTRL_DRV_TYPE_A 0x0010
156#define SDHCI_CTRL_DRV_TYPE_C 0x0020
157#define SDHCI_CTRL_DRV_TYPE_D 0x0030
158#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
153 159
154#define SDHCI_CAPABILITIES 0x40 160#define SDHCI_CAPABILITIES 0x40
155#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 161#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
@@ -173,6 +179,9 @@
173#define SDHCI_SUPPORT_SDR50 0x00000001 179#define SDHCI_SUPPORT_SDR50 0x00000001
174#define SDHCI_SUPPORT_SDR104 0x00000002 180#define SDHCI_SUPPORT_SDR104 0x00000002
175#define SDHCI_SUPPORT_DDR50 0x00000004 181#define SDHCI_SUPPORT_DDR50 0x00000004
182#define SDHCI_DRIVER_TYPE_A 0x00000010
183#define SDHCI_DRIVER_TYPE_C 0x00000020
184#define SDHCI_DRIVER_TYPE_D 0x00000040
176 185
177#define SDHCI_CAPABILITIES_1 0x44 186#define SDHCI_CAPABILITIES_1 0x44
178 187