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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 12:03:55 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 12:03:55 -0400
commita7726350e06401929eac0aa0677a5467106565fc (patch)
treee189513e5014bdfccd73a3af731a6b57733743fa /drivers/mmc/host
parent4d26aa305414dbb33b3c32fb205b68004cda8ffc (diff)
parentafcf7924ecab726dab0227188783c4a40d9f0eec (diff)
Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanup from Olof Johansson: "Here is a collection of cleanup patches. Among the pieces that stand out are: - The deletion of h720x platforms - Split of at91 non-dt platforms to their own Kconfig file to keep them separate - General cleanups and refactoring of i.MX and MXS platforms - Some restructuring of clock tables for OMAP - Convertion of PMC driver for Tegra to dt-only - Some renames of sunxi -> sun4i (Allwinner A10) - ... plus a bunch of other stuff that I haven't mentioned" * tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits) ARM: i.MX: remove unused ARCH_* configs ARM i.MX53: remove platform ahci support ARM: sunxi: Rework the restart code irqchip: sunxi: Rename sunxi to sun4i irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro clocksource: sunxi: Rename sunxi to sun4i clocksource: sunxi: make use of CLKSRC_OF clocksource: sunxi: Cleanup the timer code ARM: at91: remove trailing semicolon from macros ARM: at91/setup: fix trivial typos ARM: EXYNOS: remove "config EXYNOS_DEV_DRM" ARM: EXYNOS: change the name of USB ohci header ARM: SAMSUNG: Remove unnecessary code for dma ARM: S3C24XX: Remove unused GPIO drive strength register definitions ARM: OMAP4+: PM: Restore CPU power state to ON with clockdomain force wakeup method ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2412 ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2410 ARM: S3C24XX: Removed unneeded dependency on ARCH_S3C24XX for boards ARM: SAMSUNG: Fix typo "CONFIG_SAMSUNG_DEV_RTC" ARM: S5P64X0: Fix typo "CONFIG_S5P64X0_SETUP_SDHCI" ...
Diffstat (limited to 'drivers/mmc/host')
-rw-r--r--drivers/mmc/host/msm_sdcc.c1
-rw-r--r--drivers/mmc/host/s3cmci.c83
2 files changed, 81 insertions, 3 deletions
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 7c0af0e80047..0ee4a57fe6b2 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -43,7 +43,6 @@
43#include <asm/sizes.h> 43#include <asm/sizes.h>
44 44
45#include <linux/platform_data/mmc-msm_sdcc.h> 45#include <linux/platform_data/mmc-msm_sdcc.h>
46#include <mach/msm_iomap.h>
47#include <mach/dma.h> 46#include <mach/dma.h>
48#include <mach/clk.h> 47#include <mach/clk.h>
49 48
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 63fb265e0da6..8d6794cdf899 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -25,14 +25,93 @@
25 25
26#include <mach/dma.h> 26#include <mach/dma.h>
27 27
28#include <mach/regs-sdi.h>
29
30#include <linux/platform_data/mmc-s3cmci.h> 28#include <linux/platform_data/mmc-s3cmci.h>
31 29
32#include "s3cmci.h" 30#include "s3cmci.h"
33 31
34#define DRIVER_NAME "s3c-mci" 32#define DRIVER_NAME "s3c-mci"
35 33
34#define S3C2410_SDICON (0x00)
35#define S3C2410_SDIPRE (0x04)
36#define S3C2410_SDICMDARG (0x08)
37#define S3C2410_SDICMDCON (0x0C)
38#define S3C2410_SDICMDSTAT (0x10)
39#define S3C2410_SDIRSP0 (0x14)
40#define S3C2410_SDIRSP1 (0x18)
41#define S3C2410_SDIRSP2 (0x1C)
42#define S3C2410_SDIRSP3 (0x20)
43#define S3C2410_SDITIMER (0x24)
44#define S3C2410_SDIBSIZE (0x28)
45#define S3C2410_SDIDCON (0x2C)
46#define S3C2410_SDIDCNT (0x30)
47#define S3C2410_SDIDSTA (0x34)
48#define S3C2410_SDIFSTA (0x38)
49
50#define S3C2410_SDIDATA (0x3C)
51#define S3C2410_SDIIMSK (0x40)
52
53#define S3C2440_SDIDATA (0x40)
54#define S3C2440_SDIIMSK (0x3C)
55
56#define S3C2440_SDICON_SDRESET (1 << 8)
57#define S3C2410_SDICON_SDIOIRQ (1 << 3)
58#define S3C2410_SDICON_FIFORESET (1 << 1)
59#define S3C2410_SDICON_CLOCKTYPE (1 << 0)
60
61#define S3C2410_SDICMDCON_LONGRSP (1 << 10)
62#define S3C2410_SDICMDCON_WAITRSP (1 << 9)
63#define S3C2410_SDICMDCON_CMDSTART (1 << 8)
64#define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
65#define S3C2410_SDICMDCON_INDEX (0x3f)
66
67#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
68#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
69#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
70#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
71
72#define S3C2440_SDIDCON_DS_WORD (2 << 22)
73#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
74#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
75#define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
76#define S3C2410_SDIDCON_WIDEBUS (1 << 16)
77#define S3C2410_SDIDCON_DMAEN (1 << 15)
78#define S3C2410_SDIDCON_STOP (1 << 14)
79#define S3C2440_SDIDCON_DATSTART (1 << 14)
80
81#define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
82#define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
83
84#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
85
86#define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9)
87#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
88#define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
89#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
90#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
91#define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
92#define S3C2410_SDIDSTA_TXDATAON (1 << 1)
93#define S3C2410_SDIDSTA_RXDATAON (1 << 0)
94
95#define S3C2440_SDIFSTA_FIFORESET (1 << 16)
96#define S3C2440_SDIFSTA_FIFOFAIL (3 << 14)
97#define S3C2410_SDIFSTA_TFDET (1 << 13)
98#define S3C2410_SDIFSTA_RFDET (1 << 12)
99#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
100
101#define S3C2410_SDIIMSK_RESPONSECRC (1 << 17)
102#define S3C2410_SDIIMSK_CMDSENT (1 << 16)
103#define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15)
104#define S3C2410_SDIIMSK_RESPONSEND (1 << 14)
105#define S3C2410_SDIIMSK_SDIOIRQ (1 << 12)
106#define S3C2410_SDIIMSK_FIFOFAIL (1 << 11)
107#define S3C2410_SDIIMSK_CRCSTATUS (1 << 10)
108#define S3C2410_SDIIMSK_DATACRC (1 << 9)
109#define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8)
110#define S3C2410_SDIIMSK_DATAFINISH (1 << 7)
111#define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4)
112#define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2)
113#define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0)
114
36enum dbg_channels { 115enum dbg_channels {
37 dbg_err = (1 << 0), 116 dbg_err = (1 << 0),
38 dbg_debug = (1 << 1), 117 dbg_debug = (1 << 1),