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author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-05-23 18:15:27 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-05-23 18:15:27 -0400 |
commit | 42cd71bf1e3a081b3150018bbf448cb6c8a844a5 (patch) | |
tree | 4a5d2eb0444255e4ad827a76dbd1417dd3876db6 /drivers/mmc/host | |
parent | f5039935ac685b3b9b8c13fbc33cac8643dee32e (diff) | |
parent | 9a55d9752d8abfc62f1ab05ccc790d22a0c8e7c0 (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (137 commits)
ARM: bcmring: convert to use sp804 clockevents
ARM: bcmring: convert to sp804 clocksource
ARM: 6912/1: bcmring: Add clkdev table in init_early
clockevents: ARM sp804: obtain sp804 timer rate via clks
clockevents: ARM sp804: allow clockevent name to be specified
clocksource: ARM sp804: obtain sp804 timer rate via clks
clocksource: ARM sp804: allow clocksource name to be specified
clocksource: convert OMAP1 to 32-bit down counting clocksource
clocksource: convert MXS timrotv2 to 32-bit down counting clocksource
clocksource: convert SPEAr platforms 16-bit up counting clocksource
clocksource: convert Integrator/AP 16-bit down counting clocksource
clocksource: convert W90x900 24-bit down counting clocksource
clocksource: convert ARM 32-bit down counting clocksources
clocksource: convert ARM 32-bit up counting clocksources
clocksource: add common mmio clocksource
ARM: update sa1100 to reflect PXA updates
ARM: omap1: convert to using readl/writel instead of volatile struct
ARM: omap1: delete useless interrupt handler
ARM: s5p: consolidate selection of timer register
ARM: 6939/1: fix missing 'cpu_relax()' declaration
...
Diffstat (limited to 'drivers/mmc/host')
-rw-r--r-- | drivers/mmc/host/mmci.c | 6 | ||||
-rw-r--r-- | drivers/mmc/host/mmci.h | 41 |
2 files changed, 31 insertions, 16 deletions
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index b4a7e4fba90f..4941e06fe2e1 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c | |||
@@ -77,7 +77,7 @@ static struct variant_data variant_arm_extended_fifo = { | |||
77 | static struct variant_data variant_u300 = { | 77 | static struct variant_data variant_u300 = { |
78 | .fifosize = 16 * 4, | 78 | .fifosize = 16 * 4, |
79 | .fifohalfsize = 8 * 4, | 79 | .fifohalfsize = 8 * 4, |
80 | .clkreg_enable = 1 << 13, /* HWFCEN */ | 80 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
81 | .datalength_bits = 16, | 81 | .datalength_bits = 16, |
82 | .sdio = true, | 82 | .sdio = true, |
83 | }; | 83 | }; |
@@ -86,7 +86,7 @@ static struct variant_data variant_ux500 = { | |||
86 | .fifosize = 30 * 4, | 86 | .fifosize = 30 * 4, |
87 | .fifohalfsize = 8 * 4, | 87 | .fifohalfsize = 8 * 4, |
88 | .clkreg = MCI_CLK_ENABLE, | 88 | .clkreg = MCI_CLK_ENABLE, |
89 | .clkreg_enable = 1 << 14, /* HWFCEN */ | 89 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
90 | .datalength_bits = 24, | 90 | .datalength_bits = 24, |
91 | .sdio = true, | 91 | .sdio = true, |
92 | .st_clkdiv = true, | 92 | .st_clkdiv = true, |
@@ -103,6 +103,8 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |||
103 | if (desired) { | 103 | if (desired) { |
104 | if (desired >= host->mclk) { | 104 | if (desired >= host->mclk) { |
105 | clk = MCI_CLK_BYPASS; | 105 | clk = MCI_CLK_BYPASS; |
106 | if (variant->st_clkdiv) | ||
107 | clk |= MCI_ST_UX500_NEG_EDGE; | ||
106 | host->cclk = host->mclk; | 108 | host->cclk = host->mclk; |
107 | } else if (variant->st_clkdiv) { | 109 | } else if (variant->st_clkdiv) { |
108 | /* | 110 | /* |
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index ec9a7bc6d0df..bb32e21c09db 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h | |||
@@ -11,23 +11,33 @@ | |||
11 | #define MCI_PWR_OFF 0x00 | 11 | #define MCI_PWR_OFF 0x00 |
12 | #define MCI_PWR_UP 0x02 | 12 | #define MCI_PWR_UP 0x02 |
13 | #define MCI_PWR_ON 0x03 | 13 | #define MCI_PWR_ON 0x03 |
14 | #define MCI_DATA2DIREN (1 << 2) | ||
15 | #define MCI_CMDDIREN (1 << 3) | ||
16 | #define MCI_DATA0DIREN (1 << 4) | ||
17 | #define MCI_DATA31DIREN (1 << 5) | ||
18 | #define MCI_OD (1 << 6) | 14 | #define MCI_OD (1 << 6) |
19 | #define MCI_ROD (1 << 7) | 15 | #define MCI_ROD (1 << 7) |
20 | /* The ST Micro version does not have ROD */ | 16 | /* |
21 | #define MCI_FBCLKEN (1 << 7) | 17 | * The ST Micro version does not have ROD and reuse the voltage registers |
22 | #define MCI_DATA74DIREN (1 << 8) | 18 | * for direction settings |
19 | */ | ||
20 | #define MCI_ST_DATA2DIREN (1 << 2) | ||
21 | #define MCI_ST_CMDDIREN (1 << 3) | ||
22 | #define MCI_ST_DATA0DIREN (1 << 4) | ||
23 | #define MCI_ST_DATA31DIREN (1 << 5) | ||
24 | #define MCI_ST_FBCLKEN (1 << 7) | ||
25 | #define MCI_ST_DATA74DIREN (1 << 8) | ||
23 | 26 | ||
24 | #define MMCICLOCK 0x004 | 27 | #define MMCICLOCK 0x004 |
25 | #define MCI_CLK_ENABLE (1 << 8) | 28 | #define MCI_CLK_ENABLE (1 << 8) |
26 | #define MCI_CLK_PWRSAVE (1 << 9) | 29 | #define MCI_CLK_PWRSAVE (1 << 9) |
27 | #define MCI_CLK_BYPASS (1 << 10) | 30 | #define MCI_CLK_BYPASS (1 << 10) |
28 | #define MCI_4BIT_BUS (1 << 11) | 31 | #define MCI_4BIT_BUS (1 << 11) |
29 | /* 8bit wide buses supported in ST Micro versions */ | 32 | /* |
33 | * 8bit wide buses, hardware flow contronl, negative edges and clock inversion | ||
34 | * supported in ST Micro U300 and Ux500 versions | ||
35 | */ | ||
30 | #define MCI_ST_8BIT_BUS (1 << 12) | 36 | #define MCI_ST_8BIT_BUS (1 << 12) |
37 | #define MCI_ST_U300_HWFCEN (1 << 13) | ||
38 | #define MCI_ST_UX500_NEG_EDGE (1 << 13) | ||
39 | #define MCI_ST_UX500_HWFCEN (1 << 14) | ||
40 | #define MCI_ST_UX500_CLK_INV (1 << 15) | ||
31 | 41 | ||
32 | #define MMCIARGUMENT 0x008 | 42 | #define MMCIARGUMENT 0x008 |
33 | #define MMCICOMMAND 0x00c | 43 | #define MMCICOMMAND 0x00c |
@@ -88,8 +98,9 @@ | |||
88 | #define MCI_RXFIFOEMPTY (1 << 19) | 98 | #define MCI_RXFIFOEMPTY (1 << 19) |
89 | #define MCI_TXDATAAVLBL (1 << 20) | 99 | #define MCI_TXDATAAVLBL (1 << 20) |
90 | #define MCI_RXDATAAVLBL (1 << 21) | 100 | #define MCI_RXDATAAVLBL (1 << 21) |
91 | #define MCI_SDIOIT (1 << 22) | 101 | /* Extended status bits for the ST Micro variants */ |
92 | #define MCI_CEATAEND (1 << 23) | 102 | #define MCI_ST_SDIOIT (1 << 22) |
103 | #define MCI_ST_CEATAEND (1 << 23) | ||
93 | 104 | ||
94 | #define MMCICLEAR 0x038 | 105 | #define MMCICLEAR 0x038 |
95 | #define MCI_CMDCRCFAILCLR (1 << 0) | 106 | #define MCI_CMDCRCFAILCLR (1 << 0) |
@@ -102,8 +113,9 @@ | |||
102 | #define MCI_CMDSENTCLR (1 << 7) | 113 | #define MCI_CMDSENTCLR (1 << 7) |
103 | #define MCI_DATAENDCLR (1 << 8) | 114 | #define MCI_DATAENDCLR (1 << 8) |
104 | #define MCI_DATABLOCKENDCLR (1 << 10) | 115 | #define MCI_DATABLOCKENDCLR (1 << 10) |
105 | #define MCI_SDIOITC (1 << 22) | 116 | /* Extended status bits for the ST Micro variants */ |
106 | #define MCI_CEATAENDC (1 << 23) | 117 | #define MCI_ST_SDIOITC (1 << 22) |
118 | #define MCI_ST_CEATAENDC (1 << 23) | ||
107 | 119 | ||
108 | #define MMCIMASK0 0x03c | 120 | #define MMCIMASK0 0x03c |
109 | #define MCI_CMDCRCFAILMASK (1 << 0) | 121 | #define MCI_CMDCRCFAILMASK (1 << 0) |
@@ -127,8 +139,9 @@ | |||
127 | #define MCI_RXFIFOEMPTYMASK (1 << 19) | 139 | #define MCI_RXFIFOEMPTYMASK (1 << 19) |
128 | #define MCI_TXDATAAVLBLMASK (1 << 20) | 140 | #define MCI_TXDATAAVLBLMASK (1 << 20) |
129 | #define MCI_RXDATAAVLBLMASK (1 << 21) | 141 | #define MCI_RXDATAAVLBLMASK (1 << 21) |
130 | #define MCI_SDIOITMASK (1 << 22) | 142 | /* Extended status bits for the ST Micro variants */ |
131 | #define MCI_CEATAENDMASK (1 << 23) | 143 | #define MCI_ST_SDIOITMASK (1 << 22) |
144 | #define MCI_ST_CEATAENDMASK (1 << 23) | ||
132 | 145 | ||
133 | #define MMCIMASK1 0x040 | 146 | #define MMCIMASK1 0x040 |
134 | #define MMCIFIFOCNT 0x048 | 147 | #define MMCIFIFOCNT 0x048 |