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authorPierre Ossman <drzeus@drzeus.cx>2008-03-18 12:35:49 -0400
committerPierre Ossman <drzeus@drzeus.cx>2008-07-15 08:14:39 -0400
commitb8c86fc5d8deaa5a6dc49c2c1ed144e6838bf0f3 (patch)
treea6405b8f5843760fa6f93c763f5850738d3142cd /drivers/mmc/host/sdhci.h
parentc9b74c5b8fb807187f6b1db09012828fcd2d7e73 (diff)
sdhci: move pci stuff to separate module
The SDHCI interface is not PCI specific, yet the Linux driver was intimitely connected to the PCI bus. This patch properly separates the PCI specific portion from the bus independent code. This patch is based on work by Ben Dooks but he did not have time to complete it. Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
Diffstat (limited to 'drivers/mmc/host/sdhci.h')
-rw-r--r--drivers/mmc/host/sdhci.h82
1 files changed, 57 insertions, 25 deletions
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 299118de8933..22fc258b12aa 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -10,18 +10,6 @@
10 */ 10 */
11 11
12/* 12/*
13 * PCI registers
14 */
15
16#define PCI_SDHCI_IFPIO 0x00
17#define PCI_SDHCI_IFDMA 0x01
18#define PCI_SDHCI_IFVENDOR 0x02
19
20#define PCI_SLOT_INFO 0x40 /* 8 bits */
21#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
22#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
23
24/*
25 * Controller registers 13 * Controller registers
26 */ 14 */
27 15
@@ -162,10 +150,43 @@
162#define SDHCI_SPEC_VER_MASK 0x00FF 150#define SDHCI_SPEC_VER_MASK 0x00FF
163#define SDHCI_SPEC_VER_SHIFT 0 151#define SDHCI_SPEC_VER_SHIFT 0
164 152
165struct sdhci_chip; 153struct sdhci_ops;
166 154
167struct sdhci_host { 155struct sdhci_host {
168 struct sdhci_chip *chip; 156 /* Data set by hardware interface driver */
157 const char *hw_name; /* Hardware bus name */
158
159 unsigned int quirks; /* Deviations from spec. */
160
161/* Controller doesn't honor resets unless we touch the clock register */
162#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
163/* Controller has bad caps bits, but really supports DMA */
164#define SDHCI_QUIRK_FORCE_DMA (1<<1)
165/* Controller doesn't like to be reset when there is no card inserted. */
166#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
167/* Controller doesn't like clearing the power reg before a change */
168#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
169/* Controller has flaky internal state so reset it on each ios change */
170#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
171/* Controller has an unusable DMA engine */
172#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
173/* Controller can only DMA from 32-bit aligned addresses */
174#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6)
175/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
176#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7)
177/* Controller needs to be reset after each request to stay stable */
178#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8)
179/* Controller needs voltage and power writes to happen separately */
180#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<9)
181/* Controller has an off-by-one issue with timeout value */
182#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<10)
183
184 int irq; /* Device IRQ */
185 void __iomem * ioaddr; /* Mapped address */
186
187 const struct sdhci_ops *ops; /* Low level hw interface */
188
189 /* Internal data */
169 struct mmc_host *mmc; /* MMC structure */ 190 struct mmc_host *mmc; /* MMC structure */
170 191
171#ifdef CONFIG_LEDS_CLASS 192#ifdef CONFIG_LEDS_CLASS
@@ -194,22 +215,33 @@ struct sdhci_host {
194 int offset; /* Offset into current sg */ 215 int offset; /* Offset into current sg */
195 int remain; /* Bytes left in current */ 216 int remain; /* Bytes left in current */
196 217
197 int irq; /* Device IRQ */
198 int bar; /* PCI BAR index */
199 unsigned long addr; /* Bus address */
200 void __iomem * ioaddr; /* Mapped address */
201
202 struct tasklet_struct card_tasklet; /* Tasklet structures */ 218 struct tasklet_struct card_tasklet; /* Tasklet structures */
203 struct tasklet_struct finish_tasklet; 219 struct tasklet_struct finish_tasklet;
204 220
205 struct timer_list timer; /* Timer for timeouts */ 221 struct timer_list timer; /* Timer for timeouts */
206};
207 222
208struct sdhci_chip { 223 unsigned long private[0] ____cacheline_aligned;
209 struct pci_dev *pdev; 224};
210 225
211 unsigned long quirks;
212 226
213 int num_slots; /* Slots on controller */ 227struct sdhci_ops {
214 struct sdhci_host *hosts[0]; /* Pointers to hosts */ 228 int (*enable_dma)(struct sdhci_host *host);
215}; 229};
230
231
232extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
233 size_t priv_size);
234extern void sdhci_free_host(struct sdhci_host *host);
235
236static inline void *sdhci_priv(struct sdhci_host *host)
237{
238 return (void *)host->private;
239}
240
241extern int sdhci_add_host(struct sdhci_host *host);
242extern void sdhci_remove_host(struct sdhci_host *host);
243
244#ifdef CONFIG_PM
245extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
246extern int sdhci_resume_host(struct sdhci_host *host);
247#endif