diff options
author | Marc Kleine-Budde <mkl@pengutronix.de> | 2008-10-10 06:05:03 -0400 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2008-12-16 08:58:15 -0500 |
commit | 4b7c0e4cae35b49380ad69e668324d4d70b7fd4c (patch) | |
tree | 6d546d2b738a2e2d28bf6ef70bf833a2ef8137e4 /drivers/mmc/host/imxmmc.c | |
parent | 3287abbd71fded81469adce21628e838c566b86b (diff) |
imxmmc: Checkpatch cleanup
This cleans up the warnings issued by the checkpatch script
and remove the file history from the header
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/mmc/host/imxmmc.c')
-rw-r--r-- | drivers/mmc/host/imxmmc.c | 301 |
1 files changed, 141 insertions, 160 deletions
diff --git a/drivers/mmc/host/imxmmc.c b/drivers/mmc/host/imxmmc.c index 2f0fcdb869b7..02e9dd3e22db 100644 --- a/drivers/mmc/host/imxmmc.c +++ b/drivers/mmc/host/imxmmc.c | |||
@@ -10,20 +10,6 @@ | |||
10 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
12 | * | 12 | * |
13 | * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
14 | * Changed to conform redesigned i.MX scatter gather DMA interface | ||
15 | * | ||
16 | * 2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
17 | * Updated for 2.6.14 kernel | ||
18 | * | ||
19 | * 2005-12-13 Jay Monkman <jtm@smoothsmoothie.com> | ||
20 | * Found and corrected problems in the write path | ||
21 | * | ||
22 | * 2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
23 | * The event handling rewritten right way in softirq. | ||
24 | * Added many ugly hacks and delays to overcome SDHC | ||
25 | * deficiencies | ||
26 | * | ||
27 | */ | 13 | */ |
28 | 14 | ||
29 | #include <linux/module.h> | 15 | #include <linux/module.h> |
@@ -37,9 +23,9 @@ | |||
37 | #include <linux/mmc/card.h> | 23 | #include <linux/mmc/card.h> |
38 | #include <linux/delay.h> | 24 | #include <linux/delay.h> |
39 | #include <linux/clk.h> | 25 | #include <linux/clk.h> |
26 | #include <linux/io.h> | ||
40 | 27 | ||
41 | #include <asm/dma.h> | 28 | #include <asm/dma.h> |
42 | #include <asm/io.h> | ||
43 | #include <asm/irq.h> | 29 | #include <asm/irq.h> |
44 | #include <asm/sizes.h> | 30 | #include <asm/sizes.h> |
45 | #include <mach/mmc.h> | 31 | #include <mach/mmc.h> |
@@ -50,8 +36,8 @@ | |||
50 | #define DRIVER_NAME "imx-mmc" | 36 | #define DRIVER_NAME "imx-mmc" |
51 | 37 | ||
52 | #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \ | 38 | #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \ |
53 | INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \ | 39 | INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \ |
54 | INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO) | 40 | INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO) |
55 | 41 | ||
56 | struct imxmci_host { | 42 | struct imxmci_host { |
57 | struct mmc_host *mmc; | 43 | struct mmc_host *mmc; |
@@ -74,7 +60,7 @@ struct imxmci_host { | |||
74 | struct tasklet_struct tasklet; | 60 | struct tasklet_struct tasklet; |
75 | unsigned int status_reg; | 61 | unsigned int status_reg; |
76 | unsigned long pending_events; | 62 | unsigned long pending_events; |
77 | /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */ | 63 | /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */ |
78 | u16 *data_ptr; | 64 | u16 *data_ptr; |
79 | unsigned int data_cnt; | 65 | unsigned int data_cnt; |
80 | atomic_t stuck_timeout; | 66 | atomic_t stuck_timeout; |
@@ -115,13 +101,13 @@ static void imxmci_stop_clock(struct imxmci_host *host) | |||
115 | { | 101 | { |
116 | int i = 0; | 102 | int i = 0; |
117 | MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK; | 103 | MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK; |
118 | while(i < 0x1000) { | 104 | while (i < 0x1000) { |
119 | if(!(i & 0x7f)) | 105 | if (!(i & 0x7f)) |
120 | MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK; | 106 | MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK; |
121 | 107 | ||
122 | if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) { | 108 | if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) { |
123 | /* Check twice before cut */ | 109 | /* Check twice before cut */ |
124 | if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) | 110 | if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) |
125 | return; | 111 | return; |
126 | } | 112 | } |
127 | 113 | ||
@@ -150,13 +136,13 @@ static int imxmci_start_clock(struct imxmci_host *host) | |||
150 | do { | 136 | do { |
151 | unsigned int delay = delay_limit; | 137 | unsigned int delay = delay_limit; |
152 | 138 | ||
153 | while(delay--){ | 139 | while (delay--) { |
154 | if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) | 140 | if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) |
155 | /* Check twice before cut */ | 141 | /* Check twice before cut */ |
156 | if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) | 142 | if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) |
157 | return 0; | 143 | return 0; |
158 | 144 | ||
159 | if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) | 145 | if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) |
160 | return 0; | 146 | return 0; |
161 | } | 147 | } |
162 | 148 | ||
@@ -167,11 +153,11 @@ static int imxmci_start_clock(struct imxmci_host *host) | |||
167 | * IRQ or schedule delays this function execution and the clocks has | 153 | * IRQ or schedule delays this function execution and the clocks has |
168 | * been already stopped by other means (response processing, SDHC HW) | 154 | * been already stopped by other means (response processing, SDHC HW) |
169 | */ | 155 | */ |
170 | if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) | 156 | if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) |
171 | MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK; | 157 | MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK; |
172 | local_irq_restore(flags); | 158 | local_irq_restore(flags); |
173 | 159 | ||
174 | } while(++trials<256); | 160 | } while (++trials < 256); |
175 | 161 | ||
176 | dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n"); | 162 | dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n"); |
177 | 163 | ||
@@ -198,13 +184,14 @@ static void imxmci_softreset(void) | |||
198 | } | 184 | } |
199 | 185 | ||
200 | static int imxmci_busy_wait_for_status(struct imxmci_host *host, | 186 | static int imxmci_busy_wait_for_status(struct imxmci_host *host, |
201 | unsigned int *pstat, unsigned int stat_mask, | 187 | unsigned int *pstat, unsigned int stat_mask, |
202 | int timeout, const char *where) | 188 | int timeout, const char *where) |
203 | { | 189 | { |
204 | int loops=0; | 190 | int loops = 0; |
205 | while(!(*pstat & stat_mask)) { | 191 | |
206 | loops+=2; | 192 | while (!(*pstat & stat_mask)) { |
207 | if(loops >= timeout) { | 193 | loops += 2; |
194 | if (loops >= timeout) { | ||
208 | dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n", | 195 | dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n", |
209 | where, *pstat, stat_mask); | 196 | where, *pstat, stat_mask); |
210 | return -1; | 197 | return -1; |
@@ -212,13 +199,13 @@ static int imxmci_busy_wait_for_status(struct imxmci_host *host, | |||
212 | udelay(2); | 199 | udelay(2); |
213 | *pstat |= MMC_STATUS; | 200 | *pstat |= MMC_STATUS; |
214 | } | 201 | } |
215 | if(!loops) | 202 | if (!loops) |
216 | return 0; | 203 | return 0; |
217 | 204 | ||
218 | /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */ | 205 | /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */ |
219 | if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000)) | 206 | if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000)) |
220 | dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n", | 207 | dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n", |
221 | loops, where, *pstat, stat_mask); | 208 | loops, where, *pstat, stat_mask); |
222 | return loops; | 209 | return loops; |
223 | } | 210 | } |
224 | 211 | ||
@@ -259,7 +246,7 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) | |||
259 | } | 246 | } |
260 | 247 | ||
261 | /* Convert back to virtual address */ | 248 | /* Convert back to virtual address */ |
262 | host->data_ptr = (u16*)sg_virt(data->sg); | 249 | host->data_ptr = (u16 *)sg_virt(data->sg); |
263 | host->data_cnt = 0; | 250 | host->data_cnt = 0; |
264 | 251 | ||
265 | clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events); | 252 | clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events); |
@@ -271,10 +258,10 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) | |||
271 | if (data->flags & MMC_DATA_READ) { | 258 | if (data->flags & MMC_DATA_READ) { |
272 | host->dma_dir = DMA_FROM_DEVICE; | 259 | host->dma_dir = DMA_FROM_DEVICE; |
273 | host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, | 260 | host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, |
274 | data->sg_len, host->dma_dir); | 261 | data->sg_len, host->dma_dir); |
275 | 262 | ||
276 | imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, | 263 | imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, |
277 | host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ); | 264 | host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ); |
278 | 265 | ||
279 | /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/ | 266 | /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/ |
280 | CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN; | 267 | CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN; |
@@ -282,10 +269,10 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) | |||
282 | host->dma_dir = DMA_TO_DEVICE; | 269 | host->dma_dir = DMA_TO_DEVICE; |
283 | 270 | ||
284 | host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, | 271 | host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, |
285 | data->sg_len, host->dma_dir); | 272 | data->sg_len, host->dma_dir); |
286 | 273 | ||
287 | imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, | 274 | imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, |
288 | host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE); | 275 | host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE); |
289 | 276 | ||
290 | /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/ | 277 | /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/ |
291 | CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN; | 278 | CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN; |
@@ -293,12 +280,12 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) | |||
293 | 280 | ||
294 | #if 1 /* This code is there only for consistency checking and can be disabled in future */ | 281 | #if 1 /* This code is there only for consistency checking and can be disabled in future */ |
295 | host->dma_size = 0; | 282 | host->dma_size = 0; |
296 | for(i=0; i<host->dma_nents; i++) | 283 | for (i = 0; i < host->dma_nents; i++) |
297 | host->dma_size+=data->sg[i].length; | 284 | host->dma_size += data->sg[i].length; |
298 | 285 | ||
299 | if (datasz > host->dma_size) { | 286 | if (datasz > host->dma_size) { |
300 | dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n", | 287 | dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n", |
301 | datasz, host->dma_size); | 288 | datasz, host->dma_size); |
302 | } | 289 | } |
303 | #endif | 290 | #endif |
304 | 291 | ||
@@ -306,7 +293,7 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) | |||
306 | 293 | ||
307 | wmb(); | 294 | wmb(); |
308 | 295 | ||
309 | if(host->actual_bus_width == MMC_BUS_WIDTH_4) | 296 | if (host->actual_bus_width == MMC_BUS_WIDTH_4) |
310 | BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */ | 297 | BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */ |
311 | else | 298 | else |
312 | BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */ | 299 | BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */ |
@@ -317,9 +304,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) | |||
317 | clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events); | 304 | clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events); |
318 | 305 | ||
319 | /* start DMA engine for read, write is delayed after initial response */ | 306 | /* start DMA engine for read, write is delayed after initial response */ |
320 | if (host->dma_dir == DMA_FROM_DEVICE) { | 307 | if (host->dma_dir == DMA_FROM_DEVICE) |
321 | imx_dma_enable(host->dma); | 308 | imx_dma_enable(host->dma); |
322 | } | ||
323 | } | 309 | } |
324 | 310 | ||
325 | static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat) | 311 | static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat) |
@@ -351,10 +337,10 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, | |||
351 | break; | 337 | break; |
352 | } | 338 | } |
353 | 339 | ||
354 | if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) ) | 340 | if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events)) |
355 | cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */ | 341 | cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */ |
356 | 342 | ||
357 | if ( host->actual_bus_width == MMC_BUS_WIDTH_4 ) | 343 | if (host->actual_bus_width == MMC_BUS_WIDTH_4) |
358 | cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; | 344 | cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; |
359 | 345 | ||
360 | MMC_CMD = cmd->opcode; | 346 | MMC_CMD = cmd->opcode; |
@@ -368,12 +354,12 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, | |||
368 | 354 | ||
369 | imask = IMXMCI_INT_MASK_DEFAULT; | 355 | imask = IMXMCI_INT_MASK_DEFAULT; |
370 | imask &= ~INT_MASK_END_CMD_RES; | 356 | imask &= ~INT_MASK_END_CMD_RES; |
371 | if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) { | 357 | if (cmdat & CMD_DAT_CONT_DATA_ENABLE) { |
372 | /*imask &= ~INT_MASK_BUF_READY;*/ | 358 | /* imask &= ~INT_MASK_BUF_READY; */ |
373 | imask &= ~INT_MASK_DATA_TRAN; | 359 | imask &= ~INT_MASK_DATA_TRAN; |
374 | if ( cmdat & CMD_DAT_CONT_WRITE ) | 360 | if (cmdat & CMD_DAT_CONT_WRITE) |
375 | imask &= ~INT_MASK_WRITE_OP_DONE; | 361 | imask &= ~INT_MASK_WRITE_OP_DONE; |
376 | if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) | 362 | if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) |
377 | imask &= ~INT_MASK_BUF_READY; | 363 | imask &= ~INT_MASK_BUF_READY; |
378 | } | 364 | } |
379 | 365 | ||
@@ -395,14 +381,14 @@ static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request * | |||
395 | spin_lock_irqsave(&host->lock, flags); | 381 | spin_lock_irqsave(&host->lock, flags); |
396 | 382 | ||
397 | host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m | | 383 | host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m | |
398 | IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m); | 384 | IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m); |
399 | 385 | ||
400 | host->imask = IMXMCI_INT_MASK_DEFAULT; | 386 | host->imask = IMXMCI_INT_MASK_DEFAULT; |
401 | MMC_INT_MASK = host->imask; | 387 | MMC_INT_MASK = host->imask; |
402 | 388 | ||
403 | spin_unlock_irqrestore(&host->lock, flags); | 389 | spin_unlock_irqrestore(&host->lock, flags); |
404 | 390 | ||
405 | if(req && req->cmd) | 391 | if (req && req->cmd) |
406 | host->prev_cmd_code = req->cmd->opcode; | 392 | host->prev_cmd_code = req->cmd->opcode; |
407 | 393 | ||
408 | host->req = NULL; | 394 | host->req = NULL; |
@@ -416,17 +402,17 @@ static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat) | |||
416 | struct mmc_data *data = host->data; | 402 | struct mmc_data *data = host->data; |
417 | int data_error; | 403 | int data_error; |
418 | 404 | ||
419 | if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){ | 405 | if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { |
420 | imx_dma_disable(host->dma); | 406 | imx_dma_disable(host->dma); |
421 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents, | 407 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents, |
422 | host->dma_dir); | 408 | host->dma_dir); |
423 | } | 409 | } |
424 | 410 | ||
425 | if ( stat & STATUS_ERR_MASK ) { | 411 | if (stat & STATUS_ERR_MASK) { |
426 | dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat); | 412 | dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat); |
427 | if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR)) | 413 | if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR)) |
428 | data->error = -EILSEQ; | 414 | data->error = -EILSEQ; |
429 | else if(stat & STATUS_TIME_OUT_READ) | 415 | else if (stat & STATUS_TIME_OUT_READ) |
430 | data->error = -ETIMEDOUT; | 416 | data->error = -ETIMEDOUT; |
431 | else | 417 | else |
432 | data->error = -EIO; | 418 | data->error = -EIO; |
@@ -445,7 +431,7 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat) | |||
445 | { | 431 | { |
446 | struct mmc_command *cmd = host->cmd; | 432 | struct mmc_command *cmd = host->cmd; |
447 | int i; | 433 | int i; |
448 | u32 a,b,c; | 434 | u32 a, b, c; |
449 | struct mmc_data *data = host->data; | 435 | struct mmc_data *data = host->data; |
450 | 436 | ||
451 | if (!cmd) | 437 | if (!cmd) |
@@ -461,18 +447,18 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat) | |||
461 | cmd->error = -EILSEQ; | 447 | cmd->error = -EILSEQ; |
462 | } | 448 | } |
463 | 449 | ||
464 | if(cmd->flags & MMC_RSP_PRESENT) { | 450 | if (cmd->flags & MMC_RSP_PRESENT) { |
465 | if(cmd->flags & MMC_RSP_136) { | 451 | if (cmd->flags & MMC_RSP_136) { |
466 | for (i = 0; i < 4; i++) { | 452 | for (i = 0; i < 4; i++) { |
467 | u32 a = MMC_RES_FIFO & 0xffff; | 453 | u32 d = MMC_RES_FIFO & 0xffff; |
468 | u32 b = MMC_RES_FIFO & 0xffff; | 454 | u32 e = MMC_RES_FIFO & 0xffff; |
469 | cmd->resp[i] = a<<16 | b; | 455 | cmd->resp[i] = d << 16 | e; |
470 | } | 456 | } |
471 | } else { | 457 | } else { |
472 | a = MMC_RES_FIFO & 0xffff; | 458 | a = MMC_RES_FIFO & 0xffff; |
473 | b = MMC_RES_FIFO & 0xffff; | 459 | b = MMC_RES_FIFO & 0xffff; |
474 | c = MMC_RES_FIFO & 0xffff; | 460 | c = MMC_RES_FIFO & 0xffff; |
475 | cmd->resp[0] = a<<24 | b<<8 | c>>8; | 461 | cmd->resp[0] = a << 24 | b << 8 | c >> 8; |
476 | } | 462 | } |
477 | } | 463 | } |
478 | 464 | ||
@@ -485,35 +471,33 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat) | |||
485 | /* Wait for FIFO to be empty before starting DMA write */ | 471 | /* Wait for FIFO to be empty before starting DMA write */ |
486 | 472 | ||
487 | stat = MMC_STATUS; | 473 | stat = MMC_STATUS; |
488 | if(imxmci_busy_wait_for_status(host, &stat, | 474 | if (imxmci_busy_wait_for_status(host, &stat, |
489 | STATUS_APPL_BUFF_FE, | 475 | STATUS_APPL_BUFF_FE, |
490 | 40, "imxmci_cmd_done DMA WR") < 0) { | 476 | 40, "imxmci_cmd_done DMA WR") < 0) { |
491 | cmd->error = -EIO; | 477 | cmd->error = -EIO; |
492 | imxmci_finish_data(host, stat); | 478 | imxmci_finish_data(host, stat); |
493 | if(host->req) | 479 | if (host->req) |
494 | imxmci_finish_request(host, host->req); | 480 | imxmci_finish_request(host, host->req); |
495 | dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n", | 481 | dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n", |
496 | stat); | 482 | stat); |
497 | return 0; | 483 | return 0; |
498 | } | 484 | } |
499 | 485 | ||
500 | if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { | 486 | if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) |
501 | imx_dma_enable(host->dma); | 487 | imx_dma_enable(host->dma); |
502 | } | ||
503 | } | 488 | } |
504 | } else { | 489 | } else { |
505 | struct mmc_request *req; | 490 | struct mmc_request *req; |
506 | imxmci_stop_clock(host); | 491 | imxmci_stop_clock(host); |
507 | req = host->req; | 492 | req = host->req; |
508 | 493 | ||
509 | if(data) | 494 | if (data) |
510 | imxmci_finish_data(host, stat); | 495 | imxmci_finish_data(host, stat); |
511 | 496 | ||
512 | if( req ) { | 497 | if (req) |
513 | imxmci_finish_request(host, req); | 498 | imxmci_finish_request(host, req); |
514 | } else { | 499 | else |
515 | dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n"); | 500 | dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n"); |
516 | } | ||
517 | } | 501 | } |
518 | 502 | ||
519 | return 1; | 503 | return 1; |
@@ -535,11 +519,10 @@ static int imxmci_data_done(struct imxmci_host *host, unsigned int stat) | |||
535 | } else { | 519 | } else { |
536 | struct mmc_request *req; | 520 | struct mmc_request *req; |
537 | req = host->req; | 521 | req = host->req; |
538 | if( req ) { | 522 | if (req) |
539 | imxmci_finish_request(host, req); | 523 | imxmci_finish_request(host, req); |
540 | } else { | 524 | else |
541 | dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n"); | 525 | dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n"); |
542 | } | ||
543 | } | 526 | } |
544 | 527 | ||
545 | return 1; | 528 | return 1; |
@@ -552,7 +535,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) | |||
552 | int trans_done = 0; | 535 | int trans_done = 0; |
553 | unsigned int stat = *pstat; | 536 | unsigned int stat = *pstat; |
554 | 537 | ||
555 | if(host->actual_bus_width != MMC_BUS_WIDTH_4) | 538 | if (host->actual_bus_width != MMC_BUS_WIDTH_4) |
556 | burst_len = 16; | 539 | burst_len = 16; |
557 | else | 540 | else |
558 | burst_len = 64; | 541 | burst_len = 64; |
@@ -563,27 +546,27 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) | |||
563 | 546 | ||
564 | udelay(20); /* required for clocks < 8MHz*/ | 547 | udelay(20); /* required for clocks < 8MHz*/ |
565 | 548 | ||
566 | if(host->dma_dir == DMA_FROM_DEVICE) { | 549 | if (host->dma_dir == DMA_FROM_DEVICE) { |
567 | imxmci_busy_wait_for_status(host, &stat, | 550 | imxmci_busy_wait_for_status(host, &stat, |
568 | STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE | | 551 | STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE | |
569 | STATUS_TIME_OUT_READ, | 552 | STATUS_TIME_OUT_READ, |
570 | 50, "imxmci_cpu_driven_data read"); | 553 | 50, "imxmci_cpu_driven_data read"); |
571 | 554 | ||
572 | while((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) && | 555 | while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) && |
573 | !(stat & STATUS_TIME_OUT_READ) && | 556 | !(stat & STATUS_TIME_OUT_READ) && |
574 | (host->data_cnt < 512)) { | 557 | (host->data_cnt < 512)) { |
575 | 558 | ||
576 | udelay(20); /* required for clocks < 8MHz*/ | 559 | udelay(20); /* required for clocks < 8MHz*/ |
577 | 560 | ||
578 | for(i = burst_len; i>=2 ; i-=2) { | 561 | for (i = burst_len; i >= 2 ; i -= 2) { |
579 | u16 data; | 562 | u16 data; |
580 | data = MMC_BUFFER_ACCESS; | 563 | data = MMC_BUFFER_ACCESS; |
581 | udelay(10); /* required for clocks < 8MHz*/ | 564 | udelay(10); /* required for clocks < 8MHz*/ |
582 | if(host->data_cnt+2 <= host->dma_size) { | 565 | if (host->data_cnt+2 <= host->dma_size) { |
583 | *(host->data_ptr++) = data; | 566 | *(host->data_ptr++) = data; |
584 | } else { | 567 | } else { |
585 | if(host->data_cnt < host->dma_size) | 568 | if (host->data_cnt < host->dma_size) |
586 | *(u8*)(host->data_ptr) = data; | 569 | *(u8 *)(host->data_ptr) = data; |
587 | } | 570 | } |
588 | host->data_cnt += 2; | 571 | host->data_cnt += 2; |
589 | } | 572 | } |
@@ -594,13 +577,13 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) | |||
594 | host->data_cnt, burst_len, stat); | 577 | host->data_cnt, burst_len, stat); |
595 | } | 578 | } |
596 | 579 | ||
597 | if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512)) | 580 | if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512)) |
598 | trans_done = 1; | 581 | trans_done = 1; |
599 | 582 | ||
600 | if(host->dma_size & 0x1ff) | 583 | if (host->dma_size & 0x1ff) |
601 | stat &= ~STATUS_CRC_READ_ERR; | 584 | stat &= ~STATUS_CRC_READ_ERR; |
602 | 585 | ||
603 | if(stat & STATUS_TIME_OUT_READ) { | 586 | if (stat & STATUS_TIME_OUT_READ) { |
604 | dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n", | 587 | dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n", |
605 | stat); | 588 | stat); |
606 | trans_done = -1; | 589 | trans_done = -1; |
@@ -608,12 +591,12 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) | |||
608 | 591 | ||
609 | } else { | 592 | } else { |
610 | imxmci_busy_wait_for_status(host, &stat, | 593 | imxmci_busy_wait_for_status(host, &stat, |
611 | STATUS_APPL_BUFF_FE, | 594 | STATUS_APPL_BUFF_FE, |
612 | 20, "imxmci_cpu_driven_data write"); | 595 | 20, "imxmci_cpu_driven_data write"); |
613 | 596 | ||
614 | while((stat & STATUS_APPL_BUFF_FE) && | 597 | while ((stat & STATUS_APPL_BUFF_FE) && |
615 | (host->data_cnt < host->dma_size)) { | 598 | (host->data_cnt < host->dma_size)) { |
616 | if(burst_len >= host->dma_size - host->data_cnt) { | 599 | if (burst_len >= host->dma_size - host->data_cnt) { |
617 | burst_len = host->dma_size - host->data_cnt; | 600 | burst_len = host->dma_size - host->data_cnt; |
618 | host->data_cnt = host->dma_size; | 601 | host->data_cnt = host->dma_size; |
619 | trans_done = 1; | 602 | trans_done = 1; |
@@ -621,7 +604,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) | |||
621 | host->data_cnt += burst_len; | 604 | host->data_cnt += burst_len; |
622 | } | 605 | } |
623 | 606 | ||
624 | for(i = burst_len; i>0 ; i-=2) | 607 | for (i = burst_len; i > 0 ; i -= 2) |
625 | MMC_BUFFER_ACCESS = *(host->data_ptr++); | 608 | MMC_BUFFER_ACCESS = *(host->data_ptr++); |
626 | 609 | ||
627 | stat = MMC_STATUS; | 610 | stat = MMC_STATUS; |
@@ -671,7 +654,7 @@ static void imxmci_tasklet_fnc(unsigned long data) | |||
671 | unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */ | 654 | unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */ |
672 | int timeout = 0; | 655 | int timeout = 0; |
673 | 656 | ||
674 | if(atomic_read(&host->stuck_timeout) > 4) { | 657 | if (atomic_read(&host->stuck_timeout) > 4) { |
675 | char *what; | 658 | char *what; |
676 | timeout = 1; | 659 | timeout = 1; |
677 | stat = MMC_STATUS; | 660 | stat = MMC_STATUS; |
@@ -683,7 +666,7 @@ static void imxmci_tasklet_fnc(unsigned long data) | |||
683 | what = "RESP"; | 666 | what = "RESP"; |
684 | else | 667 | else |
685 | if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) | 668 | if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) |
686 | if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events)) | 669 | if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events)) |
687 | what = "DATA"; | 670 | what = "DATA"; |
688 | else | 671 | else |
689 | what = "DMA"; | 672 | what = "DMA"; |
@@ -691,18 +674,18 @@ static void imxmci_tasklet_fnc(unsigned long data) | |||
691 | what = "???"; | 674 | what = "???"; |
692 | 675 | ||
693 | dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n", | 676 | dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n", |
694 | what, stat, MMC_INT_MASK); | 677 | what, stat, MMC_INT_MASK); |
695 | dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n", | 678 | dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n", |
696 | MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma)); | 679 | MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma)); |
697 | dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n", | 680 | dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n", |
698 | host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size); | 681 | host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1 << host->actual_bus_width, host->dma_size); |
699 | } | 682 | } |
700 | 683 | ||
701 | if(!host->present || timeout) | 684 | if (!host->present || timeout) |
702 | host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ | | 685 | host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ | |
703 | STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR; | 686 | STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR; |
704 | 687 | ||
705 | if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) { | 688 | if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) { |
706 | clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events); | 689 | clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events); |
707 | 690 | ||
708 | stat = MMC_STATUS; | 691 | stat = MMC_STATUS; |
@@ -713,63 +696,62 @@ static void imxmci_tasklet_fnc(unsigned long data) | |||
713 | */ | 696 | */ |
714 | stat |= host->status_reg; | 697 | stat |= host->status_reg; |
715 | 698 | ||
716 | if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) | 699 | if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) |
717 | stat &= ~STATUS_CRC_READ_ERR; | 700 | stat &= ~STATUS_CRC_READ_ERR; |
718 | 701 | ||
719 | if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { | 702 | if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { |
720 | imxmci_busy_wait_for_status(host, &stat, | 703 | imxmci_busy_wait_for_status(host, &stat, |
721 | STATUS_END_CMD_RESP | STATUS_ERR_MASK, | 704 | STATUS_END_CMD_RESP | STATUS_ERR_MASK, |
722 | 20, "imxmci_tasklet_fnc resp (ERRATUM #4)"); | 705 | 20, "imxmci_tasklet_fnc resp (ERRATUM #4)"); |
723 | } | 706 | } |
724 | 707 | ||
725 | if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) { | 708 | if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) { |
726 | if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) | 709 | if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) |
727 | imxmci_cmd_done(host, stat); | 710 | imxmci_cmd_done(host, stat); |
728 | if(host->data && (stat & STATUS_ERR_MASK)) | 711 | if (host->data && (stat & STATUS_ERR_MASK)) |
729 | imxmci_data_done(host, stat); | 712 | imxmci_data_done(host, stat); |
730 | } | 713 | } |
731 | 714 | ||
732 | if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) { | 715 | if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) { |
733 | stat |= MMC_STATUS; | 716 | stat |= MMC_STATUS; |
734 | if(imxmci_cpu_driven_data(host, &stat)){ | 717 | if (imxmci_cpu_driven_data(host, &stat)) { |
735 | if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) | 718 | if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) |
736 | imxmci_cmd_done(host, stat); | 719 | imxmci_cmd_done(host, stat); |
737 | atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m, | 720 | atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m, |
738 | &host->pending_events); | 721 | &host->pending_events); |
739 | imxmci_data_done(host, stat); | 722 | imxmci_data_done(host, stat); |
740 | } | 723 | } |
741 | } | 724 | } |
742 | } | 725 | } |
743 | 726 | ||
744 | if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) && | 727 | if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) && |
745 | !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { | 728 | !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { |
746 | 729 | ||
747 | stat = MMC_STATUS; | 730 | stat = MMC_STATUS; |
748 | /* Same as above */ | 731 | /* Same as above */ |
749 | stat |= host->status_reg; | 732 | stat |= host->status_reg; |
750 | 733 | ||
751 | if(host->dma_dir == DMA_TO_DEVICE) { | 734 | if (host->dma_dir == DMA_TO_DEVICE) |
752 | data_dir_mask = STATUS_WRITE_OP_DONE; | 735 | data_dir_mask = STATUS_WRITE_OP_DONE; |
753 | } else { | 736 | else |
754 | data_dir_mask = STATUS_DATA_TRANS_DONE; | 737 | data_dir_mask = STATUS_DATA_TRANS_DONE; |
755 | } | ||
756 | 738 | ||
757 | if(stat & data_dir_mask) { | 739 | if (stat & data_dir_mask) { |
758 | clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events); | 740 | clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events); |
759 | imxmci_data_done(host, stat); | 741 | imxmci_data_done(host, stat); |
760 | } | 742 | } |
761 | } | 743 | } |
762 | 744 | ||
763 | if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) { | 745 | if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) { |
764 | 746 | ||
765 | if(host->cmd) | 747 | if (host->cmd) |
766 | imxmci_cmd_done(host, STATUS_TIME_OUT_RESP); | 748 | imxmci_cmd_done(host, STATUS_TIME_OUT_RESP); |
767 | 749 | ||
768 | if(host->data) | 750 | if (host->data) |
769 | imxmci_data_done(host, STATUS_TIME_OUT_READ | | 751 | imxmci_data_done(host, STATUS_TIME_OUT_READ | |
770 | STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR); | 752 | STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR); |
771 | 753 | ||
772 | if(host->req) | 754 | if (host->req) |
773 | imxmci_finish_request(host, host->req); | 755 | imxmci_finish_request(host, host->req); |
774 | 756 | ||
775 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); | 757 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); |
@@ -796,9 +778,8 @@ static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req) | |||
796 | if (req->data->flags & MMC_DATA_WRITE) | 778 | if (req->data->flags & MMC_DATA_WRITE) |
797 | cmdat |= CMD_DAT_CONT_WRITE; | 779 | cmdat |= CMD_DAT_CONT_WRITE; |
798 | 780 | ||
799 | if (req->data->flags & MMC_DATA_STREAM) { | 781 | if (req->data->flags & MMC_DATA_STREAM) |
800 | cmdat |= CMD_DAT_CONT_STREAM_BLOCK; | 782 | cmdat |= CMD_DAT_CONT_STREAM_BLOCK; |
801 | } | ||
802 | } | 783 | } |
803 | 784 | ||
804 | imxmci_start_cmd(host, req->cmd, cmdat); | 785 | imxmci_start_cmd(host, req->cmd, cmdat); |
@@ -811,36 +792,36 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
811 | struct imxmci_host *host = mmc_priv(mmc); | 792 | struct imxmci_host *host = mmc_priv(mmc); |
812 | int prescaler; | 793 | int prescaler; |
813 | 794 | ||
814 | if( ios->bus_width==MMC_BUS_WIDTH_4 ) { | 795 | if (ios->bus_width == MMC_BUS_WIDTH_4) { |
815 | host->actual_bus_width = MMC_BUS_WIDTH_4; | 796 | host->actual_bus_width = MMC_BUS_WIDTH_4; |
816 | imx_gpio_mode(PB11_PF_SD_DAT3); | 797 | imx_gpio_mode(PB11_PF_SD_DAT3); |
817 | }else{ | 798 | } else { |
818 | host->actual_bus_width = MMC_BUS_WIDTH_1; | 799 | host->actual_bus_width = MMC_BUS_WIDTH_1; |
819 | imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11); | 800 | imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11); |
820 | } | 801 | } |
821 | 802 | ||
822 | if ( host->power_mode != ios->power_mode ) { | 803 | if (host->power_mode != ios->power_mode) { |
823 | switch (ios->power_mode) { | 804 | switch (ios->power_mode) { |
824 | case MMC_POWER_OFF: | 805 | case MMC_POWER_OFF: |
825 | break; | 806 | break; |
826 | case MMC_POWER_UP: | 807 | case MMC_POWER_UP: |
827 | set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); | 808 | set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); |
828 | break; | 809 | break; |
829 | case MMC_POWER_ON: | 810 | case MMC_POWER_ON: |
830 | break; | 811 | break; |
831 | } | 812 | } |
832 | host->power_mode = ios->power_mode; | 813 | host->power_mode = ios->power_mode; |
833 | } | 814 | } |
834 | 815 | ||
835 | if ( ios->clock ) { | 816 | if (ios->clock) { |
836 | unsigned int clk; | 817 | unsigned int clk; |
837 | 818 | ||
838 | /* The prescaler is 5 for PERCLK2 equal to 96MHz | 819 | /* The prescaler is 5 for PERCLK2 equal to 96MHz |
839 | * then 96MHz / 5 = 19.2 MHz | 820 | * then 96MHz / 5 = 19.2 MHz |
840 | */ | 821 | */ |
841 | clk = clk_get_rate(host->clk); | 822 | clk = clk_get_rate(host->clk); |
842 | prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE; | 823 | prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE; |
843 | switch(prescaler) { | 824 | switch (prescaler) { |
844 | case 0: | 825 | case 0: |
845 | case 1: prescaler = 0; | 826 | case 1: prescaler = 0; |
846 | break; | 827 | break; |
@@ -858,22 +839,22 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
858 | dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n", | 839 | dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n", |
859 | clk, prescaler); | 840 | clk, prescaler); |
860 | 841 | ||
861 | for(clk=0; clk<8; clk++) { | 842 | for (clk = 0; clk < 8; clk++) { |
862 | int x; | 843 | int x; |
863 | x = CLK_RATE / (1<<clk); | 844 | x = CLK_RATE / (1 << clk); |
864 | if( x <= ios->clock) | 845 | if (x <= ios->clock) |
865 | break; | 846 | break; |
866 | } | 847 | } |
867 | 848 | ||
868 | MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */ | 849 | MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */ |
869 | 850 | ||
870 | imxmci_stop_clock(host); | 851 | imxmci_stop_clock(host); |
871 | MMC_CLK_RATE = (prescaler<<3) | clk; | 852 | MMC_CLK_RATE = (prescaler << 3) | clk; |
872 | /* | 853 | /* |
873 | * Under my understanding, clock should not be started there, because it would | 854 | * Under my understanding, clock should not be started there, because it would |
874 | * initiate SDHC sequencer and send last or random command into card | 855 | * initiate SDHC sequencer and send last or random command into card |
875 | */ | 856 | */ |
876 | /*imxmci_start_clock(host);*/ | 857 | /* imxmci_start_clock(host); */ |
877 | 858 | ||
878 | dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE); | 859 | dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE); |
879 | } else { | 860 | } else { |
@@ -915,10 +896,10 @@ static void imxmci_check_status(unsigned long data) | |||
915 | tasklet_schedule(&host->tasklet); | 896 | tasklet_schedule(&host->tasklet); |
916 | } | 897 | } |
917 | 898 | ||
918 | if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) || | 899 | if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) || |
919 | test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { | 900 | test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { |
920 | atomic_inc(&host->stuck_timeout); | 901 | atomic_inc(&host->stuck_timeout); |
921 | if(atomic_read(&host->stuck_timeout) > 4) | 902 | if (atomic_read(&host->stuck_timeout) > 4) |
922 | tasklet_schedule(&host->tasklet); | 903 | tasklet_schedule(&host->tasklet); |
923 | } else { | 904 | } else { |
924 | atomic_set(&host->stuck_timeout, 0); | 905 | atomic_set(&host->stuck_timeout, 0); |
@@ -995,9 +976,9 @@ static int imxmci_probe(struct platform_device *pdev) | |||
995 | 976 | ||
996 | imxmci_softreset(); | 977 | imxmci_softreset(); |
997 | 978 | ||
998 | if ( MMC_REV_NO != 0x390 ) { | 979 | if (MMC_REV_NO != 0x390) { |
999 | dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", | 980 | dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", |
1000 | MMC_REV_NO); | 981 | MMC_REV_NO); |
1001 | goto out; | 982 | goto out; |
1002 | } | 983 | } |
1003 | 984 | ||
@@ -1012,7 +993,7 @@ static int imxmci_probe(struct platform_device *pdev) | |||
1012 | ret = -EBUSY; | 993 | ret = -EBUSY; |
1013 | goto out; | 994 | goto out; |
1014 | } | 995 | } |
1015 | host->dma_allocated=1; | 996 | host->dma_allocated = 1; |
1016 | imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host); | 997 | imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host); |
1017 | 998 | ||
1018 | tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host); | 999 | tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host); |
@@ -1032,7 +1013,7 @@ static int imxmci_probe(struct platform_device *pdev) | |||
1032 | host->timer.data = (unsigned long)host; | 1013 | host->timer.data = (unsigned long)host; |
1033 | host->timer.function = imxmci_check_status; | 1014 | host->timer.function = imxmci_check_status; |
1034 | add_timer(&host->timer); | 1015 | add_timer(&host->timer); |
1035 | mod_timer(&host->timer, jiffies + (HZ>>1)); | 1016 | mod_timer(&host->timer, jiffies + (HZ >> 1)); |
1036 | 1017 | ||
1037 | platform_set_drvdata(pdev, mmc); | 1018 | platform_set_drvdata(pdev, mmc); |
1038 | 1019 | ||
@@ -1042,9 +1023,9 @@ static int imxmci_probe(struct platform_device *pdev) | |||
1042 | 1023 | ||
1043 | out: | 1024 | out: |
1044 | if (host) { | 1025 | if (host) { |
1045 | if(host->dma_allocated){ | 1026 | if (host->dma_allocated) { |
1046 | imx_dma_free(host->dma); | 1027 | imx_dma_free(host->dma); |
1047 | host->dma_allocated=0; | 1028 | host->dma_allocated = 0; |
1048 | } | 1029 | } |
1049 | if (host->clk) { | 1030 | if (host->clk) { |
1050 | clk_disable(host->clk); | 1031 | clk_disable(host->clk); |
@@ -1072,9 +1053,9 @@ static int imxmci_remove(struct platform_device *pdev) | |||
1072 | mmc_remove_host(mmc); | 1053 | mmc_remove_host(mmc); |
1073 | 1054 | ||
1074 | free_irq(host->irq, host); | 1055 | free_irq(host->irq, host); |
1075 | if(host->dma_allocated){ | 1056 | if (host->dma_allocated) { |
1076 | imx_dma_free(host->dma); | 1057 | imx_dma_free(host->dma); |
1077 | host->dma_allocated=0; | 1058 | host->dma_allocated = 0; |
1078 | } | 1059 | } |
1079 | 1060 | ||
1080 | tasklet_kill(&host->tasklet); | 1061 | tasklet_kill(&host->tasklet); |
@@ -1109,7 +1090,7 @@ static int imxmci_resume(struct platform_device *dev) | |||
1109 | 1090 | ||
1110 | if (mmc) { | 1091 | if (mmc) { |
1111 | host = mmc_priv(mmc); | 1092 | host = mmc_priv(mmc); |
1112 | if(host) | 1093 | if (host) |
1113 | set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); | 1094 | set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); |
1114 | ret = mmc_resume_host(mmc); | 1095 | ret = mmc_resume_host(mmc); |
1115 | } | 1096 | } |