sdhci: Add support for bus-specific IO memory accessors

Currently the SDHCI driver works with PCI accessors (write{l,b,w} and
read{l,b,w}).

With this patch drivers may change memory accessors, so that we can
support hosts with "weird" IO memory access requirments.

For example, in "FSL eSDHC" SDHCI hardware all registers are 32 bit
width, with big-endian addressing. That is, readb(0x2f) should turn
into readb(0x2c), and readw(0x2c) should be translated to
le16_to_cpu(readw(0x2e)).

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 092baf66733c..e8a7b50a01e7 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -37,6 +37,13 @@ config MMC_SDHCI
 
           If unsure, say N.
 
+config MMC_SDHCI_IO_ACCESSORS
+        bool
+        depends on MMC_SDHCI
+        help
+          This is silent Kconfig symbol that is selected by the drivers that
+          need to overwrite SDHCI IO memory accessors.
+
 config MMC_SDHCI_PCI
         tristate "SDHCI support on PCI bus"
         depends on MMC_SDHCI && PCI