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authorTomas Winkler <tomas.winkler@intel.com>2014-05-12 18:30:54 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-05-27 17:16:38 -0400
commitc919951d940f28b3b9eb208e289faa27f4bc4678 (patch)
tree53dbcda8cd1a160493eaaed77d0a3f2465df7228 /drivers/misc
parent8d929d4862fdfc4a524fd4c799b8dfa3b187fe8c (diff)
mei: me: move probe quirk to cfg structure
Move quirk FW type detector to cfg structure Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/misc')
-rw-r--r--drivers/misc/mei/hw-me.c37
-rw-r--r--drivers/misc/mei/hw-me.h2
-rw-r--r--drivers/misc/mei/mei_dev.h2
-rw-r--r--drivers/misc/mei/pci-me.c47
4 files changed, 54 insertions, 34 deletions
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index ed081182f973..6a2d272cea43 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -792,6 +792,30 @@ static const struct mei_hw_ops mei_me_hw_ops = {
792 .read = mei_me_read_slots 792 .read = mei_me_read_slots
793}; 793};
794 794
795static bool mei_me_fw_type_nm(struct pci_dev *pdev)
796{
797 u32 reg;
798 pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg);
799 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
800 return (reg & 0x600) == 0x200;
801}
802
803#define MEI_CFG_FW_NM \
804 .quirk_probe = mei_me_fw_type_nm
805
806static bool mei_me_fw_type_sps(struct pci_dev *pdev)
807{
808 u32 reg;
809 /* Read ME FW Status check for SPS Firmware */
810 pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
811 /* if bits [19:16] = 15, running SPS Firmware */
812 return (reg & 0xf0000) == 0xf0000;
813}
814
815#define MEI_CFG_FW_SPS \
816 .quirk_probe = mei_me_fw_type_sps
817
818
795#define MEI_CFG_LEGACY_HFS \ 819#define MEI_CFG_LEGACY_HFS \
796 .fw_status.count = 0 820 .fw_status.count = 0
797 821
@@ -820,6 +844,19 @@ const struct mei_cfg mei_me_pch_cfg = {
820 MEI_CFG_PCH_HFS, 844 MEI_CFG_PCH_HFS,
821}; 845};
822 846
847
848/* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
849const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
850 MEI_CFG_PCH_HFS,
851 MEI_CFG_FW_NM,
852};
853
854/* PCH Lynx Point with quirk for SPS Firmware exclusion */
855const struct mei_cfg mei_me_lpt_cfg = {
856 MEI_CFG_PCH_HFS,
857 MEI_CFG_FW_SPS,
858};
859
823/** 860/**
824 * mei_me_dev_init - allocates and initializes the mei device structure 861 * mei_me_dev_init - allocates and initializes the mei device structure
825 * 862 *
diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
index 473aafbc4023..12b0f4bbe1f1 100644
--- a/drivers/misc/mei/hw-me.h
+++ b/drivers/misc/mei/hw-me.h
@@ -41,6 +41,8 @@ struct mei_me_hw {
41extern const struct mei_cfg mei_me_legacy_cfg; 41extern const struct mei_cfg mei_me_legacy_cfg;
42extern const struct mei_cfg mei_me_ich_cfg; 42extern const struct mei_cfg mei_me_ich_cfg;
43extern const struct mei_cfg mei_me_pch_cfg; 43extern const struct mei_cfg mei_me_pch_cfg;
44extern const struct mei_cfg mei_me_pch_cpt_pbg_cfg;
45extern const struct mei_cfg mei_me_lpt_cfg;
44 46
45struct mei_device *mei_me_dev_init(struct pci_dev *pdev, 47struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
46 const struct mei_cfg *cfg); 48 const struct mei_cfg *cfg);
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 909d13de17e9..5c7e990e2f22 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -383,9 +383,11 @@ enum mei_pg_state {
383 * mei_cfg 383 * mei_cfg
384 * 384 *
385 * @fw_status - FW status 385 * @fw_status - FW status
386 * @quirk_probe - device exclusion quirk
386 */ 387 */
387struct mei_cfg { 388struct mei_cfg {
388 const struct mei_fw_status fw_status; 389 const struct mei_fw_status fw_status;
390 bool (*quirk_probe)(struct pci_dev *pdev);
389}; 391};
390 392
391 393
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index 6cb9819ac5d5..1b46c64a649f 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -72,15 +72,15 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
72 72
73 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)}, 73 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)}, 74 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cfg)}, 75 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
76 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cfg)}, 76 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
77 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)}, 77 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
78 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)}, 78 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
79 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)}, 79 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
80 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch_cfg)}, 80 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_lpt_cfg)},
81 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch_cfg)}, 81 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_lpt_cfg)},
82 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch_cfg)}, 82 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch_cfg)},
83 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch_cfg)}, 83 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_lpt_cfg)},
84 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch_cfg)}, 84 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch_cfg)},
85 85
86 /* required last entry */ 86 /* required last entry */
@@ -101,40 +101,21 @@ static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
101 * mei_quirk_probe - probe for devices that doesn't valid ME interface 101 * mei_quirk_probe - probe for devices that doesn't valid ME interface
102 * 102 *
103 * @pdev: PCI device structure 103 * @pdev: PCI device structure
104 * @ent: entry into pci_device_table 104 * @cfg: per generation config
105 * 105 *
106 * returns true if ME Interface is valid, false otherwise 106 * returns true if ME Interface is valid, false otherwise
107 */ 107 */
108static bool mei_me_quirk_probe(struct pci_dev *pdev, 108static bool mei_me_quirk_probe(struct pci_dev *pdev,
109 const struct pci_device_id *ent) 109 const struct mei_cfg *cfg)
110{ 110{
111 u32 reg; 111 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
112 /* Cougar Point || Patsburg */ 112 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
113 if (ent->device == MEI_DEV_ID_CPT_1 || 113 return false;
114 ent->device == MEI_DEV_ID_PBG_1) {
115 pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg);
116 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
117 if ((reg & 0x600) == 0x200)
118 goto no_mei;
119 }
120
121 /* Lynx Point */
122 if (ent->device == MEI_DEV_ID_LPT_H ||
123 ent->device == MEI_DEV_ID_LPT_W ||
124 ent->device == MEI_DEV_ID_LPT_HR) {
125 /* Read ME FW Status check for SPS Firmware */
126 pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
127 /* if bits [19:16] = 15, running SPS Firmware */
128 if ((reg & 0xf0000) == 0xf0000)
129 goto no_mei;
130 } 114 }
131 115
132 return true; 116 return true;
133
134no_mei:
135 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
136 return false;
137} 117}
118
138/** 119/**
139 * mei_probe - Device Initialization Routine 120 * mei_probe - Device Initialization Routine
140 * 121 *
@@ -151,10 +132,8 @@ static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
151 int err; 132 int err;
152 133
153 134
154 if (!mei_me_quirk_probe(pdev, ent)) { 135 if (!mei_me_quirk_probe(pdev, cfg))
155 err = -ENODEV; 136 return -ENODEV;
156 goto end;
157 }
158 137
159 /* enable pci dev */ 138 /* enable pci dev */
160 err = pci_enable_device(pdev); 139 err = pci_enable_device(pdev);