diff options
author | Tomas Winkler <tomas.winkler@intel.com> | 2012-11-18 08:13:18 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-11-21 15:43:58 -0500 |
commit | 9a84d616980215d1d9222173c60329b57680483b (patch) | |
tree | a02f3ebc461b39f09eab24467bc3547eb12164df /drivers/misc | |
parent | 24c656e55f3985b6f5c0e2264243f7076f376193 (diff) |
mei: don't mix read and write slots
Do not pass read slots pointer into function
mei_irq_thread_write_handler, the write
slots management is handled internally in the write
handler
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/misc')
-rw-r--r-- | drivers/misc/mei/interrupt.c | 35 |
1 files changed, 19 insertions, 16 deletions
diff --git a/drivers/misc/mei/interrupt.c b/drivers/misc/mei/interrupt.c index d30db38d6188..cccb63a8c007 100644 --- a/drivers/misc/mei/interrupt.c +++ b/drivers/misc/mei/interrupt.c | |||
@@ -901,27 +901,27 @@ end: | |||
901 | * mei_irq_thread_write_handler - bottom half write routine after | 901 | * mei_irq_thread_write_handler - bottom half write routine after |
902 | * ISR to handle the write processing. | 902 | * ISR to handle the write processing. |
903 | * | 903 | * |
904 | * @cmpl_list: An instance of our list structure | ||
905 | * @dev: the device structure | 904 | * @dev: the device structure |
906 | * @slots: slots to write. | 905 | * @cmpl_list: An instance of our list structure |
907 | * | 906 | * |
908 | * returns 0 on success, <0 on failure. | 907 | * returns 0 on success, <0 on failure. |
909 | */ | 908 | */ |
910 | static int mei_irq_thread_write_handler(struct mei_cl_cb *cmpl_list, | 909 | static int mei_irq_thread_write_handler(struct mei_device *dev, |
911 | struct mei_device *dev, s32 *slots) | 910 | struct mei_cl_cb *cmpl_list) |
912 | { | 911 | { |
913 | 912 | ||
914 | struct mei_cl *cl; | 913 | struct mei_cl *cl; |
915 | struct mei_cl_cb *pos = NULL, *next = NULL; | 914 | struct mei_cl_cb *pos = NULL, *next = NULL; |
916 | struct mei_cl_cb *list; | 915 | struct mei_cl_cb *list; |
916 | s32 slots; | ||
917 | int ret; | 917 | int ret; |
918 | 918 | ||
919 | if (!mei_hbuf_is_empty(dev)) { | 919 | if (!mei_hbuf_is_empty(dev)) { |
920 | dev_dbg(&dev->pdev->dev, "host buffer is not empty.\n"); | 920 | dev_dbg(&dev->pdev->dev, "host buffer is not empty.\n"); |
921 | return 0; | 921 | return 0; |
922 | } | 922 | } |
923 | *slots = mei_hbuf_empty_slots(dev); | 923 | slots = mei_hbuf_empty_slots(dev); |
924 | if (*slots <= 0) | 924 | if (slots <= 0) |
925 | return -EMSGSIZE; | 925 | return -EMSGSIZE; |
926 | 926 | ||
927 | /* complete all waiting for write CB */ | 927 | /* complete all waiting for write CB */ |
@@ -945,7 +945,7 @@ static int mei_irq_thread_write_handler(struct mei_cl_cb *cmpl_list, | |||
945 | if (cl == &dev->iamthif_cl) { | 945 | if (cl == &dev->iamthif_cl) { |
946 | dev_dbg(&dev->pdev->dev, "check iamthif flow control.\n"); | 946 | dev_dbg(&dev->pdev->dev, "check iamthif flow control.\n"); |
947 | if (dev->iamthif_flow_control_pending) { | 947 | if (dev->iamthif_flow_control_pending) { |
948 | ret = mei_amthif_irq_read(dev, slots); | 948 | ret = mei_amthif_irq_read(dev, &slots); |
949 | if (ret) | 949 | if (ret) |
950 | return ret; | 950 | return ret; |
951 | } | 951 | } |
@@ -960,7 +960,7 @@ static int mei_irq_thread_write_handler(struct mei_cl_cb *cmpl_list, | |||
960 | if (dev->wr_ext_msg.hdr.length) { | 960 | if (dev->wr_ext_msg.hdr.length) { |
961 | mei_write_message(dev, &dev->wr_ext_msg.hdr, | 961 | mei_write_message(dev, &dev->wr_ext_msg.hdr, |
962 | dev->wr_ext_msg.data, dev->wr_ext_msg.hdr.length); | 962 | dev->wr_ext_msg.data, dev->wr_ext_msg.hdr.length); |
963 | *slots -= mei_data2slots(dev->wr_ext_msg.hdr.length); | 963 | slots -= mei_data2slots(dev->wr_ext_msg.hdr.length); |
964 | dev->wr_ext_msg.hdr.length = 0; | 964 | dev->wr_ext_msg.hdr.length = 0; |
965 | } | 965 | } |
966 | if (dev->dev_state == MEI_DEV_ENABLED) { | 966 | if (dev->dev_state == MEI_DEV_ENABLED) { |
@@ -974,9 +974,9 @@ static int mei_irq_thread_write_handler(struct mei_cl_cb *cmpl_list, | |||
974 | dev->wd_pending = false; | 974 | dev->wd_pending = false; |
975 | 975 | ||
976 | if (dev->wd_state == MEI_WD_RUNNING) | 976 | if (dev->wd_state == MEI_WD_RUNNING) |
977 | *slots -= mei_data2slots(MEI_WD_START_MSG_SIZE); | 977 | slots -= mei_data2slots(MEI_WD_START_MSG_SIZE); |
978 | else | 978 | else |
979 | *slots -= mei_data2slots(MEI_WD_STOP_MSG_SIZE); | 979 | slots -= mei_data2slots(MEI_WD_STOP_MSG_SIZE); |
980 | } | 980 | } |
981 | } | 981 | } |
982 | 982 | ||
@@ -991,14 +991,16 @@ static int mei_irq_thread_write_handler(struct mei_cl_cb *cmpl_list, | |||
991 | switch (pos->fop_type) { | 991 | switch (pos->fop_type) { |
992 | case MEI_FOP_CLOSE: | 992 | case MEI_FOP_CLOSE: |
993 | /* send disconnect message */ | 993 | /* send disconnect message */ |
994 | ret = _mei_irq_thread_close(dev, slots, pos, cl, cmpl_list); | 994 | ret = _mei_irq_thread_close(dev, &slots, pos, |
995 | cl, cmpl_list); | ||
995 | if (ret) | 996 | if (ret) |
996 | return ret; | 997 | return ret; |
997 | 998 | ||
998 | break; | 999 | break; |
999 | case MEI_FOP_READ: | 1000 | case MEI_FOP_READ: |
1000 | /* send flow control message */ | 1001 | /* send flow control message */ |
1001 | ret = _mei_irq_thread_read(dev, slots, pos, cl, cmpl_list); | 1002 | ret = _mei_irq_thread_read(dev, &slots, pos, |
1003 | cl, cmpl_list); | ||
1002 | if (ret) | 1004 | if (ret) |
1003 | return ret; | 1005 | return ret; |
1004 | 1006 | ||
@@ -1007,7 +1009,8 @@ static int mei_irq_thread_write_handler(struct mei_cl_cb *cmpl_list, | |||
1007 | /* connect message */ | 1009 | /* connect message */ |
1008 | if (mei_other_client_is_connecting(dev, cl)) | 1010 | if (mei_other_client_is_connecting(dev, cl)) |
1009 | continue; | 1011 | continue; |
1010 | ret = _mei_irq_thread_ioctl(dev, slots, pos, cl, cmpl_list); | 1012 | ret = _mei_irq_thread_ioctl(dev, &slots, pos, |
1013 | cl, cmpl_list); | ||
1011 | if (ret) | 1014 | if (ret) |
1012 | return ret; | 1015 | return ret; |
1013 | 1016 | ||
@@ -1032,7 +1035,7 @@ static int mei_irq_thread_write_handler(struct mei_cl_cb *cmpl_list, | |||
1032 | cl->host_client_id); | 1035 | cl->host_client_id); |
1033 | continue; | 1036 | continue; |
1034 | } | 1037 | } |
1035 | ret = mei_irq_thread_write_complete(dev, slots, pos, | 1038 | ret = mei_irq_thread_write_complete(dev, &slots, pos, |
1036 | cmpl_list); | 1039 | cmpl_list); |
1037 | if (ret) | 1040 | if (ret) |
1038 | return ret; | 1041 | return ret; |
@@ -1046,7 +1049,7 @@ static int mei_irq_thread_write_handler(struct mei_cl_cb *cmpl_list, | |||
1046 | cl->host_client_id); | 1049 | cl->host_client_id); |
1047 | continue; | 1050 | continue; |
1048 | } | 1051 | } |
1049 | ret = mei_amthif_irq_write_complete(dev, slots, | 1052 | ret = mei_amthif_irq_write_complete(dev, &slots, |
1050 | pos, cmpl_list); | 1053 | pos, cmpl_list); |
1051 | if (ret) | 1054 | if (ret) |
1052 | return ret; | 1055 | return ret; |
@@ -1238,7 +1241,7 @@ irqreturn_t mei_interrupt_thread_handler(int irq, void *dev_id) | |||
1238 | if (rets) | 1241 | if (rets) |
1239 | goto end; | 1242 | goto end; |
1240 | } | 1243 | } |
1241 | rets = mei_irq_thread_write_handler(&complete_list, dev, &slots); | 1244 | rets = mei_irq_thread_write_handler(dev, &complete_list); |
1242 | end: | 1245 | end: |
1243 | dev_dbg(&dev->pdev->dev, "end of bottom half function.\n"); | 1246 | dev_dbg(&dev->pdev->dev, "end of bottom half function.\n"); |
1244 | dev->host_hw_state = mei_hcsr_read(dev); | 1247 | dev->host_hw_state = mei_hcsr_read(dev); |