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authorMika Westerberg <ext-mika.1.westerberg@nokia.com>2009-12-14 08:59:18 -0500
committerTony Lindgren <tony@atomide.com>2009-12-16 15:44:04 -0500
commitf2eeeae06a41d4f9c90f8382cc0ef1d35888d09a (patch)
treec89910ae313d01d5edb859ecaec6dffed4a2f404 /drivers/misc/ibmasm/event.c
parentebeb53e1e1f11a51d8a93843a437f516e3528bfa (diff)
OMAP3: serial - fix bug introduced in
Commit f62349ee9788b1d94c55eb6c291d74a1f69bdd9e had side effect that causes kernel to oops when we are suspending to ram: # echo mem > /sys/power/state WARNING: at kernel/irq/manage.c:858 __free_irq+0x90/0x174() Trying to free already-free IRQ 72 Modules linked in: Backtrace: [<c00328d0>] (dump_backtrace+0x0/0x110) from [<c0347298>] (dump_stack+0x18/0x1c) r7:dfd4be08 r6:c009505c r5:c03fbfd1 r4:0000035a [<c0347280>] (dump_stack+0x0/0x1c) from [<c005a408>] (warn_slowpath_common+0x50/0x68) [<c005a3b8>] (warn_slowpath_common+0x0/0x68) from [<c005a46c>] (warn_slowpath_fmt+0x30) r7:c0474afc r6:00000048 r5:00000000 r4:c0474ac0 [<c005a43c>] (warn_slowpath_fmt+0x0/0x38) from [<c009505c>] (__free_irq+0x90/0x174) r3:00000048 r2:c03fc0ef [<c0094fcc>] (__free_irq+0x0/0x174) from [<c0095184>] (free_irq+0x44/0x64) [<c0095140>] (free_irq+0x0/0x64) from [<c0038100>] (omap_uart_enable_irqs+0x4c/0x90) r7:c034d58c r6:00000003 r5:00000000 r4:c0463028 [<c00380b4>] (omap_uart_enable_irqs+0x0/0x90) from [<c003d8f8>] (omap3_pm_begin+0x1c/0) r5:00000003 r4:00000000 [<c003d8dc>] (omap3_pm_begin+0x0/0x28) from [<c008d008>] (suspend_devices_and_enter+0x) [<c008cfd8>] (suspend_devices_and_enter+0x0/0x1dc) from [<c008d29c>] (enter_state+0xe8) r5:c03f7f46 r4:00000000 [<c008d1b4>] (enter_state+0x0/0x140) from [<c008c8e0>] (state_store+0x9c/0xc4) r7:c034d58c r6:00000003 r5:00000003 r4:c03f7f46 [<c008c844>] (state_store+0x0/0xc4) from [<c01cb2dc>] (kobj_attr_store+0x20/0x24) [<c01cb2bc>] (kobj_attr_store+0x0/0x24) from [<c0119420>] (sysfs_write_file+0x114/0x14) [<c011930c>] (sysfs_write_file+0x0/0x148) from [<c00cb298>] (vfs_write+0xb8/0x164) [<c00cb1e0>] (vfs_write+0x0/0x164) from [<c00cb408>] (sys_write+0x44/0x70) r8:4001f000 r7:00000004 r6:df81bd00 r5:00000000 r4:00000000 [<c00cb3c4>] (sys_write+0x0/0x70) from [<c002f040>] (ret_fast_syscall+0x0/0x38) r8:c002f204 r7:00000004 r6:401fa5e8 r5:4001f000 r4:00000004 This is due the fact that uart_list list was populated in omap_serial_early_init() and omap_uart_enable_irqs() went through this list even when serial idle wasn't enabled for all uarts. This patch moves the code that populates the uart_list and enables uart clocks into omap_serial_init_port(). Signed-off-by: Mika Westerberg <ext-mika.1.westerberg@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'drivers/misc/ibmasm/event.c')
0 files changed, 0 insertions, 0 deletions
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-20 11:37:55 -0400
EQ_B + 4) #define SEEQ_REA (SEEQ_B + 6) /* Receive End Area Register */ #define SEEQ_RPR (SEEQ_B + 10) /* Receive Pointer Register */ #define SEEQ_TPR (SEEQ_B + 12) /* Transmit Pointer Register */ #define SEEQ_DMAAR (SEEQ_B + 14) /* DMA Address Register */ #define SEEQ_BUFFER (SEEQ_B + 8) /* Buffer Window Register */ #define DEFAULT_TEA (0x3f) #define SEEQCMD_DMA_INT_EN (0x0001) /* DMA Interrupt Enable */ #define SEEQCMD_RX_INT_EN (0x0002) /* Receive Interrupt Enable */ #define SEEQCMD_TX_INT_EN (0x0004) /* Transmit Interrupt Enable */ #define SEEQCMD_WINDOW_INT_EN (0x0008) /* What the hell is this for?? */ #define SEEQCMD_INT_MASK (0x000f) #define SEEQCMD_DMA_INT_ACK (0x0010) /* DMA ack */ #define SEEQCMD_RX_INT_ACK (0x0020) #define SEEQCMD_TX_INT_ACK (0x0040) #define SEEQCMD_WINDOW_INT_ACK (0x0080) #define SEEQCMD_ACK_ALL (0x00f0) #define SEEQCMD_SET_DMA_ON (0x0100) /* Enables DMA Request logic */ #define SEEQCMD_SET_RX_ON (0x0200) /* Enables Packet RX */ #define SEEQCMD_SET_TX_ON (0x0400) /* Starts TX run */ #define SEEQCMD_SET_DMA_OFF (0x0800) #define SEEQCMD_SET_RX_OFF (0x1000) #define SEEQCMD_SET_TX_OFF (0x2000) #define SEEQCMD_SET_ALL_OFF (0x3800) /* set all logic off */ #define SEEQCMD_FIFO_READ (0x4000) /* Set FIFO to read mode (read from Buffer) */ #define SEEQCMD_FIFO_WRITE (0x8000) /* Set FIFO to write mode */ #define SEEQSTAT_DMA_INT_EN (0x0001) /* Status of interrupt enable */ #define SEEQSTAT_RX_INT_EN (0x0002) #define SEEQSTAT_TX_INT_EN (0x0004) #define SEEQSTAT_WINDOW_INT_EN (0x0008) #define SEEQSTAT_DMA_INT (0x0010) /* Interrupt flagged */ #define SEEQSTAT_RX_INT (0x0020) #define SEEQSTAT_TX_INT (0x0040) #define SEEQSTAT_WINDOW_INT (0x0080) #define SEEQSTAT_ANY_INT (0x00f0) #define SEEQSTAT_DMA_ON (0x0100) /* DMA logic on */ #define SEEQSTAT_RX_ON (0x0200) /* Packet RX on */ #define SEEQSTAT_TX_ON (0x0400) /* TX running */ #define SEEQSTAT_FIFO_FULL (0x2000) #define SEEQSTAT_FIFO_EMPTY (0x4000) #define SEEQSTAT_FIFO_DIR (0x8000) /* 1=read, 0=write */ #define SEEQCFG1_BUFFER_MASK (0x000f) /* define what maps into the BUFFER register */ #define SEEQCFG1_BUFFER_MAC0 (0x0000) /* MAC station addresses 0-5 */ #define SEEQCFG1_BUFFER_MAC1 (0x0001) #define SEEQCFG1_BUFFER_MAC2 (0x0002) #define SEEQCFG1_BUFFER_MAC3 (0x0003) #define SEEQCFG1_BUFFER_MAC4 (0x0004) #define SEEQCFG1_BUFFER_MAC5 (0x0005) #define SEEQCFG1_BUFFER_PROM (0x0006) /* The Address/CFG PROM */ #define SEEQCFG1_BUFFER_TEA (0x0007) /* Transmit end area */ #define SEEQCFG1_BUFFER_BUFFER (0x0008) /* Packet buffer memory */ #define SEEQCFG1_BUFFER_INT_VEC (0x0009) /* Interrupt Vector */ #define SEEQCFG1_DMA_INTVL_MASK (0x0030) #define SEEQCFG1_DMA_CONT (0x0000) #define SEEQCFG1_DMA_800ns (0x0010) #define SEEQCFG1_DMA_1600ns (0x0020) #define SEEQCFG1_DMA_3200ns (0x0030) #define SEEQCFG1_DMA_LEN_MASK (0x00c0) #define SEEQCFG1_DMA_LEN1 (0x0000) #define SEEQCFG1_DMA_LEN2 (0x0040) #define SEEQCFG1_DMA_LEN4 (0x0080) #define SEEQCFG1_DMA_LEN8 (0x00c0) #define SEEQCFG1_MAC_MASK (0x3f00) /* Dis/enable bits for MAC addresses */ #define SEEQCFG1_MAC0_EN (0x0100) #define SEEQCFG1_MAC1_EN (0x0200) #define SEEQCFG1_MAC2_EN (0x0400) #define SEEQCFG1_MAC3_EN (0x0800) #define SEEQCFG1_MAC4_EN (0x1000) #define SEEQCFG1_MAC5_EN (0x2000) #define SEEQCFG1_MATCH_MASK (0xc000) /* Packet matching logic cfg bits */ #define SEEQCFG1_MATCH_SPECIFIC (0x0000) /* only matching MAC addresses */ #define SEEQCFG1_MATCH_BROAD (0x4000) /* matching and broadcast addresses */ #define SEEQCFG1_MATCH_MULTI (0x8000) /* matching, broadcast and multicast */ #define SEEQCFG1_MATCH_ALL (0xc000) /* Promiscuous mode */ #define SEEQCFG1_DEFAULT (SEEQCFG1_BUFFER_BUFFER | SEEQCFG1_MAC0_EN | SEEQCFG1_MATCH_BROAD) #define SEEQCFG2_BYTE_SWAP (0x0001) /* 0=Intel byte-order */ #define SEEQCFG2_AUTO_REA (0x0002) /* if set, Receive End Area will be updated when reading from Buffer */ #define SEEQCFG2_CRC_ERR_EN (0x0008) /* enables receiving of packets with CRC errors */ #define SEEQCFG2_DRIBBLE_EN (0x0010) /* enables receiving of non-aligned packets */ #define SEEQCFG2_SHORT_EN (0x0020) /* enables receiving of short packets */ #define SEEQCFG2_SLOTSEL (0x0040) /* 0= standard IEEE802.3, 1= smaller,faster, non-standard */ #define SEEQCFG2_NO_PREAM (0x0080) /* 1= user supplies Xmit preamble bytes */ #define SEEQCFG2_ADDR_LEN (0x0100) /* 1= 2byte addresses */ #define SEEQCFG2_REC_CRC (0x0200) /* 0= received packets will have CRC stripped from them */ #define SEEQCFG2_XMIT_NO_CRC (0x0400) /* don't xmit CRC with each packet (user supplies it) */ #define SEEQCFG2_LOOPBACK (0x0800) #define SEEQCFG2_CTRLO (0x1000) #define SEEQCFG2_RESET (0x8000) /* software Hard-reset bit */ struct seeq_pkt_hdr { unsigned short next; /* address of next packet header */ unsigned char babble_int:1, /* enable int on >1514 byte packet */ coll_int:1, /* enable int on collision */ coll_16_int:1, /* enable int on >15 collision */ xmit_int:1, /* enable int on success (or xmit with <15 collision) */ unused:1, data_follows:1, /* if not set, process this as a header and pointer only */ chain_cont:1, /* if set, more headers in chain only cmd bit valid in recv header */ xmit_recv:1; /* if set, a xmit packet, else a receive packet.*/ unsigned char status; }; #define SEEQPKTH_BAB_INT_EN (0x01) /* xmit only */ #define SEEQPKTH_COL_INT_EN (0x02) /* xmit only */ #define SEEQPKTH_COL16_INT_EN (0x04) /* xmit only */ #define SEEQPKTH_XMIT_INT_EN (0x08) /* xmit only */ #define SEEQPKTH_DATA_FOLLOWS (0x20) /* supposedly in xmit only */ #define SEEQPKTH_CHAIN (0x40) /* more headers follow */ #define SEEQPKTH_XMIT (0x80) #define SEEQPKTS_BABBLE (0x0100) /* xmit only */ #define SEEQPKTS_OVERSIZE (0x0100) /* recv only */ #define SEEQPKTS_COLLISION (0x0200) /* xmit only */ #define SEEQPKTS_CRC_ERR (0x0200) /* recv only */ #define SEEQPKTS_COLL16 (0x0400) /* xmit only */ #define SEEQPKTS_DRIB (0x0400) /* recv only */ #define SEEQPKTS_SHORT (0x0800) /* recv only */ #define SEEQPKTS_DONE (0x8000) #define SEEQPKTS_ANY_ERROR (0x0f00)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-20 11:37:55 -0400