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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-09-28 10:37:20 -0400
committerSamuel Ortiz <sameo@linux.intel.com>2010-10-28 18:29:57 -0400
commit8e00593557c3c5a7bc6f636412a1cadcf4624232 (patch)
tree5d2872ae1cc0f39ebc0e29114864d12acdee292d /drivers/mfd
parentb4e017e332b873133602f47ae8cacfae64ab82c5 (diff)
mfd: Add mc13892 support to mc13xxx
mc13892 is the companion PMIC for Freescale's i.MX51. It's similar enough to mc13782 to support it in a single driver. This patch introduces enough compatibility cruft to keep all users of the superseded mc13783 driver unchanged. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd')
-rw-r--r--drivers/mfd/Kconfig9
-rw-r--r--drivers/mfd/Makefile2
-rw-r--r--drivers/mfd/mc13783-core.c743
-rw-r--r--drivers/mfd/mc13xxx-core.c840
4 files changed, 848 insertions, 746 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 9735f581574d..6c6b9f02d177 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -409,11 +409,16 @@ config MFD_PCF50633
409 so that function-specific drivers can bind to them. 409 so that function-specific drivers can bind to them.
410 410
411config MFD_MC13783 411config MFD_MC13783
412 tristate "Support Freescale MC13783" 412 tristate
413
414config MFD_MC13XXX
415 tristate "Support Freescale MC13783 and MC13892"
413 depends on SPI_MASTER 416 depends on SPI_MASTER
414 select MFD_CORE 417 select MFD_CORE
418 select MFD_MC13783
415 help 419 help
416 Support for the Freescale (Atlas) MC13783 PMIC and audio CODEC. 420 Support for the Freescale (Atlas) PMIC and audio CODECs
421 MC13783 and MC13892.
417 This driver provides common support for accessing the device, 422 This driver provides common support for accessing the device,
418 additional drivers must be enabled in order to use the 423 additional drivers must be enabled in order to use the
419 functionality of the device. 424 functionality of the device.
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index d18a6ab2ab58..70b26999dc81 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -39,7 +39,7 @@ obj-$(CONFIG_TWL4030_POWER) += twl4030-power.o
39obj-$(CONFIG_TWL4030_CODEC) += twl4030-codec.o 39obj-$(CONFIG_TWL4030_CODEC) += twl4030-codec.o
40obj-$(CONFIG_TWL6030_PWM) += twl6030-pwm.o 40obj-$(CONFIG_TWL6030_PWM) += twl6030-pwm.o
41 41
42obj-$(CONFIG_MFD_MC13783) += mc13783-core.o 42obj-$(CONFIG_MFD_MC13XXX) += mc13xxx-core.o
43 43
44obj-$(CONFIG_MFD_CORE) += mfd-core.o 44obj-$(CONFIG_MFD_CORE) += mfd-core.o
45 45
diff --git a/drivers/mfd/mc13783-core.c b/drivers/mfd/mc13783-core.c
deleted file mode 100644
index 2506e6888507..000000000000
--- a/drivers/mfd/mc13783-core.c
+++ /dev/null
@@ -1,743 +0,0 @@
1/*
2 * Copyright 2009 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * loosely based on an earlier driver that has
6 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation.
11 */
12#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/mutex.h>
16#include <linux/interrupt.h>
17#include <linux/spi/spi.h>
18#include <linux/mfd/core.h>
19#include <linux/mfd/mc13783.h>
20
21struct mc13783 {
22 struct spi_device *spidev;
23 struct mutex lock;
24 int irq;
25 int adcflags;
26
27 irq_handler_t irqhandler[MC13783_NUM_IRQ];
28 void *irqdata[MC13783_NUM_IRQ];
29};
30
31#define MC13783_REG_REVISION 7
32#define MC13783_REG_ADC_0 43
33#define MC13783_REG_ADC_1 44
34#define MC13783_REG_ADC_2 45
35
36#define MC13783_IRQSTAT0 0
37#define MC13783_IRQSTAT0_ADCDONEI (1 << 0)
38#define MC13783_IRQSTAT0_ADCBISDONEI (1 << 1)
39#define MC13783_IRQSTAT0_TSI (1 << 2)
40#define MC13783_IRQSTAT0_WHIGHI (1 << 3)
41#define MC13783_IRQSTAT0_WLOWI (1 << 4)
42#define MC13783_IRQSTAT0_CHGDETI (1 << 6)
43#define MC13783_IRQSTAT0_CHGOVI (1 << 7)
44#define MC13783_IRQSTAT0_CHGREVI (1 << 8)
45#define MC13783_IRQSTAT0_CHGSHORTI (1 << 9)
46#define MC13783_IRQSTAT0_CCCVI (1 << 10)
47#define MC13783_IRQSTAT0_CHGCURRI (1 << 11)
48#define MC13783_IRQSTAT0_BPONI (1 << 12)
49#define MC13783_IRQSTAT0_LOBATLI (1 << 13)
50#define MC13783_IRQSTAT0_LOBATHI (1 << 14)
51#define MC13783_IRQSTAT0_UDPI (1 << 15)
52#define MC13783_IRQSTAT0_USBI (1 << 16)
53#define MC13783_IRQSTAT0_IDI (1 << 19)
54#define MC13783_IRQSTAT0_SE1I (1 << 21)
55#define MC13783_IRQSTAT0_CKDETI (1 << 22)
56#define MC13783_IRQSTAT0_UDMI (1 << 23)
57
58#define MC13783_IRQMASK0 1
59#define MC13783_IRQMASK0_ADCDONEM MC13783_IRQSTAT0_ADCDONEI
60#define MC13783_IRQMASK0_ADCBISDONEM MC13783_IRQSTAT0_ADCBISDONEI
61#define MC13783_IRQMASK0_TSM MC13783_IRQSTAT0_TSI
62#define MC13783_IRQMASK0_WHIGHM MC13783_IRQSTAT0_WHIGHI
63#define MC13783_IRQMASK0_WLOWM MC13783_IRQSTAT0_WLOWI
64#define MC13783_IRQMASK0_CHGDETM MC13783_IRQSTAT0_CHGDETI
65#define MC13783_IRQMASK0_CHGOVM MC13783_IRQSTAT0_CHGOVI
66#define MC13783_IRQMASK0_CHGREVM MC13783_IRQSTAT0_CHGREVI
67#define MC13783_IRQMASK0_CHGSHORTM MC13783_IRQSTAT0_CHGSHORTI
68#define MC13783_IRQMASK0_CCCVM MC13783_IRQSTAT0_CCCVI
69#define MC13783_IRQMASK0_CHGCURRM MC13783_IRQSTAT0_CHGCURRI
70#define MC13783_IRQMASK0_BPONM MC13783_IRQSTAT0_BPONI
71#define MC13783_IRQMASK0_LOBATLM MC13783_IRQSTAT0_LOBATLI
72#define MC13783_IRQMASK0_LOBATHM MC13783_IRQSTAT0_LOBATHI
73#define MC13783_IRQMASK0_UDPM MC13783_IRQSTAT0_UDPI
74#define MC13783_IRQMASK0_USBM MC13783_IRQSTAT0_USBI
75#define MC13783_IRQMASK0_IDM MC13783_IRQSTAT0_IDI
76#define MC13783_IRQMASK0_SE1M MC13783_IRQSTAT0_SE1I
77#define MC13783_IRQMASK0_CKDETM MC13783_IRQSTAT0_CKDETI
78#define MC13783_IRQMASK0_UDMM MC13783_IRQSTAT0_UDMI
79
80#define MC13783_IRQSTAT1 3
81#define MC13783_IRQSTAT1_1HZI (1 << 0)
82#define MC13783_IRQSTAT1_TODAI (1 << 1)
83#define MC13783_IRQSTAT1_ONOFD1I (1 << 3)
84#define MC13783_IRQSTAT1_ONOFD2I (1 << 4)
85#define MC13783_IRQSTAT1_ONOFD3I (1 << 5)
86#define MC13783_IRQSTAT1_SYSRSTI (1 << 6)
87#define MC13783_IRQSTAT1_RTCRSTI (1 << 7)
88#define MC13783_IRQSTAT1_PCI (1 << 8)
89#define MC13783_IRQSTAT1_WARMI (1 << 9)
90#define MC13783_IRQSTAT1_MEMHLDI (1 << 10)
91#define MC13783_IRQSTAT1_PWRRDYI (1 << 11)
92#define MC13783_IRQSTAT1_THWARNLI (1 << 12)
93#define MC13783_IRQSTAT1_THWARNHI (1 << 13)
94#define MC13783_IRQSTAT1_CLKI (1 << 14)
95#define MC13783_IRQSTAT1_SEMAFI (1 << 15)
96#define MC13783_IRQSTAT1_MC2BI (1 << 17)
97#define MC13783_IRQSTAT1_HSDETI (1 << 18)
98#define MC13783_IRQSTAT1_HSLI (1 << 19)
99#define MC13783_IRQSTAT1_ALSPTHI (1 << 20)
100#define MC13783_IRQSTAT1_AHSSHORTI (1 << 21)
101
102#define MC13783_IRQMASK1 4
103#define MC13783_IRQMASK1_1HZM MC13783_IRQSTAT1_1HZI
104#define MC13783_IRQMASK1_TODAM MC13783_IRQSTAT1_TODAI
105#define MC13783_IRQMASK1_ONOFD1M MC13783_IRQSTAT1_ONOFD1I
106#define MC13783_IRQMASK1_ONOFD2M MC13783_IRQSTAT1_ONOFD2I
107#define MC13783_IRQMASK1_ONOFD3M MC13783_IRQSTAT1_ONOFD3I
108#define MC13783_IRQMASK1_SYSRSTM MC13783_IRQSTAT1_SYSRSTI
109#define MC13783_IRQMASK1_RTCRSTM MC13783_IRQSTAT1_RTCRSTI
110#define MC13783_IRQMASK1_PCM MC13783_IRQSTAT1_PCI
111#define MC13783_IRQMASK1_WARMM MC13783_IRQSTAT1_WARMI
112#define MC13783_IRQMASK1_MEMHLDM MC13783_IRQSTAT1_MEMHLDI
113#define MC13783_IRQMASK1_PWRRDYM MC13783_IRQSTAT1_PWRRDYI
114#define MC13783_IRQMASK1_THWARNLM MC13783_IRQSTAT1_THWARNLI
115#define MC13783_IRQMASK1_THWARNHM MC13783_IRQSTAT1_THWARNHI
116#define MC13783_IRQMASK1_CLKM MC13783_IRQSTAT1_CLKI
117#define MC13783_IRQMASK1_SEMAFM MC13783_IRQSTAT1_SEMAFI
118#define MC13783_IRQMASK1_MC2BM MC13783_IRQSTAT1_MC2BI
119#define MC13783_IRQMASK1_HSDETM MC13783_IRQSTAT1_HSDETI
120#define MC13783_IRQMASK1_HSLM MC13783_IRQSTAT1_HSLI
121#define MC13783_IRQMASK1_ALSPTHM MC13783_IRQSTAT1_ALSPTHI
122#define MC13783_IRQMASK1_AHSSHORTM MC13783_IRQSTAT1_AHSSHORTI
123
124#define MC13783_ADC1 44
125#define MC13783_ADC1_ADEN (1 << 0)
126#define MC13783_ADC1_RAND (1 << 1)
127#define MC13783_ADC1_ADSEL (1 << 3)
128#define MC13783_ADC1_ASC (1 << 20)
129#define MC13783_ADC1_ADTRIGIGN (1 << 21)
130
131#define MC13783_NUMREGS 0x3f
132
133void mc13783_lock(struct mc13783 *mc13783)
134{
135 if (!mutex_trylock(&mc13783->lock)) {
136 dev_dbg(&mc13783->spidev->dev, "wait for %s from %pf\n",
137 __func__, __builtin_return_address(0));
138
139 mutex_lock(&mc13783->lock);
140 }
141 dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
142 __func__, __builtin_return_address(0));
143}
144EXPORT_SYMBOL(mc13783_lock);
145
146void mc13783_unlock(struct mc13783 *mc13783)
147{
148 dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
149 __func__, __builtin_return_address(0));
150 mutex_unlock(&mc13783->lock);
151}
152EXPORT_SYMBOL(mc13783_unlock);
153
154#define MC13783_REGOFFSET_SHIFT 25
155int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val)
156{
157 struct spi_transfer t;
158 struct spi_message m;
159 int ret;
160
161 BUG_ON(!mutex_is_locked(&mc13783->lock));
162
163 if (offset > MC13783_NUMREGS)
164 return -EINVAL;
165
166 *val = offset << MC13783_REGOFFSET_SHIFT;
167
168 memset(&t, 0, sizeof(t));
169
170 t.tx_buf = val;
171 t.rx_buf = val;
172 t.len = sizeof(u32);
173
174 spi_message_init(&m);
175 spi_message_add_tail(&t, &m);
176
177 ret = spi_sync(mc13783->spidev, &m);
178
179 /* error in message.status implies error return from spi_sync */
180 BUG_ON(!ret && m.status);
181
182 if (ret)
183 return ret;
184
185 *val &= 0xffffff;
186
187 dev_vdbg(&mc13783->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
188
189 return 0;
190}
191EXPORT_SYMBOL(mc13783_reg_read);
192
193int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val)
194{
195 u32 buf;
196 struct spi_transfer t;
197 struct spi_message m;
198 int ret;
199
200 BUG_ON(!mutex_is_locked(&mc13783->lock));
201
202 dev_vdbg(&mc13783->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
203
204 if (offset > MC13783_NUMREGS || val > 0xffffff)
205 return -EINVAL;
206
207 buf = 1 << 31 | offset << MC13783_REGOFFSET_SHIFT | val;
208
209 memset(&t, 0, sizeof(t));
210
211 t.tx_buf = &buf;
212 t.rx_buf = &buf;
213 t.len = sizeof(u32);
214
215 spi_message_init(&m);
216 spi_message_add_tail(&t, &m);
217
218 ret = spi_sync(mc13783->spidev, &m);
219
220 BUG_ON(!ret && m.status);
221
222 if (ret)
223 return ret;
224
225 return 0;
226}
227EXPORT_SYMBOL(mc13783_reg_write);
228
229int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
230 u32 mask, u32 val)
231{
232 int ret;
233 u32 valread;
234
235 BUG_ON(val & ~mask);
236
237 ret = mc13783_reg_read(mc13783, offset, &valread);
238 if (ret)
239 return ret;
240
241 valread = (valread & ~mask) | val;
242
243 return mc13783_reg_write(mc13783, offset, valread);
244}
245EXPORT_SYMBOL(mc13783_reg_rmw);
246
247int mc13783_get_flags(struct mc13783 *mc13783)
248{
249 struct mc13783_platform_data *pdata =
250 dev_get_platdata(&mc13783->spidev->dev);
251
252 return pdata->flags;
253}
254EXPORT_SYMBOL(mc13783_get_flags);
255
256int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
257{
258 int ret;
259 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
260 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
261 u32 mask;
262
263 if (irq < 0 || irq >= MC13783_NUM_IRQ)
264 return -EINVAL;
265
266 ret = mc13783_reg_read(mc13783, offmask, &mask);
267 if (ret)
268 return ret;
269
270 if (mask & irqbit)
271 /* already masked */
272 return 0;
273
274 return mc13783_reg_write(mc13783, offmask, mask | irqbit);
275}
276EXPORT_SYMBOL(mc13783_irq_mask);
277
278int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
279{
280 int ret;
281 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
282 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
283 u32 mask;
284
285 if (irq < 0 || irq >= MC13783_NUM_IRQ)
286 return -EINVAL;
287
288 ret = mc13783_reg_read(mc13783, offmask, &mask);
289 if (ret)
290 return ret;
291
292 if (!(mask & irqbit))
293 /* already unmasked */
294 return 0;
295
296 return mc13783_reg_write(mc13783, offmask, mask & ~irqbit);
297}
298EXPORT_SYMBOL(mc13783_irq_unmask);
299
300int mc13783_irq_status(struct mc13783 *mc13783, int irq,
301 int *enabled, int *pending)
302{
303 int ret;
304 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
305 unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
306 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
307
308 if (irq < 0 || irq >= MC13783_NUM_IRQ)
309 return -EINVAL;
310
311 if (enabled) {
312 u32 mask;
313
314 ret = mc13783_reg_read(mc13783, offmask, &mask);
315 if (ret)
316 return ret;
317
318 *enabled = mask & irqbit;
319 }
320
321 if (pending) {
322 u32 stat;
323
324 ret = mc13783_reg_read(mc13783, offstat, &stat);
325 if (ret)
326 return ret;
327
328 *pending = stat & irqbit;
329 }
330
331 return 0;
332}
333EXPORT_SYMBOL(mc13783_irq_status);
334
335int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
336{
337 unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
338 unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
339
340 BUG_ON(irq < 0 || irq >= MC13783_NUM_IRQ);
341
342 return mc13783_reg_write(mc13783, offstat, val);
343}
344EXPORT_SYMBOL(mc13783_irq_ack);
345
346int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
347 irq_handler_t handler, const char *name, void *dev)
348{
349 BUG_ON(!mutex_is_locked(&mc13783->lock));
350 BUG_ON(!handler);
351
352 if (irq < 0 || irq >= MC13783_NUM_IRQ)
353 return -EINVAL;
354
355 if (mc13783->irqhandler[irq])
356 return -EBUSY;
357
358 mc13783->irqhandler[irq] = handler;
359 mc13783->irqdata[irq] = dev;
360
361 return 0;
362}
363EXPORT_SYMBOL(mc13783_irq_request_nounmask);
364
365int mc13783_irq_request(struct mc13783 *mc13783, int irq,
366 irq_handler_t handler, const char *name, void *dev)
367{
368 int ret;
369
370 ret = mc13783_irq_request_nounmask(mc13783, irq, handler, name, dev);
371 if (ret)
372 return ret;
373
374 ret = mc13783_irq_unmask(mc13783, irq);
375 if (ret) {
376 mc13783->irqhandler[irq] = NULL;
377 mc13783->irqdata[irq] = NULL;
378 return ret;
379 }
380
381 return 0;
382}
383EXPORT_SYMBOL(mc13783_irq_request);
384
385int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
386{
387 int ret;
388 BUG_ON(!mutex_is_locked(&mc13783->lock));
389
390 if (irq < 0 || irq >= MC13783_NUM_IRQ || !mc13783->irqhandler[irq] ||
391 mc13783->irqdata[irq] != dev)
392 return -EINVAL;
393
394 ret = mc13783_irq_mask(mc13783, irq);
395 if (ret)
396 return ret;
397
398 mc13783->irqhandler[irq] = NULL;
399 mc13783->irqdata[irq] = NULL;
400
401 return 0;
402}
403EXPORT_SYMBOL(mc13783_irq_free);
404
405static inline irqreturn_t mc13783_irqhandler(struct mc13783 *mc13783, int irq)
406{
407 return mc13783->irqhandler[irq](irq, mc13783->irqdata[irq]);
408}
409
410/*
411 * returns: number of handled irqs or negative error
412 * locking: holds mc13783->lock
413 */
414static int mc13783_irq_handle(struct mc13783 *mc13783,
415 unsigned int offstat, unsigned int offmask, int baseirq)
416{
417 u32 stat, mask;
418 int ret = mc13783_reg_read(mc13783, offstat, &stat);
419 int num_handled = 0;
420
421 if (ret)
422 return ret;
423
424 ret = mc13783_reg_read(mc13783, offmask, &mask);
425 if (ret)
426 return ret;
427
428 while (stat & ~mask) {
429 int irq = __ffs(stat & ~mask);
430
431 stat &= ~(1 << irq);
432
433 if (likely(mc13783->irqhandler[baseirq + irq])) {
434 irqreturn_t handled;
435
436 handled = mc13783_irqhandler(mc13783, baseirq + irq);
437 if (handled == IRQ_HANDLED)
438 num_handled++;
439 } else {
440 dev_err(&mc13783->spidev->dev,
441 "BUG: irq %u but no handler\n",
442 baseirq + irq);
443
444 mask |= 1 << irq;
445
446 ret = mc13783_reg_write(mc13783, offmask, mask);
447 }
448 }
449
450 return num_handled;
451}
452
453static irqreturn_t mc13783_irq_thread(int irq, void *data)
454{
455 struct mc13783 *mc13783 = data;
456 irqreturn_t ret;
457 int handled = 0;
458
459 mc13783_lock(mc13783);
460
461 ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT0,
462 MC13783_IRQMASK0, MC13783_IRQ_ADCDONE);
463 if (ret > 0)
464 handled = 1;
465
466 ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT1,
467 MC13783_IRQMASK1, MC13783_IRQ_1HZ);
468 if (ret > 0)
469 handled = 1;
470
471 mc13783_unlock(mc13783);
472
473 return IRQ_RETVAL(handled);
474}
475
476#define MC13783_ADC1_CHAN0_SHIFT 5
477#define MC13783_ADC1_CHAN1_SHIFT 8
478
479struct mc13783_adcdone_data {
480 struct mc13783 *mc13783;
481 struct completion done;
482};
483
484static irqreturn_t mc13783_handler_adcdone(int irq, void *data)
485{
486 struct mc13783_adcdone_data *adcdone_data = data;
487
488 mc13783_irq_ack(adcdone_data->mc13783, irq);
489
490 complete_all(&adcdone_data->done);
491
492 return IRQ_HANDLED;
493}
494
495#define MC13783_ADC_WORKING (1 << 0)
496
497int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
498 unsigned int channel, unsigned int *sample)
499{
500 u32 adc0, adc1, old_adc0;
501 int i, ret;
502 struct mc13783_adcdone_data adcdone_data = {
503 .mc13783 = mc13783,
504 };
505 init_completion(&adcdone_data.done);
506
507 dev_dbg(&mc13783->spidev->dev, "%s\n", __func__);
508
509 mc13783_lock(mc13783);
510
511 if (mc13783->adcflags & MC13783_ADC_WORKING) {
512 ret = -EBUSY;
513 goto out;
514 }
515
516 mc13783->adcflags |= MC13783_ADC_WORKING;
517
518 mc13783_reg_read(mc13783, MC13783_ADC0, &old_adc0);
519
520 adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
521 adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC;
522
523 if (channel > 7)
524 adc1 |= MC13783_ADC1_ADSEL;
525
526 switch (mode) {
527 case MC13783_ADC_MODE_TS:
528 adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 |
529 MC13783_ADC0_TSMOD1;
530 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
531 break;
532
533 case MC13783_ADC_MODE_SINGLE_CHAN:
534 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
535 adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
536 adc1 |= MC13783_ADC1_RAND;
537 break;
538
539 case MC13783_ADC_MODE_MULT_CHAN:
540 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
541 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
542 break;
543
544 default:
545 mc13783_unlock(mc13783);
546 return -EINVAL;
547 }
548
549 dev_dbg(&mc13783->spidev->dev, "%s: request irq\n", __func__);
550 mc13783_irq_request(mc13783, MC13783_IRQ_ADCDONE,
551 mc13783_handler_adcdone, __func__, &adcdone_data);
552 mc13783_irq_ack(mc13783, MC13783_IRQ_ADCDONE);
553
554 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, adc0);
555 mc13783_reg_write(mc13783, MC13783_REG_ADC_1, adc1);
556
557 mc13783_unlock(mc13783);
558
559 ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
560
561 if (!ret)
562 ret = -ETIMEDOUT;
563
564 mc13783_lock(mc13783);
565
566 mc13783_irq_free(mc13783, MC13783_IRQ_ADCDONE, &adcdone_data);
567
568 if (ret > 0)
569 for (i = 0; i < 4; ++i) {
570 ret = mc13783_reg_read(mc13783,
571 MC13783_REG_ADC_2, &sample[i]);
572 if (ret)
573 break;
574 }
575
576 if (mode == MC13783_ADC_MODE_TS)
577 /* restore TSMOD */
578 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, old_adc0);
579
580 mc13783->adcflags &= ~MC13783_ADC_WORKING;
581out:
582 mc13783_unlock(mc13783);
583
584 return ret;
585}
586EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
587
588static int mc13783_add_subdevice_pdata(struct mc13783 *mc13783,
589 const char *name, void *pdata, size_t pdata_size)
590{
591 struct mfd_cell cell = {
592 .name = name,
593 .platform_data = pdata,
594 .data_size = pdata_size,
595 };
596
597 return mfd_add_devices(&mc13783->spidev->dev, -1, &cell, 1, NULL, 0);
598}
599
600static int mc13783_add_subdevice(struct mc13783 *mc13783, const char *name)
601{
602 return mc13783_add_subdevice_pdata(mc13783, name, NULL, 0);
603}
604
605static int mc13783_check_revision(struct mc13783 *mc13783)
606{
607 u32 rev_id, rev1, rev2, finid, icid;
608
609 mc13783_reg_read(mc13783, MC13783_REG_REVISION, &rev_id);
610
611 rev1 = (rev_id & 0x018) >> 3;
612 rev2 = (rev_id & 0x007);
613 icid = (rev_id & 0x01C0) >> 6;
614 finid = (rev_id & 0x01E00) >> 9;
615
616 /* Ver 0.2 is actually 3.2a. Report as 3.2 */
617 if ((rev1 == 0) && (rev2 == 2))
618 rev1 = 3;
619
620 if (rev1 == 0 || icid != 2) {
621 dev_err(&mc13783->spidev->dev, "No MC13783 detected.\n");
622 return -ENODEV;
623 }
624
625 dev_info(&mc13783->spidev->dev,
626 "MC13783 Rev %d.%d FinVer %x detected\n",
627 rev1, rev2, finid);
628
629 return 0;
630}
631
632static int mc13783_probe(struct spi_device *spi)
633{
634 struct mc13783 *mc13783;
635 struct mc13783_platform_data *pdata = dev_get_platdata(&spi->dev);
636 int ret;
637
638 mc13783 = kzalloc(sizeof(*mc13783), GFP_KERNEL);
639 if (!mc13783)
640 return -ENOMEM;
641
642 dev_set_drvdata(&spi->dev, mc13783);
643 spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
644 spi->bits_per_word = 32;
645 spi_setup(spi);
646
647 mc13783->spidev = spi;
648
649 mutex_init(&mc13783->lock);
650 mc13783_lock(mc13783);
651
652 ret = mc13783_check_revision(mc13783);
653 if (ret)
654 goto err_revision;
655
656 /* mask all irqs */
657 ret = mc13783_reg_write(mc13783, MC13783_IRQMASK0, 0x00ffffff);
658 if (ret)
659 goto err_mask;
660
661 ret = mc13783_reg_write(mc13783, MC13783_IRQMASK1, 0x00ffffff);
662 if (ret)
663 goto err_mask;
664
665 ret = request_threaded_irq(spi->irq, NULL, mc13783_irq_thread,
666 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13783", mc13783);
667
668 if (ret) {
669err_mask:
670err_revision:
671 mutex_unlock(&mc13783->lock);
672 dev_set_drvdata(&spi->dev, NULL);
673 kfree(mc13783);
674 return ret;
675 }
676
677 mc13783_unlock(mc13783);
678
679 if (pdata->flags & MC13783_USE_ADC)
680 mc13783_add_subdevice(mc13783, "mc13783-adc");
681
682 if (pdata->flags & MC13783_USE_CODEC)
683 mc13783_add_subdevice(mc13783, "mc13783-codec");
684
685 if (pdata->flags & MC13783_USE_REGULATOR) {
686 struct mc13783_regulator_platform_data regulator_pdata = {
687 .num_regulators = pdata->num_regulators,
688 .regulators = pdata->regulators,
689 };
690
691 mc13783_add_subdevice_pdata(mc13783, "mc13783-regulator",
692 &regulator_pdata, sizeof(regulator_pdata));
693 }
694
695 if (pdata->flags & MC13783_USE_RTC)
696 mc13783_add_subdevice(mc13783, "mc13783-rtc");
697
698 if (pdata->flags & MC13783_USE_TOUCHSCREEN)
699 mc13783_add_subdevice(mc13783, "mc13783-ts");
700
701 if (pdata->flags & MC13783_USE_LED)
702 mc13783_add_subdevice_pdata(mc13783, "mc13783-led",
703 pdata->leds, sizeof(*pdata->leds));
704
705 return 0;
706}
707
708static int __devexit mc13783_remove(struct spi_device *spi)
709{
710 struct mc13783 *mc13783 = dev_get_drvdata(&spi->dev);
711
712 free_irq(mc13783->spidev->irq, mc13783);
713
714 mfd_remove_devices(&spi->dev);
715
716 return 0;
717}
718
719static struct spi_driver mc13783_driver = {
720 .driver = {
721 .name = "mc13783",
722 .bus = &spi_bus_type,
723 .owner = THIS_MODULE,
724 },
725 .probe = mc13783_probe,
726 .remove = __devexit_p(mc13783_remove),
727};
728
729static int __init mc13783_init(void)
730{
731 return spi_register_driver(&mc13783_driver);
732}
733subsys_initcall(mc13783_init);
734
735static void __exit mc13783_exit(void)
736{
737 spi_unregister_driver(&mc13783_driver);
738}
739module_exit(mc13783_exit);
740
741MODULE_DESCRIPTION("Core driver for Freescale MC13783 PMIC");
742MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
743MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
new file mode 100644
index 000000000000..93258adf8b63
--- /dev/null
+++ b/drivers/mfd/mc13xxx-core.c
@@ -0,0 +1,840 @@
1/*
2 * Copyright 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * loosely based on an earlier driver that has
6 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation.
11 */
12#define DEBUG
13#define VERBOSE_DEBUG
14
15#include <linux/slab.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/mutex.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
21#include <linux/mfd/core.h>
22#include <linux/mfd/mc13xxx.h>
23
24struct mc13xxx {
25 struct spi_device *spidev;
26 struct mutex lock;
27 int irq;
28
29 irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
30 void *irqdata[MC13XXX_NUM_IRQ];
31};
32
33struct mc13783 {
34 struct mc13xxx mc13xxx;
35
36 int adcflags;
37};
38
39struct mc13xxx *mc13783_to_mc13xxx(struct mc13783 *mc13783)
40{
41 return &mc13783->mc13xxx;
42}
43EXPORT_SYMBOL(mc13783_to_mc13xxx);
44
45#define MC13XXX_IRQSTAT0 0
46#define MC13XXX_IRQSTAT0_ADCDONEI (1 << 0)
47#define MC13XXX_IRQSTAT0_ADCBISDONEI (1 << 1)
48#define MC13XXX_IRQSTAT0_TSI (1 << 2)
49#define MC13783_IRQSTAT0_WHIGHI (1 << 3)
50#define MC13783_IRQSTAT0_WLOWI (1 << 4)
51#define MC13XXX_IRQSTAT0_CHGDETI (1 << 6)
52#define MC13783_IRQSTAT0_CHGOVI (1 << 7)
53#define MC13XXX_IRQSTAT0_CHGREVI (1 << 8)
54#define MC13XXX_IRQSTAT0_CHGSHORTI (1 << 9)
55#define MC13XXX_IRQSTAT0_CCCVI (1 << 10)
56#define MC13XXX_IRQSTAT0_CHGCURRI (1 << 11)
57#define MC13XXX_IRQSTAT0_BPONI (1 << 12)
58#define MC13XXX_IRQSTAT0_LOBATLI (1 << 13)
59#define MC13XXX_IRQSTAT0_LOBATHI (1 << 14)
60#define MC13783_IRQSTAT0_UDPI (1 << 15)
61#define MC13783_IRQSTAT0_USBI (1 << 16)
62#define MC13783_IRQSTAT0_IDI (1 << 19)
63#define MC13783_IRQSTAT0_SE1I (1 << 21)
64#define MC13783_IRQSTAT0_CKDETI (1 << 22)
65#define MC13783_IRQSTAT0_UDMI (1 << 23)
66
67#define MC13XXX_IRQMASK0 1
68#define MC13XXX_IRQMASK0_ADCDONEM MC13XXX_IRQSTAT0_ADCDONEI
69#define MC13XXX_IRQMASK0_ADCBISDONEM MC13XXX_IRQSTAT0_ADCBISDONEI
70#define MC13XXX_IRQMASK0_TSM MC13XXX_IRQSTAT0_TSI
71#define MC13783_IRQMASK0_WHIGHM MC13783_IRQSTAT0_WHIGHI
72#define MC13783_IRQMASK0_WLOWM MC13783_IRQSTAT0_WLOWI
73#define MC13XXX_IRQMASK0_CHGDETM MC13XXX_IRQSTAT0_CHGDETI
74#define MC13783_IRQMASK0_CHGOVM MC13783_IRQSTAT0_CHGOVI
75#define MC13XXX_IRQMASK0_CHGREVM MC13XXX_IRQSTAT0_CHGREVI
76#define MC13XXX_IRQMASK0_CHGSHORTM MC13XXX_IRQSTAT0_CHGSHORTI
77#define MC13XXX_IRQMASK0_CCCVM MC13XXX_IRQSTAT0_CCCVI
78#define MC13XXX_IRQMASK0_CHGCURRM MC13XXX_IRQSTAT0_CHGCURRI
79#define MC13XXX_IRQMASK0_BPONM MC13XXX_IRQSTAT0_BPONI
80#define MC13XXX_IRQMASK0_LOBATLM MC13XXX_IRQSTAT0_LOBATLI
81#define MC13XXX_IRQMASK0_LOBATHM MC13XXX_IRQSTAT0_LOBATHI
82#define MC13783_IRQMASK0_UDPM MC13783_IRQSTAT0_UDPI
83#define MC13783_IRQMASK0_USBM MC13783_IRQSTAT0_USBI
84#define MC13783_IRQMASK0_IDM MC13783_IRQSTAT0_IDI
85#define MC13783_IRQMASK0_SE1M MC13783_IRQSTAT0_SE1I
86#define MC13783_IRQMASK0_CKDETM MC13783_IRQSTAT0_CKDETI
87#define MC13783_IRQMASK0_UDMM MC13783_IRQSTAT0_UDMI
88
89#define MC13XXX_IRQSTAT1 3
90#define MC13XXX_IRQSTAT1_1HZI (1 << 0)
91#define MC13XXX_IRQSTAT1_TODAI (1 << 1)
92#define MC13783_IRQSTAT1_ONOFD1I (1 << 3)
93#define MC13783_IRQSTAT1_ONOFD2I (1 << 4)
94#define MC13783_IRQSTAT1_ONOFD3I (1 << 5)
95#define MC13XXX_IRQSTAT1_SYSRSTI (1 << 6)
96#define MC13XXX_IRQSTAT1_RTCRSTI (1 << 7)
97#define MC13XXX_IRQSTAT1_PCI (1 << 8)
98#define MC13XXX_IRQSTAT1_WARMI (1 << 9)
99#define MC13XXX_IRQSTAT1_MEMHLDI (1 << 10)
100#define MC13783_IRQSTAT1_PWRRDYI (1 << 11)
101#define MC13XXX_IRQSTAT1_THWARNLI (1 << 12)
102#define MC13XXX_IRQSTAT1_THWARNHI (1 << 13)
103#define MC13XXX_IRQSTAT1_CLKI (1 << 14)
104#define MC13783_IRQSTAT1_SEMAFI (1 << 15)
105#define MC13783_IRQSTAT1_MC2BI (1 << 17)
106#define MC13783_IRQSTAT1_HSDETI (1 << 18)
107#define MC13783_IRQSTAT1_HSLI (1 << 19)
108#define MC13783_IRQSTAT1_ALSPTHI (1 << 20)
109#define MC13783_IRQSTAT1_AHSSHORTI (1 << 21)
110
111#define MC13XXX_IRQMASK1 4
112#define MC13XXX_IRQMASK1_1HZM MC13XXX_IRQSTAT1_1HZI
113#define MC13XXX_IRQMASK1_TODAM MC13XXX_IRQSTAT1_TODAI
114#define MC13783_IRQMASK1_ONOFD1M MC13783_IRQSTAT1_ONOFD1I
115#define MC13783_IRQMASK1_ONOFD2M MC13783_IRQSTAT1_ONOFD2I
116#define MC13783_IRQMASK1_ONOFD3M MC13783_IRQSTAT1_ONOFD3I
117#define MC13XXX_IRQMASK1_SYSRSTM MC13XXX_IRQSTAT1_SYSRSTI
118#define MC13XXX_IRQMASK1_RTCRSTM MC13XXX_IRQSTAT1_RTCRSTI
119#define MC13XXX_IRQMASK1_PCM MC13XXX_IRQSTAT1_PCI
120#define MC13XXX_IRQMASK1_WARMM MC13XXX_IRQSTAT1_WARMI
121#define MC13XXX_IRQMASK1_MEMHLDM MC13XXX_IRQSTAT1_MEMHLDI
122#define MC13783_IRQMASK1_PWRRDYM MC13783_IRQSTAT1_PWRRDYI
123#define MC13XXX_IRQMASK1_THWARNLM MC13XXX_IRQSTAT1_THWARNLI
124#define MC13XXX_IRQMASK1_THWARNHM MC13XXX_IRQSTAT1_THWARNHI
125#define MC13XXX_IRQMASK1_CLKM MC13XXX_IRQSTAT1_CLKI
126#define MC13783_IRQMASK1_SEMAFM MC13783_IRQSTAT1_SEMAFI
127#define MC13783_IRQMASK1_MC2BM MC13783_IRQSTAT1_MC2BI
128#define MC13783_IRQMASK1_HSDETM MC13783_IRQSTAT1_HSDETI
129#define MC13783_IRQMASK1_HSLM MC13783_IRQSTAT1_HSLI
130#define MC13783_IRQMASK1_ALSPTHM MC13783_IRQSTAT1_ALSPTHI
131#define MC13783_IRQMASK1_AHSSHORTM MC13783_IRQSTAT1_AHSSHORTI
132
133#define MC13XXX_REVISION 7
134#define MC13XXX_REVISION_REVMETAL (0x07 << 0)
135#define MC13XXX_REVISION_REVFULL (0x03 << 3)
136#define MC13XXX_REVISION_ICID (0x07 << 6)
137#define MC13XXX_REVISION_FIN (0x03 << 9)
138#define MC13XXX_REVISION_FAB (0x03 << 11)
139#define MC13XXX_REVISION_ICIDCODE (0x3f << 13)
140
141#define MC13783_ADC1 44
142#define MC13783_ADC1_ADEN (1 << 0)
143#define MC13783_ADC1_RAND (1 << 1)
144#define MC13783_ADC1_ADSEL (1 << 3)
145#define MC13783_ADC1_ASC (1 << 20)
146#define MC13783_ADC1_ADTRIGIGN (1 << 21)
147
148#define MC13783_ADC2 45
149
150#define MC13XXX_NUMREGS 0x3f
151
152void mc13xxx_lock(struct mc13xxx *mc13xxx)
153{
154 if (!mutex_trylock(&mc13xxx->lock)) {
155 dev_dbg(&mc13xxx->spidev->dev, "wait for %s from %pf\n",
156 __func__, __builtin_return_address(0));
157
158 mutex_lock(&mc13xxx->lock);
159 }
160 dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
161 __func__, __builtin_return_address(0));
162}
163EXPORT_SYMBOL(mc13xxx_lock);
164
165void mc13xxx_unlock(struct mc13xxx *mc13xxx)
166{
167 dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
168 __func__, __builtin_return_address(0));
169 mutex_unlock(&mc13xxx->lock);
170}
171EXPORT_SYMBOL(mc13xxx_unlock);
172
173#define MC13XXX_REGOFFSET_SHIFT 25
174int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
175{
176 struct spi_transfer t;
177 struct spi_message m;
178 int ret;
179
180 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
181
182 if (offset > MC13XXX_NUMREGS)
183 return -EINVAL;
184
185 *val = offset << MC13XXX_REGOFFSET_SHIFT;
186
187 memset(&t, 0, sizeof(t));
188
189 t.tx_buf = val;
190 t.rx_buf = val;
191 t.len = sizeof(u32);
192
193 spi_message_init(&m);
194 spi_message_add_tail(&t, &m);
195
196 ret = spi_sync(mc13xxx->spidev, &m);
197
198 /* error in message.status implies error return from spi_sync */
199 BUG_ON(!ret && m.status);
200
201 if (ret)
202 return ret;
203
204 *val &= 0xffffff;
205
206 dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
207
208 return 0;
209}
210EXPORT_SYMBOL(mc13xxx_reg_read);
211
212int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
213{
214 u32 buf;
215 struct spi_transfer t;
216 struct spi_message m;
217 int ret;
218
219 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
220
221 dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
222
223 if (offset > MC13XXX_NUMREGS || val > 0xffffff)
224 return -EINVAL;
225
226 buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
227
228 memset(&t, 0, sizeof(t));
229
230 t.tx_buf = &buf;
231 t.rx_buf = &buf;
232 t.len = sizeof(u32);
233
234 spi_message_init(&m);
235 spi_message_add_tail(&t, &m);
236
237 ret = spi_sync(mc13xxx->spidev, &m);
238
239 BUG_ON(!ret && m.status);
240
241 if (ret)
242 return ret;
243
244 return 0;
245}
246EXPORT_SYMBOL(mc13xxx_reg_write);
247
248int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
249 u32 mask, u32 val)
250{
251 int ret;
252 u32 valread;
253
254 BUG_ON(val & ~mask);
255
256 ret = mc13xxx_reg_read(mc13xxx, offset, &valread);
257 if (ret)
258 return ret;
259
260 valread = (valread & ~mask) | val;
261
262 return mc13xxx_reg_write(mc13xxx, offset, valread);
263}
264EXPORT_SYMBOL(mc13xxx_reg_rmw);
265
266int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
267{
268 int ret;
269 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
270 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
271 u32 mask;
272
273 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
274 return -EINVAL;
275
276 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
277 if (ret)
278 return ret;
279
280 if (mask & irqbit)
281 /* already masked */
282 return 0;
283
284 return mc13xxx_reg_write(mc13xxx, offmask, mask | irqbit);
285}
286EXPORT_SYMBOL(mc13xxx_irq_mask);
287
288int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
289{
290 int ret;
291 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
292 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
293 u32 mask;
294
295 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
296 return -EINVAL;
297
298 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
299 if (ret)
300 return ret;
301
302 if (!(mask & irqbit))
303 /* already unmasked */
304 return 0;
305
306 return mc13xxx_reg_write(mc13xxx, offmask, mask & ~irqbit);
307}
308EXPORT_SYMBOL(mc13xxx_irq_unmask);
309
310int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
311 int *enabled, int *pending)
312{
313 int ret;
314 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
315 unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
316 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
317
318 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
319 return -EINVAL;
320
321 if (enabled) {
322 u32 mask;
323
324 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
325 if (ret)
326 return ret;
327
328 *enabled = mask & irqbit;
329 }
330
331 if (pending) {
332 u32 stat;
333
334 ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
335 if (ret)
336 return ret;
337
338 *pending = stat & irqbit;
339 }
340
341 return 0;
342}
343EXPORT_SYMBOL(mc13xxx_irq_status);
344
345int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq)
346{
347 unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
348 unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
349
350 BUG_ON(irq < 0 || irq >= MC13XXX_NUM_IRQ);
351
352 return mc13xxx_reg_write(mc13xxx, offstat, val);
353}
354EXPORT_SYMBOL(mc13xxx_irq_ack);
355
356int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
357 irq_handler_t handler, const char *name, void *dev)
358{
359 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
360 BUG_ON(!handler);
361
362 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
363 return -EINVAL;
364
365 if (mc13xxx->irqhandler[irq])
366 return -EBUSY;
367
368 mc13xxx->irqhandler[irq] = handler;
369 mc13xxx->irqdata[irq] = dev;
370
371 return 0;
372}
373EXPORT_SYMBOL(mc13xxx_irq_request_nounmask);
374
375int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
376 irq_handler_t handler, const char *name, void *dev)
377{
378 int ret;
379
380 ret = mc13xxx_irq_request_nounmask(mc13xxx, irq, handler, name, dev);
381 if (ret)
382 return ret;
383
384 ret = mc13xxx_irq_unmask(mc13xxx, irq);
385 if (ret) {
386 mc13xxx->irqhandler[irq] = NULL;
387 mc13xxx->irqdata[irq] = NULL;
388 return ret;
389 }
390
391 return 0;
392}
393EXPORT_SYMBOL(mc13xxx_irq_request);
394
395int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
396{
397 int ret;
398 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
399
400 if (irq < 0 || irq >= MC13XXX_NUM_IRQ || !mc13xxx->irqhandler[irq] ||
401 mc13xxx->irqdata[irq] != dev)
402 return -EINVAL;
403
404 ret = mc13xxx_irq_mask(mc13xxx, irq);
405 if (ret)
406 return ret;
407
408 mc13xxx->irqhandler[irq] = NULL;
409 mc13xxx->irqdata[irq] = NULL;
410
411 return 0;
412}
413EXPORT_SYMBOL(mc13xxx_irq_free);
414
415static inline irqreturn_t mc13xxx_irqhandler(struct mc13xxx *mc13xxx, int irq)
416{
417 return mc13xxx->irqhandler[irq](irq, mc13xxx->irqdata[irq]);
418}
419
420/*
421 * returns: number of handled irqs or negative error
422 * locking: holds mc13xxx->lock
423 */
424static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
425 unsigned int offstat, unsigned int offmask, int baseirq)
426{
427 u32 stat, mask;
428 int ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
429 int num_handled = 0;
430
431 if (ret)
432 return ret;
433
434 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
435 if (ret)
436 return ret;
437
438 while (stat & ~mask) {
439 int irq = __ffs(stat & ~mask);
440
441 stat &= ~(1 << irq);
442
443 if (likely(mc13xxx->irqhandler[baseirq + irq])) {
444 irqreturn_t handled;
445
446 handled = mc13xxx_irqhandler(mc13xxx, baseirq + irq);
447 if (handled == IRQ_HANDLED)
448 num_handled++;
449 } else {
450 dev_err(&mc13xxx->spidev->dev,
451 "BUG: irq %u but no handler\n",
452 baseirq + irq);
453
454 mask |= 1 << irq;
455
456 ret = mc13xxx_reg_write(mc13xxx, offmask, mask);
457 }
458 }
459
460 return num_handled;
461}
462
463static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
464{
465 struct mc13xxx *mc13xxx = data;
466 irqreturn_t ret;
467 int handled = 0;
468
469 mc13xxx_lock(mc13xxx);
470
471 ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT0,
472 MC13XXX_IRQMASK0, 0);
473 if (ret > 0)
474 handled = 1;
475
476 ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT1,
477 MC13XXX_IRQMASK1, 24);
478 if (ret > 0)
479 handled = 1;
480
481 mc13xxx_unlock(mc13xxx);
482
483 return IRQ_RETVAL(handled);
484}
485
486enum mc13xxx_id {
487 MC13XXX_ID_MC13783,
488 MC13XXX_ID_MC13892,
489 MC13XXX_ID_INVALID,
490};
491
492const char *mc13xxx_chipname[] = {
493 [MC13XXX_ID_MC13783] = "mc13783",
494 [MC13XXX_ID_MC13892] = "mc13892",
495};
496
497#define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask))
498static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
499{
500 u32 icid;
501 u32 revision;
502 const char *name;
503 int ret;
504
505 ret = mc13xxx_reg_read(mc13xxx, 46, &icid);
506 if (ret)
507 return ret;
508
509 icid = (icid >> 6) & 0x7;
510
511 switch (icid) {
512 case 2:
513 *id = MC13XXX_ID_MC13783;
514 name = "mc13783";
515 break;
516 case 7:
517 *id = MC13XXX_ID_MC13892;
518 name = "mc13892";
519 break;
520 default:
521 *id = MC13XXX_ID_INVALID;
522 break;
523 }
524
525 if (*id == MC13XXX_ID_MC13783 || *id == MC13XXX_ID_MC13892) {
526 ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
527 if (ret)
528 return ret;
529
530 dev_info(&mc13xxx->spidev->dev, "%s: rev: %d.%d, "
531 "fin: %d, fab: %d, icid: %d/%d\n",
532 mc13xxx_chipname[*id],
533 maskval(revision, MC13XXX_REVISION_REVFULL),
534 maskval(revision, MC13XXX_REVISION_REVMETAL),
535 maskval(revision, MC13XXX_REVISION_FIN),
536 maskval(revision, MC13XXX_REVISION_FAB),
537 maskval(revision, MC13XXX_REVISION_ICID),
538 maskval(revision, MC13XXX_REVISION_ICIDCODE));
539 }
540
541 if (*id != MC13XXX_ID_INVALID) {
542 const struct spi_device_id *devid =
543 spi_get_device_id(mc13xxx->spidev);
544 if (!devid || devid->driver_data != *id)
545 dev_warn(&mc13xxx->spidev->dev, "device id doesn't "
546 "match auto detection!\n");
547 }
548
549 return 0;
550}
551
552static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
553{
554 const struct spi_device_id *devid =
555 spi_get_device_id(mc13xxx->spidev);
556
557 if (!devid)
558 return NULL;
559
560 return mc13xxx_chipname[devid->driver_data];
561}
562
563#include <linux/mfd/mc13783.h>
564
565int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
566{
567 struct mc13xxx_platform_data *pdata =
568 dev_get_platdata(&mc13xxx->spidev->dev);
569
570 return pdata->flags;
571}
572EXPORT_SYMBOL(mc13xxx_get_flags);
573
574#define MC13783_ADC1_CHAN0_SHIFT 5
575#define MC13783_ADC1_CHAN1_SHIFT 8
576
577struct mc13xxx_adcdone_data {
578 struct mc13xxx *mc13xxx;
579 struct completion done;
580};
581
582static irqreturn_t mc13783_handler_adcdone(int irq, void *data)
583{
584 struct mc13xxx_adcdone_data *adcdone_data = data;
585
586 mc13xxx_irq_ack(adcdone_data->mc13xxx, irq);
587
588 complete_all(&adcdone_data->done);
589
590 return IRQ_HANDLED;
591}
592
593#define MC13783_ADC_WORKING (1 << 0)
594
595int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
596 unsigned int channel, unsigned int *sample)
597{
598 struct mc13xxx *mc13xxx = &mc13783->mc13xxx;
599 u32 adc0, adc1, old_adc0;
600 int i, ret;
601 struct mc13xxx_adcdone_data adcdone_data = {
602 .mc13xxx = mc13xxx,
603 };
604 init_completion(&adcdone_data.done);
605
606 dev_dbg(&mc13xxx->spidev->dev, "%s\n", __func__);
607
608 mc13xxx_lock(mc13xxx);
609
610 if (mc13783->adcflags & MC13783_ADC_WORKING) {
611 ret = -EBUSY;
612 goto out;
613 }
614
615 mc13783->adcflags |= MC13783_ADC_WORKING;
616
617 mc13xxx_reg_read(mc13xxx, MC13783_ADC0, &old_adc0);
618
619 adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
620 adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC;
621
622 if (channel > 7)
623 adc1 |= MC13783_ADC1_ADSEL;
624
625 switch (mode) {
626 case MC13783_ADC_MODE_TS:
627 adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 |
628 MC13783_ADC0_TSMOD1;
629 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
630 break;
631
632 case MC13783_ADC_MODE_SINGLE_CHAN:
633 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
634 adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
635 adc1 |= MC13783_ADC1_RAND;
636 break;
637
638 case MC13783_ADC_MODE_MULT_CHAN:
639 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
640 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
641 break;
642
643 default:
644 mc13783_unlock(mc13783);
645 return -EINVAL;
646 }
647
648 dev_dbg(&mc13783->mc13xxx.spidev->dev, "%s: request irq\n", __func__);
649 mc13xxx_irq_request(mc13xxx, MC13783_IRQ_ADCDONE,
650 mc13783_handler_adcdone, __func__, &adcdone_data);
651 mc13xxx_irq_ack(mc13xxx, MC13783_IRQ_ADCDONE);
652
653 mc13xxx_reg_write(mc13xxx, MC13783_ADC0, adc0);
654 mc13xxx_reg_write(mc13xxx, MC13783_ADC1, adc1);
655
656 mc13xxx_unlock(mc13xxx);
657
658 ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
659
660 if (!ret)
661 ret = -ETIMEDOUT;
662
663 mc13xxx_lock(mc13xxx);
664
665 mc13xxx_irq_free(mc13xxx, MC13783_IRQ_ADCDONE, &adcdone_data);
666
667 if (ret > 0)
668 for (i = 0; i < 4; ++i) {
669 ret = mc13xxx_reg_read(mc13xxx,
670 MC13783_ADC2, &sample[i]);
671 if (ret)
672 break;
673 }
674
675 if (mode == MC13783_ADC_MODE_TS)
676 /* restore TSMOD */
677 mc13xxx_reg_write(mc13xxx, MC13783_ADC0, old_adc0);
678
679 mc13783->adcflags &= ~MC13783_ADC_WORKING;
680out:
681 mc13xxx_unlock(mc13xxx);
682
683 return ret;
684}
685EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
686
687static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
688 const char *format, void *pdata, size_t pdata_size)
689{
690 char buf[30];
691 const char *name = mc13xxx_get_chipname(mc13xxx);
692
693 struct mfd_cell cell = {
694 .platform_data = pdata,
695 .data_size = pdata_size,
696 };
697
698 /* there is no asnprintf in the kernel :-( */
699 if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
700 return -E2BIG;
701
702 cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
703 if (!cell.name)
704 return -ENOMEM;
705
706 return mfd_add_devices(&mc13xxx->spidev->dev, -1, &cell, 1, NULL, 0);
707}
708
709static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
710{
711 return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
712}
713
714static int mc13xxx_probe(struct spi_device *spi)
715{
716 struct mc13xxx *mc13xxx;
717 struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
718 enum mc13xxx_id id;
719 int ret;
720
721 mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
722 if (!mc13xxx)
723 return -ENOMEM;
724
725 dev_set_drvdata(&spi->dev, mc13xxx);
726 spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
727 spi->bits_per_word = 32;
728 spi_setup(spi);
729
730 mc13xxx->spidev = spi;
731
732 mutex_init(&mc13xxx->lock);
733 mc13xxx_lock(mc13xxx);
734
735 ret = mc13xxx_identify(mc13xxx, &id);
736 if (ret || id == MC13XXX_ID_INVALID)
737 goto err_revision;
738
739 /* mask all irqs */
740 ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK0, 0x00ffffff);
741 if (ret)
742 goto err_mask;
743
744 ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK1, 0x00ffffff);
745 if (ret)
746 goto err_mask;
747
748 ret = request_threaded_irq(spi->irq, NULL, mc13xxx_irq_thread,
749 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
750
751 if (ret) {
752err_mask:
753err_revision:
754 mutex_unlock(&mc13xxx->lock);
755 dev_set_drvdata(&spi->dev, NULL);
756 kfree(mc13xxx);
757 return ret;
758 }
759
760 mc13xxx_unlock(mc13xxx);
761
762 if (pdata->flags & MC13XXX_USE_ADC)
763 mc13xxx_add_subdevice(mc13xxx, "%s-adc");
764
765 if (pdata->flags & MC13XXX_USE_CODEC)
766 mc13xxx_add_subdevice(mc13xxx, "%s-codec");
767
768 if (pdata->flags & MC13XXX_USE_REGULATOR) {
769 struct mc13xxx_regulator_platform_data regulator_pdata = {
770 .num_regulators = pdata->num_regulators,
771 .regulators = pdata->regulators,
772 };
773
774 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
775 &regulator_pdata, sizeof(regulator_pdata));
776 }
777
778 if (pdata->flags & MC13XXX_USE_RTC)
779 mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
780
781 if (pdata->flags & MC13XXX_USE_TOUCHSCREEN)
782 mc13xxx_add_subdevice(mc13xxx, "%s-ts");
783
784 if (pdata->flags & MC13XXX_USE_LED) {
785 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
786 pdata->leds, sizeof(*pdata->leds));
787 }
788
789 return 0;
790}
791
792static int __devexit mc13xxx_remove(struct spi_device *spi)
793{
794 struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
795
796 free_irq(mc13xxx->spidev->irq, mc13xxx);
797
798 mfd_remove_devices(&spi->dev);
799
800 return 0;
801}
802
803static const struct spi_device_id mc13xxx_device_id[] = {
804 {
805 .name = "mc13783",
806 .driver_data = MC13XXX_ID_MC13783,
807 }, {
808 .name = "mc13892",
809 .driver_data = MC13XXX_ID_MC13892,
810 }, {
811 /* sentinel */
812 }
813};
814
815static struct spi_driver mc13xxx_driver = {
816 .id_table = mc13xxx_device_id,
817 .driver = {
818 .name = "mc13xxx",
819 .bus = &spi_bus_type,
820 .owner = THIS_MODULE,
821 },
822 .probe = mc13xxx_probe,
823 .remove = __devexit_p(mc13xxx_remove),
824};
825
826static int __init mc13xxx_init(void)
827{
828 return spi_register_driver(&mc13xxx_driver);
829}
830subsys_initcall(mc13xxx_init);
831
832static void __exit mc13xxx_exit(void)
833{
834 spi_unregister_driver(&mc13xxx_driver);
835}
836module_exit(mc13xxx_exit);
837
838MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
839MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
840MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 14:14:11 -0500