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authorSamuel Ortiz <sameo@openedhand.com>2008-06-20 05:09:51 -0400
committerSamuel Ortiz <samuel@sortiz.org>2008-07-20 13:55:00 -0400
commit3b26bf17226f66bfd6cd4e36ac81f83fe994043a (patch)
treef619c0570a31cbb0cdd2e3c148bd66bb962b7b74 /drivers/mfd
parent1effe5bc6cfbac4506d7944d68dadbd29ad62645 (diff)
mfd: New asic3 gpio configuration code
The ASIC3 GPIO configuration code is a bit obscure and hardly readable. This patch changes it so that it is now more readable and understandable, by being more explicit. Signed-off-by: Samuel Ortiz <sameo@openedhand.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Diffstat (limited to 'drivers/mfd')
-rw-r--r--drivers/mfd/asic3.c99
1 files changed, 43 insertions, 56 deletions
diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c
index dfee0a2ba167..36b46ded1bff 100644
--- a/drivers/mfd/asic3.c
+++ b/drivers/mfd/asic3.c
@@ -465,69 +465,54 @@ static void asic3_gpio_set(struct gpio_chip *chip,
465 return; 465 return;
466} 466}
467 467
468static inline u32 asic3_get_gpio(struct asic3 *asic, unsigned int base, 468static int asic3_gpio_probe(struct platform_device *pdev,
469 unsigned int function) 469 u16 *gpio_config, int num)
470{ 470{
471 return asic3_read_register(asic, base + function);
472}
473
474static void asic3_set_gpio(struct asic3 *asic, unsigned int base,
475 unsigned int function, u32 bits, u32 val)
476{
477 unsigned long flags;
478
479 spin_lock_irqsave(&asic->lock, flags);
480 val |= (asic3_read_register(asic, base + function) & ~bits);
481
482 asic3_write_register(asic, base + function, val);
483 spin_unlock_irqrestore(&asic->lock, flags);
484}
485
486#define asic3_set_gpio_a(asic, fn, bits, val) \
487 asic3_set_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn, bits, val)
488#define asic3_set_gpio_b(asic, fn, bits, val) \
489 asic3_set_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn, bits, val)
490#define asic3_set_gpio_c(asic, fn, bits, val) \
491 asic3_set_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn, bits, val)
492#define asic3_set_gpio_d(asic, fn, bits, val) \
493 asic3_set_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn, bits, val)
494
495#define asic3_set_gpio_banks(asic, fn, bits, pdata, field) \
496 do { \
497 asic3_set_gpio_a((asic), fn, (bits), (pdata)->gpio_a.field); \
498 asic3_set_gpio_b((asic), fn, (bits), (pdata)->gpio_b.field); \
499 asic3_set_gpio_c((asic), fn, (bits), (pdata)->gpio_c.field); \
500 asic3_set_gpio_d((asic), fn, (bits), (pdata)->gpio_d.field); \
501 } while (0)
502
503
504static int asic3_gpio_probe(struct platform_device *pdev)
505{
506 struct asic3_platform_data *pdata = pdev->dev.platform_data;
507 struct asic3 *asic = platform_get_drvdata(pdev); 471 struct asic3 *asic = platform_get_drvdata(pdev);
472 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
473 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
474 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
475 int i;
508 476
477 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS);
478 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS);
479 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS);
480
481 /* Enable all GPIOs */
509 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff); 482 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff);
510 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff); 483 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff);
511 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff); 484 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff);
512 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff); 485 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff);
513 486
514 asic3_set_gpio_a(asic, SleepMask, 0xffff, 0xffff); 487 for (i = 0; i < num; i++) {
515 asic3_set_gpio_b(asic, SleepMask, 0xffff, 0xffff); 488 u8 alt, pin, dir, init, bank_num, bit_num;
516 asic3_set_gpio_c(asic, SleepMask, 0xffff, 0xffff); 489 u16 config = gpio_config[i];
517 asic3_set_gpio_d(asic, SleepMask, 0xffff, 0xffff); 490
518 491 pin = ASIC3_CONFIG_GPIO_PIN(config);
519 if (pdata) { 492 alt = ASIC3_CONFIG_GPIO_ALT(config);
520 asic3_set_gpio_banks(asic, Out, 0xffff, pdata, init); 493 dir = ASIC3_CONFIG_GPIO_DIR(config);
521 asic3_set_gpio_banks(asic, Direction, 0xffff, pdata, dir); 494 init = ASIC3_CONFIG_GPIO_INIT(config);
522 asic3_set_gpio_banks(asic, SleepMask, 0xffff, pdata, 495
523 sleep_mask); 496 bank_num = ASIC3_GPIO_TO_BANK(pin);
524 asic3_set_gpio_banks(asic, SleepOut, 0xffff, pdata, sleep_out); 497 bit_num = ASIC3_GPIO_TO_BIT(pin);
525 asic3_set_gpio_banks(asic, BattFaultOut, 0xffff, pdata, 498
526 batt_fault_out); 499 alt_reg[bank_num] |= (alt << bit_num);
527 asic3_set_gpio_banks(asic, SleepConf, 0xffff, pdata, 500 out_reg[bank_num] |= (init << bit_num);
528 sleep_conf); 501 dir_reg[bank_num] |= (dir << bit_num);
529 asic3_set_gpio_banks(asic, AltFunction, 0xffff, pdata, 502 }
530 alt_function); 503
504 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
505 asic3_write_register(asic,
506 ASIC3_BANK_TO_BASE(i) +
507 ASIC3_GPIO_Direction,
508 dir_reg[i]);
509 asic3_write_register(asic,
510 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_Out,
511 out_reg[i]);
512 asic3_write_register(asic,
513 ASIC3_BANK_TO_BASE(i) +
514 ASIC3_GPIO_AltFunction,
515 alt_reg[i]);
531 } 516 }
532 517
533 return gpiochip_add(&asic->gpio); 518 return gpiochip_add(&asic->gpio);
@@ -598,7 +583,9 @@ static int asic3_probe(struct platform_device *pdev)
598 asic->gpio.direction_input = asic3_gpio_direction_input; 583 asic->gpio.direction_input = asic3_gpio_direction_input;
599 asic->gpio.direction_output = asic3_gpio_direction_output; 584 asic->gpio.direction_output = asic3_gpio_direction_output;
600 585
601 ret = asic3_gpio_probe(pdev); 586 ret = asic3_gpio_probe(pdev,
587 pdata->gpio_config,
588 pdata->gpio_config_num);
602 if (ret < 0) { 589 if (ret < 0) {
603 printk(KERN_ERR "GPIO probe failed\n"); 590 printk(KERN_ERR "GPIO probe failed\n");
604 goto out_irq; 591 goto out_irq;