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authorMark Brown <broonie@opensource.wolfsonmicro.com>2013-01-26 23:07:30 -0500
committerSamuel Ortiz <sameo@linux.intel.com>2013-02-13 18:22:47 -0500
commit595e5bf75cea0664eeb63d8df20716f66f4aa459 (patch)
treebba4177dc314b147959e9cd809a64e268226863d /drivers/mfd/wm5102-tables.c
parent0cc9d08d3dca174ee712044e299732f26fdab22d (diff)
mfd: wm5102: Refresh register defaults
The WM5102 register defaults are not up to date with the current register map, synchronise them with those for current devices. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd/wm5102-tables.c')
-rw-r--r--drivers/mfd/wm5102-tables.c95
1 files changed, 33 insertions, 62 deletions
diff --git a/drivers/mfd/wm5102-tables.c b/drivers/mfd/wm5102-tables.c
index 6655c9e89e92..ff8f0804dde3 100644
--- a/drivers/mfd/wm5102-tables.c
+++ b/drivers/mfd/wm5102-tables.c
@@ -225,11 +225,9 @@ const struct regmap_irq_chip wm5102_irq = {
225static const struct reg_default wm5102_reg_default[] = { 225static const struct reg_default wm5102_reg_default[] = {
226 { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */ 226 { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
227 { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */ 227 { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
228 { 0x0000000D, 0x0000 }, /* R13 - Ctrl IF Status 1 */
229 { 0x00000016, 0x0000 }, /* R22 - Write Sequencer Ctrl 0 */ 228 { 0x00000016, 0x0000 }, /* R22 - Write Sequencer Ctrl 0 */
230 { 0x00000017, 0x0000 }, /* R23 - Write Sequencer Ctrl 1 */ 229 { 0x00000017, 0x0000 }, /* R23 - Write Sequencer Ctrl 1 */
231 { 0x00000018, 0x0000 }, /* R24 - Write Sequencer Ctrl 2 */ 230 { 0x00000018, 0x0000 }, /* R24 - Write Sequencer Ctrl 2 */
232 { 0x0000001A, 0x0000 }, /* R26 - Write Sequencer PROM */
233 { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */ 231 { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
234 { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */ 232 { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
235 { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */ 233 { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
@@ -244,12 +242,14 @@ static const struct reg_default wm5102_reg_default[] = {
244 { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */ 242 { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
245 { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */ 243 { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
246 { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */ 244 { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
247 { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 1 */ 245 { 0x00000066, 0x01FF }, /* R102 - Always On Triggers Sequence Select 1 */
248 { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 2 */ 246 { 0x00000067, 0x01FF }, /* R103 - Always On Triggers Sequence Select 2 */
249 { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 3 */ 247 { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 3 */
250 { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 4 */ 248 { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 4 */
251 { 0x0000006C, 0x01FF }, /* R108 - Always On Triggers Sequence Select 5 */ 249 { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 5 */
252 { 0x0000006D, 0x01FF }, /* R109 - Always On Triggers Sequence Select 6 */ 250 { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 6 */
251 { 0x0000006E, 0x01FF }, /* R110 - Trigger Sequence Select 32 */
252 { 0x0000006F, 0x01FF }, /* R111 - Trigger Sequence Select 33 */
253 { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */ 253 { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */
254 { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */ 254 { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
255 { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */ 255 { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
@@ -259,13 +259,14 @@ static const struct reg_default wm5102_reg_default[] = {
259 { 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */ 259 { 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */
260 { 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */ 260 { 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */
261 { 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */ 261 { 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */
262 { 0x00000100, 0x0001 }, /* R256 - Clock 32k 1 */ 262 { 0x00000100, 0x0002 }, /* R256 - Clock 32k 1 */
263 { 0x00000101, 0x0304 }, /* R257 - System Clock 1 */ 263 { 0x00000101, 0x0304 }, /* R257 - System Clock 1 */
264 { 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */ 264 { 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */
265 { 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */ 265 { 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */
266 { 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */ 266 { 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */
267 { 0x00000112, 0x0305 }, /* R274 - Async clock 1 */ 267 { 0x00000112, 0x0305 }, /* R274 - Async clock 1 */
268 { 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */ 268 { 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */
269 { 0x00000114, 0x0011 }, /* R276 - Async sample rate 2 */
269 { 0x00000149, 0x0000 }, /* R329 - Output system clock */ 270 { 0x00000149, 0x0000 }, /* R329 - Output system clock */
270 { 0x0000014A, 0x0000 }, /* R330 - Output async clock */ 271 { 0x0000014A, 0x0000 }, /* R330 - Output async clock */
271 { 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */ 272 { 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */
@@ -274,13 +275,14 @@ static const struct reg_default wm5102_reg_default[] = {
274 { 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */ 275 { 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */
275 { 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */ 276 { 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */
276 { 0x00000161, 0x0000 }, /* R353 - Dynamic Frequency Scaling 1 */ 277 { 0x00000161, 0x0000 }, /* R353 - Dynamic Frequency Scaling 1 */
277 { 0x00000171, 0x0000 }, /* R369 - FLL1 Control 1 */ 278 { 0x00000171, 0x0002 }, /* R369 - FLL1 Control 1 */
278 { 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */ 279 { 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */
279 { 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */ 280 { 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */
280 { 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */ 281 { 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */
281 { 0x00000175, 0x0004 }, /* R373 - FLL1 Control 5 */ 282 { 0x00000175, 0x0004 }, /* R373 - FLL1 Control 5 */
282 { 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */ 283 { 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */
283 { 0x00000177, 0x0181 }, /* R375 - FLL1 Loop Filter Test 1 */ 284 { 0x00000177, 0x0181 }, /* R375 - FLL1 Loop Filter Test 1 */
285 { 0x00000178, 0x0000 }, /* R376 - FLL1 NCO Test 0 */
284 { 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */ 286 { 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */
285 { 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */ 287 { 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */
286 { 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */ 288 { 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */
@@ -296,6 +298,7 @@ static const struct reg_default wm5102_reg_default[] = {
296 { 0x00000195, 0x0004 }, /* R405 - FLL2 Control 5 */ 298 { 0x00000195, 0x0004 }, /* R405 - FLL2 Control 5 */
297 { 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */ 299 { 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */
298 { 0x00000197, 0x0000 }, /* R407 - FLL2 Loop Filter Test 1 */ 300 { 0x00000197, 0x0000 }, /* R407 - FLL2 Loop Filter Test 1 */
301 { 0x00000198, 0x0000 }, /* R408 - FLL2 NCO Test 0 */
299 { 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */ 302 { 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */
300 { 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */ 303 { 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */
301 { 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */ 304 { 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */
@@ -311,8 +314,13 @@ static const struct reg_default wm5102_reg_default[] = {
311 { 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */ 314 { 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */
312 { 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */ 315 { 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */
313 { 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */ 316 { 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */
317 { 0x00000225, 0x0400 }, /* R549 - HP Ctrl 1L */
318 { 0x00000226, 0x0400 }, /* R550 - HP Ctrl 1R */
314 { 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */ 319 { 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */
315 { 0x0000029B, 0x0020 }, /* R667 - Headphone Detect 1 */ 320 { 0x0000029B, 0x0020 }, /* R667 - Headphone Detect 1 */
321 { 0x0000029C, 0x0000 }, /* R668 - Headphone Detect 2 */
322 { 0x0000029F, 0x0000 }, /* R671 - Headphone Detect Test */
323 { 0x000002A2, 0x0000 }, /* R674 - Micd Clamp control */
316 { 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */ 324 { 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */
317 { 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */ 325 { 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */
318 { 0x000002A5, 0x0000 }, /* R677 - Mic Detect 3 */ 326 { 0x000002A5, 0x0000 }, /* R677 - Mic Detect 3 */
@@ -343,53 +351,44 @@ static const struct reg_default wm5102_reg_default[] = {
343 { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */ 351 { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
344 { 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */ 352 { 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */
345 { 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */ 353 { 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */
346 { 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */ 354 { 0x00000410, 0x4080 }, /* R1040 - Output Path Config 1L */
347 { 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */ 355 { 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */
348 { 0x00000412, 0x0080 }, /* R1042 - DAC Volume Limit 1L */ 356 { 0x00000412, 0x0081 }, /* R1042 - DAC Volume Limit 1L */
349 { 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */ 357 { 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */
350 { 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */ 358 { 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */
351 { 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */ 359 { 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */
352 { 0x00000416, 0x0080 }, /* R1046 - DAC Volume Limit 1R */ 360 { 0x00000416, 0x0081 }, /* R1046 - DAC Volume Limit 1R */
353 { 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */ 361 { 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */
354 { 0x00000418, 0x0080 }, /* R1048 - Output Path Config 2L */ 362 { 0x00000418, 0x4080 }, /* R1048 - Output Path Config 2L */
355 { 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */ 363 { 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */
356 { 0x0000041A, 0x0080 }, /* R1050 - DAC Volume Limit 2L */ 364 { 0x0000041A, 0x0081 }, /* R1050 - DAC Volume Limit 2L */
357 { 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */ 365 { 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */
358 { 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */ 366 { 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */
359 { 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */ 367 { 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */
360 { 0x0000041E, 0x0080 }, /* R1054 - DAC Volume Limit 2R */ 368 { 0x0000041E, 0x0081 }, /* R1054 - DAC Volume Limit 2R */
361 { 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */ 369 { 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */
362 { 0x00000420, 0x0080 }, /* R1056 - Output Path Config 3L */ 370 { 0x00000420, 0x4080 }, /* R1056 - Output Path Config 3L */
363 { 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */ 371 { 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */
364 { 0x00000422, 0x0080 }, /* R1058 - DAC Volume Limit 3L */ 372 { 0x00000422, 0x0081 }, /* R1058 - DAC Volume Limit 3L */
365 { 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */ 373 { 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */
366 { 0x00000424, 0x0080 }, /* R1060 - Output Path Config 3R */ 374 { 0x00000428, 0xC000 }, /* R1064 - Output Path Config 4L */
367 { 0x00000425, 0x0180 }, /* R1061 - DAC Digital Volume 3R */
368 { 0x00000426, 0x0080 }, /* R1062 - DAC Volume Limit 3R */
369 { 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */
370 { 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */ 375 { 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */
371 { 0x0000042A, 0x0080 }, /* R1066 - Out Volume 4L */ 376 { 0x0000042A, 0x0081 }, /* R1066 - Out Volume 4L */
372 { 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */ 377 { 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */
373 { 0x0000042C, 0x0000 }, /* R1068 - Output Path Config 4R */
374 { 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */ 378 { 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */
375 { 0x0000042E, 0x0080 }, /* R1070 - Out Volume 4R */ 379 { 0x0000042E, 0x0081 }, /* R1070 - Out Volume 4R */
376 { 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */ 380 { 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */
377 { 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */ 381 { 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */
378 { 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */ 382 { 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */
379 { 0x00000432, 0x0080 }, /* R1074 - DAC Volume Limit 5L */ 383 { 0x00000432, 0x0081 }, /* R1074 - DAC Volume Limit 5L */
380 { 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */ 384 { 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */
381 { 0x00000434, 0x0000 }, /* R1076 - Output Path Config 5R */
382 { 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */ 385 { 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */
383 { 0x00000436, 0x0080 }, /* R1078 - DAC Volume Limit 5R */ 386 { 0x00000436, 0x0081 }, /* R1078 - DAC Volume Limit 5R */
384 { 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */ 387 { 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */
385 { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */ 388 { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
386 { 0x00000458, 0x0001 }, /* R1112 - Noise Gate Control */ 389 { 0x00000458, 0x0001 }, /* R1112 - Noise Gate Control */
387 { 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */ 390 { 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */
388 { 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */ 391 { 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */
389 { 0x000004DC, 0x0000 }, /* R1244 - DAC comp 1 */
390 { 0x000004DD, 0x0000 }, /* R1245 - DAC comp 2 */
391 { 0x000004DE, 0x0000 }, /* R1246 - DAC comp 3 */
392 { 0x000004DF, 0x0000 }, /* R1247 - DAC comp 4 */
393 { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */ 392 { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
394 { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */ 393 { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
395 { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */ 394 { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
@@ -417,7 +416,6 @@ static const struct reg_default wm5102_reg_default[] = {
417 { 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */ 416 { 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */
418 { 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */ 417 { 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */
419 { 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */ 418 { 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */
420 { 0x0000051B, 0x0000 }, /* R1307 - AIF1 Force Write */
421 { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */ 419 { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */
422 { 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */ 420 { 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */
423 { 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */ 421 { 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */
@@ -433,7 +431,6 @@ static const struct reg_default wm5102_reg_default[] = {
433 { 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */ 431 { 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */
434 { 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */ 432 { 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */
435 { 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */ 433 { 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */
436 { 0x0000055B, 0x0000 }, /* R1371 - AIF2 Force Write */
437 { 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */ 434 { 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */
438 { 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */ 435 { 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */
439 { 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */ 436 { 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */
@@ -449,7 +446,6 @@ static const struct reg_default wm5102_reg_default[] = {
449 { 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */ 446 { 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */
450 { 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */ 447 { 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */
451 { 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */ 448 { 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */
452 { 0x0000059B, 0x0000 }, /* R1435 - AIF3 Force Write */
453 { 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */ 449 { 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */
454 { 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */ 450 { 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */
455 { 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */ 451 { 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */
@@ -773,22 +769,6 @@ static const struct reg_default wm5102_reg_default[] = {
773 { 0x000008CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */ 769 { 0x000008CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */
774 { 0x000008CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */ 770 { 0x000008CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */
775 { 0x000008CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */ 771 { 0x000008CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */
776 { 0x000008D0, 0x0000 }, /* R2256 - DRC2LMIX Input 1 Source */
777 { 0x000008D1, 0x0080 }, /* R2257 - DRC2LMIX Input 1 Volume */
778 { 0x000008D2, 0x0000 }, /* R2258 - DRC2LMIX Input 2 Source */
779 { 0x000008D3, 0x0080 }, /* R2259 - DRC2LMIX Input 2 Volume */
780 { 0x000008D4, 0x0000 }, /* R2260 - DRC2LMIX Input 3 Source */
781 { 0x000008D5, 0x0080 }, /* R2261 - DRC2LMIX Input 3 Volume */
782 { 0x000008D6, 0x0000 }, /* R2262 - DRC2LMIX Input 4 Source */
783 { 0x000008D7, 0x0080 }, /* R2263 - DRC2LMIX Input 4 Volume */
784 { 0x000008D8, 0x0000 }, /* R2264 - DRC2RMIX Input 1 Source */
785 { 0x000008D9, 0x0080 }, /* R2265 - DRC2RMIX Input 1 Volume */
786 { 0x000008DA, 0x0000 }, /* R2266 - DRC2RMIX Input 2 Source */
787 { 0x000008DB, 0x0080 }, /* R2267 - DRC2RMIX Input 2 Volume */
788 { 0x000008DC, 0x0000 }, /* R2268 - DRC2RMIX Input 3 Source */
789 { 0x000008DD, 0x0080 }, /* R2269 - DRC2RMIX Input 3 Volume */
790 { 0x000008DE, 0x0000 }, /* R2270 - DRC2RMIX Input 4 Source */
791 { 0x000008DF, 0x0080 }, /* R2271 - DRC2RMIX Input 4 Volume */
792 { 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */ 772 { 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */
793 { 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */ 773 { 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */
794 { 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */ 774 { 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */
@@ -880,7 +860,7 @@ static const struct reg_default wm5102_reg_default[] = {
880 { 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */ 860 { 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */
881 { 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */ 861 { 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */
882 { 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */ 862 { 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */
883 { 0x00000D41, 0x0000 }, /* R3393 - ADSP2 IRQ0 */ 863 { 0x00000D50, 0x0000 }, /* R3408 - AOD wkup and trig */
884 { 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */ 864 { 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */
885 { 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */ 865 { 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */
886 { 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */ 866 { 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */
@@ -975,11 +955,6 @@ static const struct reg_default wm5102_reg_default[] = {
975 { 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */ 955 { 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */
976 { 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */ 956 { 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */
977 { 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */ 957 { 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */
978 { 0x00000E89, 0x0018 }, /* R3721 - DRC2 ctrl1 */
979 { 0x00000E8A, 0x0933 }, /* R3722 - DRC2 ctrl2 */
980 { 0x00000E8B, 0x0018 }, /* R3723 - DRC2 ctrl3 */
981 { 0x00000E8C, 0x0000 }, /* R3724 - DRC2 ctrl4 */
982 { 0x00000E8D, 0x0000 }, /* R3725 - DRC2 ctrl5 */
983 { 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */ 958 { 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */
984 { 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */ 959 { 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */
985 { 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */ 960 { 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */
@@ -990,16 +965,12 @@ static const struct reg_default wm5102_reg_default[] = {
990 { 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */ 965 { 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
991 { 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */ 966 { 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */
992 { 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */ 967 { 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */
993 { 0x00000EE3, 0x4000 }, /* R3811 - ASRC_RATE2 */
994 { 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */ 968 { 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */
995 { 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */ 969 { 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */
996 { 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */ 970 { 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */
997 { 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */ 971 { 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */
998 { 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */ 972 { 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */
999 { 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */ 973 { 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */
1000 { 0x00000EF6, 0x0000 }, /* R3830 - ISRC 3 CTRL 1 */
1001 { 0x00000EF7, 0x0000 }, /* R3831 - ISRC 3 CTRL 2 */
1002 { 0x00000EF8, 0x0000 }, /* R3832 - ISRC 3 CTRL 3 */
1003 { 0x00001100, 0x0010 }, /* R4352 - DSP1 Control 1 */ 974 { 0x00001100, 0x0010 }, /* R4352 - DSP1 Control 1 */
1004 { 0x00001101, 0x0000 }, /* R4353 - DSP1 Clocking 1 */ 975 { 0x00001101, 0x0000 }, /* R4353 - DSP1 Clocking 1 */
1005}; 976};
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 01:46:35 -0400