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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2014-05-06 04:46:10 -0400
committerLee Jones <lee.jones@linaro.org>2014-06-03 03:11:28 -0400
commitac8320c471e187d7fdc90f807199ff77c116a668 (patch)
tree19052d42fd12b3290a26a2d1c5f99aeba06a5d70 /drivers/mfd/twl6040.c
parenta58cc84cafa2376a2d5fcdb3d513327a2fb813c2 (diff)
mfd: twl6040: Correct HPPLL configuration for 19.2 and 38.4 MHz mclk
When the MCLK is 19.2 or 38.4 MHz the HPPLL need to be enabled and can be put in bypass mode. This will fix HPPLL use on boards with 19.2MHz mclk. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'drivers/mfd/twl6040.c')
-rw-r--r--drivers/mfd/twl6040.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/drivers/mfd/twl6040.c b/drivers/mfd/twl6040.c
index 12b314ea48dc..ae26d84b3a59 100644
--- a/drivers/mfd/twl6040.c
+++ b/drivers/mfd/twl6040.c
@@ -441,12 +441,9 @@ int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
441 TWL6040_HPLLENA; 441 TWL6040_HPLLENA;
442 break; 442 break;
443 case 19200000: 443 case 19200000:
444 /* 444 /* PLL enabled, bypass mode */
445 * PLL disabled 445 hppllctl |= TWL6040_MCLK_19200KHZ |
446 * (enable PLL if MCLK jitter quality 446 TWL6040_HPLLBP | TWL6040_HPLLENA;
447 * doesn't meet specification)
448 */
449 hppllctl |= TWL6040_MCLK_19200KHZ;
450 break; 447 break;
451 case 26000000: 448 case 26000000:
452 /* PLL enabled, active mode */ 449 /* PLL enabled, active mode */
@@ -454,9 +451,9 @@ int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
454 TWL6040_HPLLENA; 451 TWL6040_HPLLENA;
455 break; 452 break;
456 case 38400000: 453 case 38400000:
457 /* PLL enabled, active mode */ 454 /* PLL enabled, bypass mode */
458 hppllctl |= TWL6040_MCLK_38400KHZ | 455 hppllctl |= TWL6040_MCLK_38400KHZ |
459 TWL6040_HPLLENA; 456 TWL6040_HPLLBP | TWL6040_HPLLENA;
460 break; 457 break;
461 default: 458 default:
462 dev_err(twl6040->dev, 459 dev_err(twl6040->dev,