mfd: sec-core: Add support for S2MPU02 device

Add support for Samsung S2MPU02 PMIC device to the MFD sec-core driver. The S2MPU02 device includes PMIC/RTC/Clock devices. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
author: Chanwoo Choi <cw00.choi@samsung.com> 2014-06-25 03:14:44 -0400
committer: Lee Jones <lee.jones@linaro.org> 2014-07-09 09:58:11 -0400
commit: 54e8827d5f0e66d152ef63e7958030ef4880cd85 (patch)
tree: 6c8d1f67b3790c53cf00285334607ecc6a705a04 /drivers/mfd/sec-irq.c
parent: 10f9edaeaa30468194e1dcd0e47e59b012f4cf8b (diff)
1 files changed, 94 insertions, 16 deletions
diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c
index 654e2c1dbf7a..f9a57869e3ec 100644
--- a/drivers/mfd/sec-irq.c
+++ b/drivers/mfd/sec-irq.c
@@ -20,6 +20,7 @@
 #include <linux/mfd/samsung/irq.h>
 #include <linux/mfd/samsung/s2mps11.h>
 #include <linux/mfd/samsung/s2mps14.h>
+#include <linux/mfd/samsung/s2mpu02.h>
 #include <linux/mfd/samsung/s5m8763.h>
 #include <linux/mfd/samsung/s5m8767.h>
@@ -161,6 +162,77 @@ static const struct regmap_irq s2mps14_irqs[] = {
        },
 };
+static const struct regmap_irq s2mpu02_irqs[] = {
+        [S2MPU02_IRQ_PWRONF] = {
+                .reg_offset = 0,
+                .mask = S2MPS11_IRQ_PWRONF_MASK,
+        },
+        [S2MPU02_IRQ_PWRONR] = {
+                .reg_offset = 0,
+                .mask = S2MPS11_IRQ_PWRONR_MASK,
+        },
+        [S2MPU02_IRQ_JIGONBF] = {
+                .reg_offset = 0,
+                .mask = S2MPS11_IRQ_JIGONBF_MASK,
+        },
+        [S2MPU02_IRQ_JIGONBR] = {
+                .reg_offset = 0,
+                .mask = S2MPS11_IRQ_JIGONBR_MASK,
+        },
+        [S2MPU02_IRQ_ACOKBF] = {
+                .reg_offset = 0,
+                .mask = S2MPS11_IRQ_ACOKBF_MASK,
+        },
+        [S2MPU02_IRQ_ACOKBR] = {
+                .reg_offset = 0,
+                .mask = S2MPS11_IRQ_ACOKBR_MASK,
+        },
+        [S2MPU02_IRQ_PWRON1S] = {
+                .reg_offset = 0,
+                .mask = S2MPS11_IRQ_PWRON1S_MASK,
+        },
+        [S2MPU02_IRQ_MRB] = {
+                .reg_offset = 0,
+                .mask = S2MPS11_IRQ_MRB_MASK,
+        },
+        [S2MPU02_IRQ_RTC60S] = {
+                .reg_offset = 1,
+                .mask = S2MPS11_IRQ_RTC60S_MASK,
+        },
+        [S2MPU02_IRQ_RTCA1] = {
+                .reg_offset = 1,
+                .mask = S2MPS11_IRQ_RTCA1_MASK,
+        },
+        [S2MPU02_IRQ_RTCA0] = {
+                .reg_offset = 1,
+                .mask = S2MPS11_IRQ_RTCA0_MASK,
+        },
+        [S2MPU02_IRQ_SMPL] = {
+                .reg_offset = 1,
+                .mask = S2MPS11_IRQ_SMPL_MASK,
+        },
+        [S2MPU02_IRQ_RTC1S] = {
+                .reg_offset = 1,
+                .mask = S2MPS11_IRQ_RTC1S_MASK,
+        },
+        [S2MPU02_IRQ_WTSR] = {
+                .reg_offset = 1,
+                .mask = S2MPS11_IRQ_WTSR_MASK,
+        },
+        [S2MPU02_IRQ_INT120C] = {
+                .reg_offset = 2,
+                .mask = S2MPS11_IRQ_INT120C_MASK,
+        },
+        [S2MPU02_IRQ_INT140C] = {
+                .reg_offset = 2,
+                .mask = S2MPS11_IRQ_INT140C_MASK,
+        },
+        [S2MPU02_IRQ_TSD] = {
+                .reg_offset = 2,
+                .mask = S2MPS14_IRQ_TSD_MASK,
+        },
+};
 static const struct regmap_irq s5m8767_irqs[] = {
        [S5M8767_IRQ_PWRR] = {
                .reg_offset = 0,
@@ -327,6 +399,16 @@ static const struct regmap_irq_chip s2mps14_irq_chip = {
        .ack_base = S2MPS14_REG_INT1,
 };
+static const struct regmap_irq_chip s2mpu02_irq_chip = {
+        .name = "s2mpu02",
+        .irqs = s2mpu02_irqs,
+        .num_irqs = ARRAY_SIZE(s2mpu02_irqs),
+        .num_regs = 3,
+        .status_base = S2MPU02_REG_INT1,
+        .mask_base = S2MPU02_REG_INT1M,
+        .ack_base = S2MPU02_REG_INT1,
+};
 static const struct regmap_irq_chip s5m8767_irq_chip = {
        .name = "s5m8767",
        .irqs = s5m8767_irqs,
@@ -351,6 +433,7 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic)
 {
        int ret = 0;
        int type = sec_pmic->device_type;
+        const struct regmap_irq_chip *sec_irq_chip;
        if (!sec_pmic->irq) {
                dev_warn(sec_pmic->dev,
@@ -361,28 +444,19 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic)
        switch (type) {
        case S5M8763X:
-                ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
+                sec_irq_chip = &s5m8763_irq_chip;
-                                  IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
-                                  sec_pmic->irq_base, &s5m8763_irq_chip,
-                                  &sec_pmic->irq_data);
                break;
        case S5M8767X:
-                ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
+                sec_irq_chip = &s5m8767_irq_chip;
-                                  IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
-                                  sec_pmic->irq_base, &s5m8767_irq_chip,
-                                  &sec_pmic->irq_data);
                break;
        case S2MPS11X:
-                ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
+                sec_irq_chip = &s2mps11_irq_chip;
-                                  IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
-                                  sec_pmic->irq_base, &s2mps11_irq_chip,
-                                  &sec_pmic->irq_data);
                break;
        case S2MPS14X:
-                ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
+                sec_irq_chip = &s2mps14_irq_chip;
-                                  IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+                break;
-                                  sec_pmic->irq_base, &s2mps14_irq_chip,
+        case S2MPU02:
-                                  &sec_pmic->irq_data);
+                sec_irq_chip = &s2mpu02_irq_chip;
                break;
        default:
                dev_err(sec_pmic->dev, "Unknown device type %lu\n",
@@ -390,6 +464,10 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic)
                return -EINVAL;
        }
+        ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
+                          IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+                          sec_pmic->irq_base, sec_irq_chip,
+                          &sec_pmic->irq_data);
        if (ret != 0) {
                dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
                return ret;
author	Chanwoo Choi <cw00.choi@samsung.com>	2014-06-25 03:14:44 -0400
committer	Lee Jones <lee.jones@linaro.org>	2014-07-09 09:58:11 -0400
commit	54e8827d5f0e66d152ef63e7958030ef4880cd85 (patch)
tree	6c8d1f67b3790c53cf00285334607ecc6a705a04 /drivers/mfd/sec-irq.c
parent	10f9edaeaa30468194e1dcd0e47e59b012f4cf8b (diff)

diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c index 654e2c1dbf7a..f9a57869e3ec 100644 --- a/drivers/mfd/sec-irq.c +++ b/drivers/mfd/sec-irq.c
@@ -20,6 +20,7 @@
20	#include <linux/mfd/samsung/irq.h>	20	#include <linux/mfd/samsung/irq.h>
21	#include <linux/mfd/samsung/s2mps11.h>	21	#include <linux/mfd/samsung/s2mps11.h>
22	#include <linux/mfd/samsung/s2mps14.h>	22	#include <linux/mfd/samsung/s2mps14.h>
		23	#include <linux/mfd/samsung/s2mpu02.h>
23	#include <linux/mfd/samsung/s5m8763.h>	24	#include <linux/mfd/samsung/s5m8763.h>
24	#include <linux/mfd/samsung/s5m8767.h>	25	#include <linux/mfd/samsung/s5m8767.h>
25		26
@@ -161,6 +162,77 @@ static const struct regmap_irq s2mps14_irqs[] = {
161	},	162	},
162	};	163	};
163		164
		165	static const struct regmap_irq s2mpu02_irqs[] = {
		166	[S2MPU02_IRQ_PWRONF] = {
		167	.reg_offset = 0,
		168	.mask = S2MPS11_IRQ_PWRONF_MASK,
		169	},
		170	[S2MPU02_IRQ_PWRONR] = {
		171	.reg_offset = 0,
		172	.mask = S2MPS11_IRQ_PWRONR_MASK,
		173	},
		174	[S2MPU02_IRQ_JIGONBF] = {
		175	.reg_offset = 0,
		176	.mask = S2MPS11_IRQ_JIGONBF_MASK,
		177	},
		178	[S2MPU02_IRQ_JIGONBR] = {
		179	.reg_offset = 0,
		180	.mask = S2MPS11_IRQ_JIGONBR_MASK,
		181	},
		182	[S2MPU02_IRQ_ACOKBF] = {
		183	.reg_offset = 0,
		184	.mask = S2MPS11_IRQ_ACOKBF_MASK,
		185	},
		186	[S2MPU02_IRQ_ACOKBR] = {
		187	.reg_offset = 0,
		188	.mask = S2MPS11_IRQ_ACOKBR_MASK,
		189	},
		190	[S2MPU02_IRQ_PWRON1S] = {
		191	.reg_offset = 0,
		192	.mask = S2MPS11_IRQ_PWRON1S_MASK,
		193	},
		194	[S2MPU02_IRQ_MRB] = {
		195	.reg_offset = 0,
		196	.mask = S2MPS11_IRQ_MRB_MASK,
		197	},
		198	[S2MPU02_IRQ_RTC60S] = {
		199	.reg_offset = 1,
		200	.mask = S2MPS11_IRQ_RTC60S_MASK,
		201	},
		202	[S2MPU02_IRQ_RTCA1] = {
		203	.reg_offset = 1,
		204	.mask = S2MPS11_IRQ_RTCA1_MASK,
		205	},
		206	[S2MPU02_IRQ_RTCA0] = {
		207	.reg_offset = 1,
		208	.mask = S2MPS11_IRQ_RTCA0_MASK,
		209	},
		210	[S2MPU02_IRQ_SMPL] = {
		211	.reg_offset = 1,
		212	.mask = S2MPS11_IRQ_SMPL_MASK,
		213	},
		214	[S2MPU02_IRQ_RTC1S] = {
		215	.reg_offset = 1,
		216	.mask = S2MPS11_IRQ_RTC1S_MASK,
		217	},
		218	[S2MPU02_IRQ_WTSR] = {
		219	.reg_offset = 1,
		220	.mask = S2MPS11_IRQ_WTSR_MASK,
		221	},
		222	[S2MPU02_IRQ_INT120C] = {
		223	.reg_offset = 2,
		224	.mask = S2MPS11_IRQ_INT120C_MASK,
		225	},
		226	[S2MPU02_IRQ_INT140C] = {
		227	.reg_offset = 2,
		228	.mask = S2MPS11_IRQ_INT140C_MASK,
		229	},
		230	[S2MPU02_IRQ_TSD] = {
		231	.reg_offset = 2,
		232	.mask = S2MPS14_IRQ_TSD_MASK,
		233	},
		234	};
		235
164	static const struct regmap_irq s5m8767_irqs[] = {	236	static const struct regmap_irq s5m8767_irqs[] = {
165	[S5M8767_IRQ_PWRR] = {	237	[S5M8767_IRQ_PWRR] = {
166	.reg_offset = 0,	238	.reg_offset = 0,
@@ -327,6 +399,16 @@ static const struct regmap_irq_chip s2mps14_irq_chip = {
327	.ack_base = S2MPS14_REG_INT1,	399	.ack_base = S2MPS14_REG_INT1,
328	};	400	};
329		401
		402	static const struct regmap_irq_chip s2mpu02_irq_chip = {
		403	.name = "s2mpu02",
		404	.irqs = s2mpu02_irqs,
		405	.num_irqs = ARRAY_SIZE(s2mpu02_irqs),
		406	.num_regs = 3,
		407	.status_base = S2MPU02_REG_INT1,
		408	.mask_base = S2MPU02_REG_INT1M,
		409	.ack_base = S2MPU02_REG_INT1,
		410	};
		411
330	static const struct regmap_irq_chip s5m8767_irq_chip = {	412	static const struct regmap_irq_chip s5m8767_irq_chip = {
331	.name = "s5m8767",	413	.name = "s5m8767",
332	.irqs = s5m8767_irqs,	414	.irqs = s5m8767_irqs,
@@ -351,6 +433,7 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic)
351	{	433	{
352	int ret = 0;	434	int ret = 0;
353	int type = sec_pmic->device_type;	435	int type = sec_pmic->device_type;
		436	const struct regmap_irq_chip *sec_irq_chip;
354		437
355	if (!sec_pmic->irq) {	438	if (!sec_pmic->irq) {
356	dev_warn(sec_pmic->dev,	439	dev_warn(sec_pmic->dev,
@@ -361,28 +444,19 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic)
361		444
362	switch (type) {	445	switch (type) {
363	case S5M8763X:	446	case S5M8763X:
364	ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,	447	sec_irq_chip = &s5m8763_irq_chip;
365	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
366	sec_pmic->irq_base, &s5m8763_irq_chip,
367	&sec_pmic->irq_data);
368	break;	448	break;
369	case S5M8767X:	449	case S5M8767X:
370	ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,	450	sec_irq_chip = &s5m8767_irq_chip;
371	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
372	sec_pmic->irq_base, &s5m8767_irq_chip,
373	&sec_pmic->irq_data);
374	break;	451	break;
375	case S2MPS11X:	452	case S2MPS11X:
376	ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,	453	sec_irq_chip = &s2mps11_irq_chip;
377	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
378	sec_pmic->irq_base, &s2mps11_irq_chip,
379	&sec_pmic->irq_data);
380	break;	454	break;
381	case S2MPS14X:	455	case S2MPS14X:
382	ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,	456	sec_irq_chip = &s2mps14_irq_chip;
383	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,	457	break;
384	sec_pmic->irq_base, &s2mps14_irq_chip,	458	case S2MPU02:
385	&sec_pmic->irq_data);	459	sec_irq_chip = &s2mpu02_irq_chip;
386	break;	460	break;
387	default:	461	default:
388	dev_err(sec_pmic->dev, "Unknown device type %lu\n",	462	dev_err(sec_pmic->dev, "Unknown device type %lu\n",
@@ -390,6 +464,10 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic)
390	return -EINVAL;	464	return -EINVAL;
391	}	465	}
392		466
		467	ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
		468	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
		469	sec_pmic->irq_base, sec_irq_chip,
		470	&sec_pmic->irq_data);
393	if (ret != 0) {	471	if (ret != 0) {
394	dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);	472	dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
395	return ret;	473	return ret;