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authorRoger Quadros <rogerq@ti.com>2012-11-12 09:32:01 -0500
committerRoger Quadros <rogerq@ti.com>2013-02-13 06:22:53 -0500
commitc4df00aed9e2e6e3ab094b4bb8b9ecb64cf8c70e (patch)
tree8ea1c45e344315e8371c74b06d2e328454d00128 /drivers/mfd/omap-usb-host.c
parentc6cd087ed058f8a7dfe1997cc51fdf8005e25a03 (diff)
mfd: omap-usb-host: clean up omap_usbhs_init()
We split initializing revision 1 and revision 2 into different functions. Initialization is now done dynamically so that only the number of ports available on the system are initialized. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/mfd/omap-usb-host.c')
-rw-r--r--drivers/mfd/omap-usb-host.c129
1 files changed, 81 insertions, 48 deletions
diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
index 0740c6856b51..7f9c38675d91 100644
--- a/drivers/mfd/omap-usb-host.c
+++ b/drivers/mfd/omap-usb-host.c
@@ -358,6 +358,75 @@ static int usbhs_runtime_suspend(struct device *dev)
358 return 0; 358 return 0;
359} 359}
360 360
361static unsigned omap_usbhs_rev1_hostconfig(struct usbhs_hcd_omap *omap,
362 unsigned reg)
363{
364 struct usbhs_omap_platform_data *pdata = omap->pdata;
365 int i;
366
367 for (i = 0; i < omap->nports; i++) {
368 switch (pdata->port_mode[i]) {
369 case OMAP_USBHS_PORT_MODE_UNUSED:
370 reg &= ~(OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS << i);
371 break;
372 case OMAP_EHCI_PORT_MODE_PHY:
373 if (pdata->single_ulpi_bypass)
374 break;
375
376 if (i == 0)
377 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
378 else
379 reg &= ~(OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
380 << (i-1));
381 break;
382 default:
383 if (pdata->single_ulpi_bypass)
384 break;
385
386 if (i == 0)
387 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
388 else
389 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
390 << (i-1);
391 break;
392 }
393 }
394
395 if (pdata->single_ulpi_bypass) {
396 /* bypass ULPI only if none of the ports use PHY mode */
397 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
398
399 for (i = 0; i < omap->nports; i++) {
400 if (is_ehci_phy_mode(pdata->port_mode[i])) {
401 reg &= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
402 break;
403 }
404 }
405 }
406
407 return reg;
408}
409
410static unsigned omap_usbhs_rev2_hostconfig(struct usbhs_hcd_omap *omap,
411 unsigned reg)
412{
413 struct usbhs_omap_platform_data *pdata = omap->pdata;
414 int i;
415
416 for (i = 0; i < omap->nports; i++) {
417 /* Clear port mode fields for PHY mode */
418 reg &= ~(OMAP4_P1_MODE_CLEAR << 2 * i);
419
420 if (is_ehci_tll_mode(pdata->port_mode[i]) ||
421 (is_ohci_port(pdata->port_mode[i])))
422 reg |= OMAP4_P1_MODE_TLL << 2 * i;
423 else if (is_ehci_hsic_mode(pdata->port_mode[i]))
424 reg |= OMAP4_P1_MODE_HSIC << 2 * i;
425 }
426
427 return reg;
428}
429
361static void omap_usbhs_init(struct device *dev) 430static void omap_usbhs_init(struct device *dev)
362{ 431{
363 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); 432 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
@@ -389,54 +458,18 @@ static void omap_usbhs_init(struct device *dev)
389 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; 458 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
390 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; 459 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
391 460
392 if (is_omap_usbhs_rev1(omap)) { 461 switch (omap->usbhs_rev) {
393 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) 462 case OMAP_USBHS_REV1:
394 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; 463 omap_usbhs_rev1_hostconfig(omap, reg);
395 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) 464 break;
396 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; 465
397 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) 466 case OMAP_USBHS_REV2:
398 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; 467 omap_usbhs_rev2_hostconfig(omap, reg);
399 468 break;
400 /* Bypass the TLL module for PHY mode operation */ 469
401 if (pdata->single_ulpi_bypass) { 470 default: /* newer revisions */
402 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n"); 471 omap_usbhs_rev2_hostconfig(omap, reg);
403 if (is_ehci_phy_mode(pdata->port_mode[0]) || 472 break;
404 is_ehci_phy_mode(pdata->port_mode[1]) ||
405 is_ehci_phy_mode(pdata->port_mode[2]))
406 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
407 else
408 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
409 } else {
410 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
411 if (is_ehci_phy_mode(pdata->port_mode[0]))
412 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
413 else
414 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
415 if (is_ehci_phy_mode(pdata->port_mode[1]))
416 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
417 else
418 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
419 if (is_ehci_phy_mode(pdata->port_mode[2]))
420 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
421 else
422 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
423 }
424 } else if (is_omap_usbhs_rev2(omap)) {
425 /* Clear port mode fields for PHY mode*/
426 reg &= ~OMAP4_P1_MODE_CLEAR;
427 reg &= ~OMAP4_P2_MODE_CLEAR;
428
429 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
430 (is_ohci_port(pdata->port_mode[0])))
431 reg |= OMAP4_P1_MODE_TLL;
432 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
433 reg |= OMAP4_P1_MODE_HSIC;
434
435 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
436 (is_ohci_port(pdata->port_mode[1])))
437 reg |= OMAP4_P2_MODE_TLL;
438 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
439 reg |= OMAP4_P2_MODE_HSIC;
440 } 473 }
441 474
442 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); 475 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);